S3882P Semiconductor Current Mode PWM Controller Descriptions The S3882 is fixed PWM controller for Off-line and DC-DC converter applications. The internal circuits include UVLO, low start up current circuit, temperature compensated reference, high gain error amplifier, current sensing comparator, and high current totempole output for driving a power MOSFET. Also S3882 provide low start up current below 0.3mA and short shutdown delay Time typical 100nsec. S3882 have UVLO threshold of 16V(on) and 10V(off). . Features • Low start up current < 0.3mA • Operating range up to 500KHz • Cycle by cycle current limiting • Under Voltage Lock Out with hysteresis • Short shutdown delay time ; typical 100nsec • High current totempole output • Output swing limiting : 22V Ordering Information Type NO. S3882P Marking S3882P Package Code DIP-8 Outline Dimensions unit : mm PIN Connections 1. Output / Compensation 2. Voltage feedback. Input 3. Current sense Input 4. Rt/Ct 5. GND 6. Output 7. Vcc 8. Vref KSI-L008-000 1 S3882P Absolute Maximum Ratings Ta=25°C Characteristic Symbol Ratings Unit Supply Voltage Vcc 28 V Output Current Io 1 A Vi(ana) -0.3 to 6.3 V Isink(EA) 10 mA Pd 1 W Analog Inputs Error Amp. Output Sink current Power Dissipation Electrical Characteristics (Vcc=15V, Rt=10Kohm,Ct=3.3nF, Ta=0℃ to 70℃, Unless otherwise specified) Characteristic Symbol Test Condition Min. Typ. Max. Unit 1. Reference Section Output Voltage Vref Tj=25℃, Io=1mA 4.91 5.00 5.09 V Line Regulation Δ Vref 12V ≤ VCC ≤ 25V - 6 20 mV Load Regulation Δ Vref 1mA ≤ IO ≤ 20mA - 6 25 mV Isc Ta=25°C -180 -100 - mA Initial Accuracy fOSC Tj=25℃ 47 52 57 KHz Voltage Stability △f /△V - 0.2 1.0 % Oscillator Voltage VOSC Vpin4, peak to peak 1.4 1.7 1.8 V Discharge Current Idischarge Tj=25°C, Pin4=2V 7.8 8.3 8.8 mA Output Short Current 2. Oscillator Section 12V ≤ VCC ≤ 25V 3. Error Amp Section Input Voltage V2 VPIN1=2.5V 2.42 2.50 2.58 V Input Bias Current Ib - -2.0 -0.3 - ㎂ Open Loop Voltage Gain AVO1 2V ≤ VO ≤ 4V 65 90 - ㏈ Unity Gain Bandwidth GBW Tj=25°C 0.7 1 - MHz VCC=12V to 25V 60 70 - ㏈ 2 6 - mA -0.8 -0.5 mA PSRR Output Sink Current Output Source Current PSRR1 ISINK ISOURCE VPIN2=2.7V, VPIN1=1.1V VPIN2=2.3V, VPIN1=5V Output High Voltage VOH Vpin2=2.3V, R1=15 ㏀ to GN 5 6 - V Output Low Voltage VOL VPIN2=2.3V, R1=15 ㏀ to PIN8 - 0.8 1.1 V GV - 2.85 3.0 3.15 V/V 0.9 1.0 1.1 V - 70 - ㏈ -10 -2 - ㎂ - 100 200 nS 4. Current Sense Section Gain Maximum Input Signal Vi(MaX) VPIN 1=5V PSRR PSRR2 12V ≤ VCC ≤ 25V Input Bias Current Delay to Output I bias Td VPIN 3=0V to 2V KSI-L008-000 2 S3882P Electrical Characteristics(continued) (Vcc=15V, Rt=10Kohm, Ct=3.3nF, Ta=0℃to 70℃, Unless otherwise specified) Characteristic Symbol Test Condition Min. Typ. Max. Unit 5. Output Section Output Low Level1 VOL1 Isink=20mA - 0.1 0.4 V Output Low Level2 VOL2 Isink=200mA - 1.5 2.0 V Output High Level1 VOH1 Isource=20mA 13.0 13.5 - V Output High Level2 VOH2 Isource=200mA 12.0 13.5 - V Rise Time tr Tj=25°C, C1=1nF - 40 100 nS Fall Time tf Tj=25°C, C1=1nF - 40 100 nS Vcc=27V, C1=1nF - 22 - V 15 16 17 V 9 10 11 V Out Volt. Swing Limit Volim 6. Under Voltage Lockout Section Start Threshold Vth - Min. Operating Voltage VtL After turn on 7.PWM Section Maximum Duty Cycle Dmax - 94 96 100 % Minimum Duty Cycle Dmin - - - 0 % Start-Up Current Ist - - 0.2 0.4 mA Operating Supply Current ICC Vpin2=Vpin3=0V - 11 17 mA ICC=25mA - 29 - V 8.Total Standby Section VCC Zener Voltage VZ NOTE: Adjust Vcc above the the start threshold before setting at 15V Block Diagram 7 Vcc 5 GND 29V Vref 5V V ref 8 Set/ Re s e t UV LO LO G IC In t e r n al Bi as PWR Vc 1/2 V r e f Er r or Amp Vfb 2 + - C.S Comp 1/3 7 PWM LATCH R Output 22V 6 1V S Com 1 PWR GND 5 C.S 3 Rt/Ct 4 Os c i l l at or KSI-L008-000 3 S3882P Information in Using IC 1. Under voltage Lockout To prevent erratic output behavior which activating V cc 7 the power switch with extraneous leakage currents, O N /O F F C O M M A N D T O R ES ET O F IC during under voltage lockout. Output(pin6) should be shunted to ground with a bleeder resister. V o n -16V V o f f -10V The Vcc comparator upper and lower threshold are Icc 16V/10V. The large hysteresis and low start up currents makes it ideally suited in off-line converter application where efficient bootstrap start-up <17mA techniques are required. <1mA V cc 16V 10V 2. Oscillator Waveforms and Maximum Duty Cycle The oscillator frequency is programmed by the values LARGE Rt SMALL Ct Vpin4 8 selected for the timing components Rt and Ct. Ct is charged from 5V, Vref, through resistor Rt to Rt INTERNAL CLOCK 4 Ct SMALL Rt LARGE Ct Vpin4 5 INTERNAL CLOCK approximately 2.8V and discharged to 1.2V by an internal current sink. During the discharge of Ct, the oscillator generates an internal blanking pulse and the center input NOR gate high. This makes output to be in a low state and control the amount of output dead time. 3. Error AMP Configuration 2.50V Error amp output(Pin1) is provided for external loop + 0.5mA compensation and error amp can source or sink up to 0.5mA. The non-inverting input is internally biased at 2.5V and is V in Zt 2 - not pinned out. The converter output voltage is typically divided down and monitored by the inverting input(pin2). COMP Zf 1 KSI-L008-000 4 S3882P 4. Current Sense Circuit ER R O R A MP 2R Iβ R IV 1 R (V p i n 1 - 2V b e ) CUR R ENT S E NS E C O MP A R A T O R CO MP Ip e a k = R 3R x R s 3 C CUR R E NT S ENS E G ND Rs 5 A normal operating conditions occurs when the power supply output is overloaded or if output voltage to 1.0V Therefore the maximum peak switch current is lpk(max)=1.0V/Rs, and under the normal operating conditions the peak inductor current controlled by the voltage at pin1. 5. Shutdown Techniques 4.7K 8 V 3 4.7K 1 RE F CO MP accomplished by two methods; ISEN SE either raise pin3 above 1V or pull 5.00 S HUT DO W N Shutdown of the S3882 can be pin1 below a voltage two diodes S HUT DO W N drops above ground. Either causes T O CUR R E NT S E NS E R ES I S T O R the output of the PWM method comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which turn off, allowing the SCR to reset. KSI-L008-000 5 S3882P 6. Open Loop Test V REF RT 2N2222 4.7K V cc 100K I SENSE ADJUST 2 V in 3 I SENSE 4 R T /CT S3882 ERROR 1K AMP ADJUST 4.7K V REF 5 1 COMP V cc 6 OUTPUT 7 GND 0.1uF 0.1uF 1K/1W OUTPUT 8 GROUND High peak currents associated with capacitive leads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to Pin5 in a single point ground. The transistor and 5 ㏀ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Pin 3. 7.Slope Compensation V A fraction of the oscillator ramp can be resistively 0.1u F RE F 8 summed with the current sense signal to provide RT R T /C T 4 CT slope compensation for converters requiring duty cycle over 50%. Note that capacitor C, forms a R1 R2 I SEN SE I SEN SE 3 C filter with R2 to suppress the leading edge switch spikes. R SEN SE KSI-L008-000 6 S3882P Electrical Characteristic Curves OUTPUT DEAD-TIME vs. OSCILLATOR FREQUENCY TIMING RESISTOR vs. OSCILLATOR FREQUENCY 80 V c c =15V Ta = 25o C 50 50 5.0n F 2.0n F R T TIMING RESISTOR (KΩ) %DT PERCENT OUTPUT DEAD-TIME 100 1.0n F 20 Ct =10n F 500pF 10 5.0 200pF 100pF 2.0 1.0 10K 20K 50K 100K 200K 500K 1.0M 500pF 20 200pF 8.0 5.0 2.0 V c c =15V Ta = 25o C 0.8 10K 20K 2.0n F 1.0n F C T =10n F 50K 100K 200K 500K 1.0M f OSC OS CILLATOR FREQUENCY (KHz ) f OSC OS CILLATOR FREQUENCY (KHz ) Error Amplifier Open-Loop Frequency Response Output Saturation Characteristics 0 80 -45 60 φ 40 -90 o ) 20 -135 AV 0 SATURATION VOLTAGE (V) 4 PHASE ( VOLTAGE GAIN (dB) 100pF 5.0n F Vcc=15V Ta = 25o C 3 Ta=-55o C 2 SOURCE SAT(Vcc-VOH) 1 -180 SINK SAT(VOL) 0 10 100 1K 10K 100K 1M 10M 0.1 0.2 0.3 0.4 0.5 0.7 1 2 3 4 5 7 10 OUTPUT CURRENT SOURCE OR SINK (A) FREQUENCY (Hz) KSI-L008-000 7