SP8503, SP8505, SP8510 12-Bit Sampling A/D Converters ■ 3µs, 5µs or 10µs Sample/Conversion Time ■ Standard ±10V and ±5V Input ■ No Missing Codes Over Temperature ■ AC Performance Over Temperature 71.5dB Signal–to–Noise Ratio at Nyquist 85dB Spurious–free Dynamic Range at 49kHz –81dB Total Harmonic Distortion at 49kHz ■ Internal Sample/Hold, Reference, Clock, and 3-State Outputs ■ Low Power Dissipation: 90mW ■ 28–Pin Narrow PDIP and SOIC DESCRIPTION… The SP85XX Series are complete 12-bit sampling A/D converters using state–of–the–art CMOS structures. They contain a complete 12–bit successive approximation A/D converter with internal sample/hold, reference, clock, digital interface for microprocessor control, and three–state output drivers. Power dissipation is only 90mW. AC and DC performance are completely specified. Sampling/conversion rates of 3µs, 5µs and 10µs are offered. CS R/C HBE Control Logic Clock Output Latches And Three State Drivers IBIP ±10VIN CDAC..... ..... ±5VIN Internal Ref VREF Out (1.2043V) Comparator ..... ..... BUSY SAR Three State Parallel Output Data Bus 43 ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Lead Temperature (soldering, 10s) ..................................... +300°C Thermal Resistance. ØJA: Plastic DIP ....................................................................... 50°C/W SOIC .............................................................................. 100°C/W VS to Digital Common ............................................................... +7V Pin 26 (VSO) to Pin 27 (VSA) .................................................... ±0.3V Analog Common to Digital Common ...................................... ±0.3V Control Inputs to Digital Common ....................... –0.3 to VS + 0.3 V Analog Input Voltage ........................................................... ±16.5V Maximum Junction Temperature ........................................... 160°C Internal Power Dissipation .................................................. 750mW SPECIFICATIONS (TA = 25°C; Sampling Frequency, FS, = 333kHz for SP8503, 200kHz for SP8505, 100kHz for SP8510, VS = +5V, unless otherwise specified.) PARAMETER MIN. TYP. MAX. ANALOG INPUT Voltage Ranges ±10V/±5V Impedance ±10V Range 4.7 6.7 8.7 ±5V Range 2.7 3.9 5.1 DC PERFORMANCE Full Scale Error –K ±0.1 ±0.50 Integral Linearity Error –K ±0.35 ±0.75 Differential Linearity Error –K ±0.35 ±0.95 No Missing Codes Guaranteed Bipolar Zero –K ±1 ±5 VOLTAGE REFERENCE Voltage Output 1.1440 1.2043 1.2645 Output Source Current 100 Output Resistance 280 AC PERFORMANCE SP8503 Conversion Time 2.6 Complete Cycle 3.0 Throughput Rate 333 Spurious-Free Dynamic Range @ 49kHz 85 @ 161kHz 72 Total Harmonic Distortion @ 49kHz –81 @ 161kHz –71 Signal to Noise Ratio (SNR) @ 49kHz 71.5 @ 161kHz 71.5 Signal to (Noise + Distortion) Ratio @ 49kHz 71 @ 161kHz 68 SP8505 Conversion Time 4.5 Complete Cycle 5.0 Throughput Rate 200 Spurious-Free Dynamic Range @ 49kHz 85 @ 97kHz 77 44 UNITS CONDITIONS V kΩ kΩ % TMIN ≤ TA ≤ TMAX TMIN ≤ TA ≤ TMAX Externally adjustable to zero; TMIN ≤ TA ≤ TMAX Note 1 LSB LSB LSB Externally adjustable to zero TMIN ≤ TA ≤ TMAX V µA Ω TMIN ≤ TA ≤ TMAX µs µs kHz Note 2 dB dB Note 2 dB dB Note 2 dB dB Note 2 dB dB µs µs kHz Note 2 dB dB SPECIFICATIONS (continued) (TA = 25°C; Sampling Frequency, FS, = 333kHz for SP8503, 200kHz for SP8505, 100kHz for SP8510, VS = +5V, unless otherwise specified.) PARAMETER MIN. AC PERFORMANCE SP8505 Total Harmonic Distortion @ 49kHz @ 97kHz Signal to Noise Ratio (SNR) @ 49kHz @ 97kHz Signal to (Noise + Distortion) Ratio @ 49kHz @ 97kHz SP8510 Conversion Time Complete Cycle 10.0 Throughput Rate Spurious-Free Dynamic Range Total Harmonic Distortion Signal to Noise Ratio (SNR) Signal to (Noise + Distortion) Ratio TYP. MAX. –65 CONDITIONS TMIN ≤ TA ≤ TMAX Note 2 –81 –76 dB dB 71.5 71.5 dB dB 71 70 dB dB 9.5 µs µs kHz dB dB dB dB Note 2 Note 2 100 85 –81 71.5 71 SAMPLING DYNAMICS Aperture Delay 13 Aperture Jitter 150 Transient Response –K 150 Overvoltage Recovery 150 DIGITAL INPUTS Logic Levels VIL –0.3 +0.8 VIH +2.4 +5.3 IIL ±0.1 ±50 IIH ±5 DIGITAL OUTPUTS Resolution 12 Data Format Parallel; 12-bit or 8-bit/4-bit Data Coding Offset Binary VOL 0.0 +0.4 VOH +2.4 VDD ±0.1 ±5 ILEAKAGE (High-Z State) POWER SUPPLY REQUIREMENTS Rated Voltage +4.75 +5.0 +5.25 Current 18 21 Power Consumption 90 ENVIRONMENTAL AND MECHANICAL Specification –K 0 +70 Storage Package –KN –KS UNITS +150 @ 49kHz; Note 2 @ 49kHz; Note 2 @ 49kHz; Note 2 @ 49kHz; Note 2 ns ps, rms Note 3 ns ns Note 4 V V µA µA Bits V V µA ISINK = 1.6mA ISOURCE = 1.6mA V mA mW VS (VSA and VSD) IS °C °C 28–pin Narrow DIP 28–pin SOIC NOTES 1. LSB means Least Significant Bit. For SP85XX Series, 1LSB = 2.44mV for ±5V range, 1 LSB = 4.88mV for ±10V range. 2. All specifications in dB are referred to a full-scale input, either ±10V or ±5V. 3. For full-scale step input, 12-bit accuracy attained in specified time. 4. Recovers to specified performance in specified time after 2 x FS input overvoltage. 45 Pin 12 — D5 — Data Bit 5 if HBE is LOW; LOW if HBE is HIGH. PINOUT N.C. 1 ±10V IN 2 ±5V IN VREF AGND D11 3 4 5 6 7 8 D10 D9 D8 9 D7 10 SP8503 SP8505 SP8510 D6 11 D5 12 D4 13 N.C. 14 28 27 26 25 N.C. VSA VSD N.C. 24 23 22 21 BUSY CS R/C HBE 20 D0 19 D1 18 D2 17 D3 16 DGND 15 N.C. PIN ASSIGNMENT Pin 1 —No Connection —This pin is not internally connected. Pin 2 — IN1 — ±10V Analog Input. Connected to AGND for ±5V range. Pin 3 — IN2 — ±5V Analog Input. Connected to AGND for ±10V range. Pin 4 — VREF – Internal Voltage. Reference Output. Pin 5 — AGND — Analog Ground. Connect to pin 16 at the device. Pin 6 — D11 — Data Bit 11. Most Significant Bit (MSB). Pin 13 — D4 — Data Bit 4 if HBE is LOW; LOW if HBE is HIGH. Pin 14 —N.C.—This pin is not internally connected. Pin 15 —N.C.—This pin is not internally connected. Pin 16— DGND — Digital Ground. Connect to pin 5, at the device. Pin 17 — D3 — Data Bit 3 if HBE is LOW; Data Bit 11 if HBE is HIGH. Pin 18 — D2 — Data Bit 2 if HBE is LOW; Data Bit 10 if HBE is HIGH. Pin 19— D1 — Data Bit 1 if HBE is LOW; Data Bit 9 if HBE is HIGH. Pin 20 — D0 — Data Bit 0 if HBE is LOW. Least Significant Bit (LSB). Data Bit 8 if HBE is HIGH. Pin 21 — HBE — High Byte Enable, When held LOW, data output as 12-bits in parallel. When held HIGH, four MSBs presented on pins 17–20, pins 10 – 13 output LOWs. Must be LOW to initiate conversion. Pin 22— R/C — Read/Convert. Falling edge initiates conversion when CS is LOW, HBE is LOW, and BUSY is HIGH. Pin 23 — CS — Chip Select. Outputs in Hi-Z state when HIGH. Must be LOW to initiate conversion or read data. Pin 7 — D10 — Data Bit 10. Pin 24 — BUSY. Output LOW during conversion. Data valid on rising edge in Convert Mode. Pin 8— D9 — Data Bit 9. Pin 25 — N.C. — This pin is not internally connected. Pin 9 — D8 — Data Bit 8. Pin 26 — VSD — Positive Digital Power Supply, +5V. Connect to pin 27, and bypass to DGND. Pin 10 — D7 — Data Bit 7 if HBE is LOW; LOW if HBE is HIGH. Pin 11 — D6 — Data Bit 6 if HBE is LOW; LOW if HBE is HIGH. 46 Pin 27 — VSA — Positive Analog Power Supply. +5V. Connect to pin 26, and bypass to AGND. Pin 28 — N.C. — This pin is not internally connected. FEATURES... The SP85XX Series are specified at sampling rates of 333kHz (SP8503), 200kHz (SP8505) or 100kHz (SP8510). Conversion times are factory set for 2.70µs, 4.7µs and 9.7µs maximum, respectively, over temperature, and the highspeed sampling input stage insures a total acquisition and conversion time of 3µs, 5µs and 10µs maximum, respectively, over temperature. Precision, laser-trimmed scaling resistors provide industry–standard input ranges of ±5V or ±10V. The 28-pin SP85XX Series are available in narrow body plastic DIP, and SOIC packages and it operates from a single +5V supply. The SP85XX Series are available in grades specified over the 0°C to +70°C commercial temperature ranges. OPERATION Basic Operation Figure 1 shows the simple hookup circuit required to operate the SP85XX Series in a ±10V range in the Convert Mode. A convert command arriving on R/C puts the SP85XX Series in the HOLD mode, and a conversion is started. This pulse must be LOW for a minimum of 40ns. Because this pulse establishes the sampling instant of the A/D, it must have very low jitter. BUSY will be held LOW during the conversion, and rises only after the conversion is completed and the data has been transferred to the output drivers. Thus, the rising Input 1 N.C. N.C. 28 2 IN 1 +5V 27 3 IN 2 +5V 26 4 VREF 5 AGND 6 D11 (MSB) 7 D10 R/C 22 8 D9 HBE 21 9 D8 D0 (LSB) 20 +5V 6.8µF + 0.1µF N.C. 25 BUSY 24 Busy 10 D7 D1 19 11 D6 D2 18 12 D5 D3 17 13 D4 DGND 16 14 N.C. D11 (MSB) CS 23 Convert Command N.C. 15 Data Out Figure 1. Basic ±10V Operation D0 (LSB) edge can be used to read the data from the conversion. Also, during conversion, the BUSY signal puts the output data lines in Hi-Z states and inhibits the input lines. This means that pulses on R/C are ignored, so that new conversions cannot be initiated during a conversion, either as a result of spurious signals or to short-cycle the SP85XX Series. In the Read Mode, the input to R/C is kept normally LOW, and a HIGH pulse is used to read data and initiate a conversion. In this mode, the rising edge of R/C will enable the output data pins, and the data from the previous conversion becomes valid. The falling edge then puts the SP85XX Series in a hold mode, and initiates a new conversion. The SP85XX Series will begin acquiring a new sample just prior to the BUSY output rising, and will track the input signal until the next conversion is started. For use with an 8-bit bus, the data can be read out in two bytes under the control of HBE. With a LOW input on HBE, at the end of a conversion, the 8 LSBs of data are loaded into the output drivers on D7 through D4 and D3 through D0. Taking HBE HIGH then loads the 4 MSBs on D3 through D0, with D7 through D4 being forced LOW. Analog Input Ranges The SP85XX Series offers two standard bipolar input ranges: ±10V and ±5V. If a ±10V range is required, the analog input signal should be connected to pin 2. A signal requiring a ±5V range should be connected to pin 3. In either case, the other pin of the two must be grounded or connected to the adjustment circuits described in the section on calibration. Controlling The SP85XX Series The SP85XX Series can be easily interfaced to most microprocessor-based and other digital systems. The microprocessor may take full control of each conversion, or the SP85XX Series may operate in a standalone mode, controlled only by the R/C input. Full control consists of initiating the conversion and reading the output data at user command, transmitting data either all 12-bits in one parallel word, or in two 8-bit bytes. The three control inputs (CS, R/C and HBE) are 47 CS R/C 1 X OPERATION X 1 None – outputs in Hi-Z state. 0 1 Holds signal and initiates conversion. 0 1 0 1 Output three-state buffers enabled once conversion has finished. 0 1 1 1 Enable hi-byte in 8-bit bus mode. 0 0 0 HBE BUSY 1 1 1 Inhibit start of conversion. 0 1 0 0 1 1 None – outputs in Hi-Z state. X X X 0 Conversion in progress. Outputs Hi-Z state. New conversion inhibited until present conversion has finished. Table 1. Control Line Functions all TTL/CMOS compatible. The functions of the control lines are shown in Table 1. For stand-alone operation, control of the SP85XX Series is accomplished by a single control line connected to R/C. In this mode, CS and HBE are connected to GND. The output data are presented as 12-bit words. The stand-alone mode is used in systems containing dedicated input ports which do not require full bus interface capability. Conversion is initiated by a HIGH-to-LOW transition on R/C. The three-state data output buffers are enabled when R/C is HIGH and BUSY is HIGH. Thus, there are two possible modes of operation: conversion can be initiated with either positive or negative pulses. In either case, the R/C pulse must remain LOW a minimum of 40ns. Figure 5 illustrates timing when conversion is initiated by an R/C pulse which goes LOW and returns HIGH during the conversion. In this case (Convert Mode), the three-state outputs go into the Hi-Z state in response to the falling edge of R/C, and are enabled for external access to the data after completion of the conversion. Figure 6 illustrates the timing when conversion is initiated by a positive R/C pulse. In this mode (Read Mode), the output data from the previous conversion is enabled during the HIGH portion of R/C. A new conversion starts on the falling edge of R/C, and the three-state outputs return to the Hi-Z state until the next occurrence of a HIGH on R/C. in Table 2. No other combination of states or transitions will initiate a conversion. Conversion is inhibited if either CS or HBE are HIGH, or if BUSY is LOW. CS and HBE should be stable a minimum of 25ns prior to the transition on R/C. Timing relationships for start of conversion are illustrated in Figure 7. The BUSY output indicates the current state of the converter by being LOW only during conversion. During this time the three-state output buffers remain in a Hi-Z state, and therefore data cannot be read during conversion. During this period, additional transitions on the three digital inputs (CS, R/C and HBE) will be ignored, so that conversion cannot be prematurely terminated or restarted. Internal Clock The SP85XX Series has an internal clock that is factory trimmed to achieve the typical conversion times given in the specifications, and a maximum conversion time over the full operating temperature range of 2.7µs, 4.7µs or 9.7µs, depending on the model. No external adjustments are required, and with the guaranteed maximum acquisition time of 300ns, throughput performance is assured with convert pulses as close as 3µs for the SP8503. Reading Data After conversion is initiated, the output buffers remain in a Hi-Z state until the following three logic conditions are simultaneously met: R/C is HIGH, BUSY is HIGH and CS is LOW. Upon satisfying these conditions, the data lines are enabled according to the state of HBE. See Figure 7 for timing relationships and specifications. CALIBRATION... Optional External Gain And Offset Trim Offset and full-scale errors may be trimmed to zero using external offset and full-scale trim potentiometers connected to the SP85XX Series as shown in Figure 3. If adjustment of offset and full scale is not required, connections as shown in Figure 2 should be used. ±10V Input Conversion Start A conversion is initiated on the SP85XX Series only by a negative transition occurring on R/C, as shown 48 2 3 SP8503/05/10 ±5V Input 2 SP8503/05/10 3 Figure 2. a) ±10V Range b) ±5V Range — Without Trims INPUT VOLTAGE RANGE AND LSB VALUES ±10V Input Voltage Range Defined As: ±5V Analog Input Connected to Pin 2 3 Pin Connected to AGND 3 2 20V/212 4.88mV 10V/212 2.44mV FSR/212 One Least Significant Bit (LSB) OUTPUT TRANSITION VALUES FFEH TO FFFH + FULL SCALE 7FFH TO 800H +10V–3/2LSB Mid Scale 000H to 001H +5V–3/2LSB +9.9927V +4.9963V 0V–1/2LSB 0V–1/2LSB (Bipolar Zero) –2.44mV –1.22mV –Full Scale –10V+1/2LSB -9.9976V –5V+1/2LSB -4.9988V Table 2. Input Voltages, Transition Voltages and LSB Values Calibration Procedure Apply a precision input voltage source to your chosen input range (±10V range at pin 2 or ±5V at pin 3). Set the A/D to convert continuously. Monitor the output code. Trim the offset first, then gain. Use the appropriate input voltages and output target codes for your chosen input range as follows. The recommended offset calibration voltage values eliminate interaction between the offset and gain calibration ±5V Range Offset and Gain Offset — Apply 1.5637V to the ±5V input at pin 3. Adjust the offset potentiometer until the LSB toggles on and off at code 1010 1000 0000 = A80 = 2688 . BIN H DEC Gain — Apply 4.9963V to the ±5V input at pin 3. Adjust the gain potentiometer until the LSB GAIN ADJUST ±10V Input R2=100Ω +5V R1=10KΩ 499Ω 10KΩ 100Ω –15V 1 2 3 4 5 6 7 toggles on and off at code 1111 1111 1110 = FFE = 4094 . BIN H DEC ±10V Range Offset and Gain Offset — Apply 1.2622V to the ±10V input at pin 2. Adjust the offset potentiometer until the LSB toggles on and off at code 1001 0000 0010 = 902 = 2306 . BIN H DEC Gain — Apply 9.9927V to the ±10V input at pin 2. Adjust the gain potentiometer until the LSB toggles on and off at code 1111 1111 1110 = FFE = 4094 . BIN H DEC Layout Considerations Because of the high resolution and linearity of the SP85XX Series, system design problems such as ground path resistance and contact resistance become very important. GAIN ADJUST SP85XX ±5V Input R2=100Ω +5V R1=10KW 1KΩ a) 30.1KΩ 301Ω 1 SP85XX 2 3 4 5 6 7 b) –15V BIPOLAR ZERO ADJUST Figure 3. a) ±10V Range b) ±5V Range — With External Trims 49 The input resistance of the SP85XX Series is 6.3kΩ or 4.2KΩ (for the ±10V and ±5V ranges respectively). To avoid introducing distortion, the source resistance must be very low, or constant with signal level. The output impedance provided by most op amps is ideal. Pins 26 Digital Supply Voltage (VSD) and 27 Analog Supply Voltage (VSA) are brought out to separate pins to maximize accuracy on the chip. They should be connected together as close as possible to the unit. Pin 27 may be slightly more sensitive than pin 26 to supply variations, but to maintain maximum system accuracy, both should be well–isolated from digital supplies with wide load variations. 1). Noise on the power supply lines can degrade converter performance, especially noise and spikes from a switching power supply. Appropriate supplies or filters must be used. The GND pins (5 and 16) are also separated internally, and should be directly connected to a ground plane under the converter. A ground plane is usually the best solution for preserving dynamic performance and reducing noise coupling into sensitive converter circuits. Where any compromises must be made, the common return of the analog input signal should be referenced to pin 5, AGND, on the SP85XX Series, which prevents any voltage drops that might occur in the power supply common returns from appearing in series with the input signal. To limit the effects of digital switching elsewhere in a system on the analog performance of the system, it often makes sense to run a separate +5V supply conductor from the supply regulator to any analog components requiring +5V, including the SP85XX Series. If the SP85XX Series traces cannot be separated back to the power supply terminals, and therefore share the same trace as the logic supply currents, then a 10 Ohm isolating resistor should be used between the board supply and pin 24 (VDA) and its bypass capacitors, to keep VDA glitch–free. The VS pins (26 and 27) should be connected together and bypassed with a parallel combination of a 6.8µF Tantalum capacitor and a 0.1µF ceramic capacitor located close to the converter to obtain noise-free operation. (See Figure Coupling between analog input and digital lines should be minimized by careful layout. For instance, if the lines must cross, they should do so at right angles. Parallel analog and digital lines should be separated from each other by a pattern connected to common. If external full scale and offset potentiometers are used, the potentiometers and related resistors should be located as close to the SP85XX Series as possible. “Hot Socket” Precaution Two separate +5V VS pins, 26 and 27, are used to minimize noise caused by digital transients. If one pin is powered and the other is not, the SP85XX R/C tB BUSY t DBC tC Converter Acquisition Mode Conversion Acquisition Conversion tAP Hold Time SYMBOL/PARAMETER TYP. MAX. t BUSY delay from R/C 80 150 ns t BUSY Low 2.5 2.7 µs SP8503 4.5 4.7 µs SP8505 9.5 9.7 µs SP8510 DBC B t MIN. UNITS Aperture Delay 13 ns ∆t Aperture Jitter 150 ps, rms t Conversion Time 2.47 4.47 9.47 AP AP C Figure 4. Acquisition and Conversion Timing 50 2.70 4.70 9.70 µs µs µs SP8503 SP8505 SP8510 tW R/C tB BUSY t DBC t DBE tAP Converter Mode Acquire Acquire Convert tC t DB t HDR and t HL Data BUS Data Valid Convert tA Hi-Z State Data Valid Hi-Z State Figure 5. Convert Mode Timing — R/C Pulse LOW, Outputs Enabled After Conversion Series may draw excessive current. In normal operation, this is not a problem because both pins will be soldered together. However, during evaluation, incoming inspection, repair, etc., where the potential of a “Hot Socket” exists, care should be taken to apply power to the SP85XX Series only after it has been socketed. Minimizing “Glitches” Coupling of external transients into an analog-todigital converter can cause errors which are difficult to debug. In addition to the discussions earlier on layout considerations for supplies, bypassing and grounding, there are several other useful steps that can be taken to R/C get the best analog performance out of a system using the SP85XX Series. These potential system problem sources are particularly important to consider when developing a new system, and looking for the causes of errors in breadboards. First, care should be taken to avoid glitches during critical times in the sampling and conversion process. Since the SP85XX Series has an internal sample/hold function, the signal that puts it into the hold state (R/C going LOW) is critical, as it would be on any sample/ hold amplifier. The R/C falling edge should have a 5 to 10ns transition time, low jitter, and have minimal ringing, especially during the 20ns after it falls. tW tB BUSY t DBC t DBE tAP Converter Mode Acquire Convert Data BUS Hi-Z State Convert Acquire tC t DD tAP tA t HDR and t HL Data Valid Hi-Z State Data Valid Hi-Z State Figure 6. Read Mode Timing — R/C Pulse HIGH, Outputs Enabled Only When R/C is High 51 AC DYNAMIC TIMING DATA SYMBOL/PARAMETER MIN . TYP. MAX. 80 150 ns 2.47 2.7 µs 40 UNITS tW R/C Pulse Width tDBC BUSY delay from R/C ns tB BUSY LOW tAP Aperture Delay 13 ns ∆tAP Aperture Jitter 150 ps, rms tC Conversion Time 2.5 tDBE BUSY from End of Conversion tDB BUSY Delay after Data Valid tA Acquisition Time t A + tC Throughput Time 2.70 µs 75 200 ns 130 300 ns 100 25 ns SP8503 3.0 µs SP8505 5.0 µs SP8510 10.0 µs tHDR Valid Data Held After R/C LOW 20 50 ns tS CS or HBE LOW before R/C Falls 25 5 ns tH CS or HBE LOW after R/C Falls 25 tDD Data Valid from CS LOW, R/C HIGH, and HBE 0 ns 65 150 ns 50 150 ns in Desired State (Load = 100pF) tHL Delay to Hi-Z State after R/C Falls or CS Rises (3KΩ Pullup or Pulldown All parameters Guaranteed By Design. Although not normally required, it is also good practice to avoid glitches from coupling to the SP85XX Series while bit decisions are being made. Since the above discussion calls for a fast, clean rise and fall on R/C, it makes sense to keep the rising edge of the convert pulse outside the time when bit decisions are being made. In other words, the convert pulse should either be short (under 100ns so that it transitions before the MSB decision), or relatively long (over 2.75µs to transition after the LSB decision). Next, although the data outputs are forced into a Hi-Z state during conversion, fast bus transients can still be capacitively coupled into the SP85XX Series. If the data bus experiences fast transients during conversion, these transients can be attenuated by adding a logic buffer to the data outputs. The BUSY output can be used to enable the buffer. 52 Naturally, transients on the analog input signal are to be avoided, especially at times within ±20ns of R/C going LOW, when they may be trapped as part of the charge on the capacitor array. This requires careful layout of the circuit in front of the SP85XX Series. Finally, in multiplexed systems, the timing relative to when the multiplexer is switched may affect the analog performance of the system. In most applications, the multiplexer can be switched as soon as R/C goes LOW (with appropriate delays), but this may affect the conversion if the switched signal shows glitches or significant ringing at the SP85XX Series input. Whenever possible, it is safer to wait until the conversion is completed before switching and multiplexer. The extremely fast acquisition time and conversion time of the SP85XX Series make this practical in many applications. CS or HBE tS tW R/C BUSY Data BUS tH t DBC Data Valid Hi-Z State t HDR and t HL Figure 7. Conversion Start Timing ORDERING INFORMATION 0°C to +70°C Model Throughput Package SP8503KN .................................................................... 333kHz ................................................................................................ 28–pin 0.3" Plastic DIP SP8503KS .................................................................... 333kHz ........................................................................................................ 28–pin, 0.3" SOIC SP8505KN .................................................................... 200kHz ................................................................................................ 28–pin 0.3" Plastic DIP SP8505KS .................................................................... 200kHz ........................................................................................................ 28–pin, 0.3" SOIC SP8510KN .................................................................... 100kHz ................................................................................................ 28–pin 0.3" Plastic DIP SP8510KS .................................................................... 100kHz ........................................................................................................ 28–pin, 0.3" SOIC 53 THIS PAGE LEFT INTENTIONALLY BLANK 54