BB ADS7888SDCKT

 ADS7887
ADS7888
SLAS468 – JUNE 2005
10-/8-Bit, 1.25-MSPS, MICRO-POWER, MINIATURE
SAR ANALOG-TO-DIGITAL CONVERTERS
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.25-MHz Sample Rate Serial Device
10-Bit Resolution – ADS7887
8-Bit Resolution – ADS7888
Zero Latency
25-MHz Serial Interface
Supply Range: 2.35 V to 5.25 V
Typical Power Dissipation at 1.25 MSPS:
– 3.8 mW at 3-V VDD
– 8 mw at 5-V VDD
±0.35 LSB INL, DNL – ADS7887
±0.15 LSB INL, ±0.1 LSB DNL – ADS7888
61dB SINAD, -84 dB THD – ADSA7887
49.5 dB SINAD, -67.5 dB THD – ADS7888
Unipolar Input Range: 0 V to VDD
Power Down Current: 1 µA
Wide Input Bandwidth: 15 MHz at 3 dB
6-Pin SOT23 and SC70 Packages
•
•
•
•
•
•
•
Base Band Converters in Radio Communication
Motor Current/Bus Voltage Sensors in Digital
Drives
Optical Networking (DWDM, MEMS Based
Switching)
Optical Sensors
Battery Powered Systems
Medical Instrumentations
High-Speed Data Acquisition Systems
High-Speed Closed-Loop Systems
DESCRIPTION
The ADS7887 is a 10-bit, 1.25-MSPS analog-to-digital converter (ADC), and the ADS7888 is a 8-bit, 1.25-MSPS
ADC. The devices include a capacitor based SAR A/D converter with inherent sample and hold. The serial
interface in each device is controlled by the CS and SCLK signals for glueless connections with microprocessors
and DSPs. The input signal is sampled with the falling edge of CS, and SCLK is used for conversion and serial
data output.
The devices operate from a wide supply range from 2.35 V to 5.25 V. The low power consumption of the devices
make them suitable for battery-powered applications. The devices also include a power saving powerdown
feature for when the devices are operated at lower conversion speeds.
The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as
high as 5.25 V when device supply is 2.35 V. This feature is useful when digital signals are coming from other
circuit with different supply levels. Also this relaxes restriction on power up sequencing.
The ADS7887 and ADS7888 are available in 6-pin SOT23 and SC70 packages and are specified for operation
from -40°C to 125°C.
Micro-Power Miniature SAR Converter Family
BIT
< 300 KSPS
300 KSPS – 1.25 MSPS
12-Bit
ADS7866 (1.2 VDD to 3.6 VDD)
ADS7886 (2.35 VDD to 5.25 VDD)
10-Bit
ADS7867 (1.2 VDD to 3.6 VDD)
ADS7887 (2.35 VDD to 5.25 VDD)
8-Bit
ADS7868 (1.2 VDD to 3.6 VDD)
ADS7888 (2.35 VDD to 5.25 VDD)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
SAR
+IN
CDAC
OUTPUT
LATCHES
&
3−STATE
DRIVERS
SDO
COMPARATOR
VDD
ADS7887/ADS7888
2
CONVERSION
&
CONTROL
LOGIC
SCLK
CS
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION (1)
DEVICE
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
ADS7887
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
±0.75
ADS7888
±0.3
NO MISSING
CODES AT
RESOLUTION
(BIT)
±0.5
PACKAGE
TYPE
PACKAGE
DESIGNATOR
6-Pin
SOT23
DBV
10
±0.3
PACKAGE
MARKING
ORDERING
INFORMATION
TRANSPORT
MEDIA
QUANTITY
BAWQ
ADS7887SDBVT
Tape and
reel 250
BAWQ
ADS7887SDBVR
Tape and
reel 3000
BNI
ADS7887SDCKT
Tape and
reel 250
BNI
ADS7887SDCKR
Tape and
reel 3000
BAZQ
ADS7888SDBVT
Tape and
reel 250
BAZQ
ADS7888SDBVR
Tape and
reel 3000
BNH
ADS7888SDCKT
Tape and
reel 250
BNH
ADS7888SDCKR
Tape and
reel 3000
–40°C to 125°C
6-Pin
SC70
DCK
6-Pin
SOT23
DBV
8
–40°C to 125°C
6-Pin
SC70
(1)
TEMPERATURE
RANGE
DCK
For most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
UNIT
+IN to AGND
–0.3 V to +VDD +0.3 V
+VDD to AGND
–0.3 V to 7.0 V
Digital input voltage to GND
–0.3V to (7.0 V)
Digital output to GND
–0.3 V to (+VDD + 0.3 V)
Operating temperature range
–40°C to 125°C
Storage temperature range
–65°C to 150°C
Junction temperature (TJ Max)
150°C
Power dissipation, SOT23 and SC70 packages
θJA Thermal impedance
Lead temperature, soldering
(1)
(TJ Max–TA)/θJA
SOT23
295.2°C/W
SC70
351.3°C/W
Vapor phase (60 sec)
215°C
Infrared (15 sec)
220°C
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
3
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
ADS7887 SPECIFICATIONS
+VDD = 2.35 V to 5.25 V, TA = –40°C to 125°C, fsample = 1.25 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
V
ANALOG INPUT
Full-scale input voltage span (1)
Absolute input voltage range
Ci
Input capacitance (2)
IIlkg
Input leakage current
0
+IN
–0.20
TA = 125°C
VDD+0.20
V
21
pF
40
nA
10
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
10
Bits
–0.75
±0.35
0.75
LSB (3)
Differential nonlinearity
–0.5
±0.35
0.5
LSB
Offset error (4) (5) (6)
–1.5
±0.5
1.5
LSB
–1
±0.5
1
LSB
530
560
INL
Integral nonlinearity
DNL
EO
EG
Gain error (5)
SAMPLING DYNAMICS
Conversion time
25-MHz SCLK
Acquisition time
Maximum throughput rate
ns
260
ns
25-MHz SCLK
1.25
Aperture delay
MHz
5
ns
Step Response
160
ns
Overvoltage recovery
160
ns
DYNAMIC CHARACTERISTICS
THD
Total harmonic distortion (7)
100 kHz
SINAD
Signal-to-noise and distortion
100 kHz
60.5
61
SFDR
Spurious free dynamic range
100 kHz
73
81
dB
Full power bandwidth
At –3 dB
15
MHz
–84
–72
dB
dB
DIGITAL INPUT/OUTPUT
Logic family — CMOS
VDD = 2.35 V to 5.25 V
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
At Isource = 200 µA
VOL
Low-level output voltage
At Isink = 200 µA
VDD–
0.4
5.25
VDD = 5 V
0.8
VDD = 3 V
0.4
VDD–0.2
0.4
V
V
V
POWER SUPPLY REQUIREMENTS
+VDD
Supply voltage
Supply current (normal mode)
Power down state supply current
Power dissipation at 1.25 MHz
throughput
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
2.35
3.3
At VDD = 2.35 V to 5.25 V, 1.25-MHz throughput
5.25
2
At VDD = 2.35 V to 5.25 V, static state
1.5
SCLK off
1
SCLK on (25 MHz)
200
VDD = 5 V
8
10
VDD = 3 V
3.8
6
Ideal input span; does not include gain or offset error.
Refer Figure 36 for details on sampling circuit
LSB means least significant bit
Measured relative to an ideal full-scale input
Offset error and gain error ensured by characterization.
First transition of 000H to 001H at 0.5 × (Vref/210)
Calculated on the first nine harmonics of the input frequency
V
mA
µA
mW
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
ADS7887 SPECIFICATIONS (continued)
+VDD = 2.35 V to 5.25 V, TA = –40°C to 125°C, fsample = 1.25 MHz
PARAMETER
Power dissipation in static state
TYP
MAX
VDD = 5 V
TEST CONDITIONS
MIN
5.5
7.5
VDD = 3 V
3
4.5
UNIT
mW
Power down time
0.1
µs
Power up time
0.8
µs
Invalid conversions after power up
1
TEMPERATURE RANGE
Specified performance
–40
125
°C
5
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
ADS7888 SPECIFICATIONS
+VDD = 2.35 V to 5.25 V, TA = –40°C to 125°C, fsample = 1.25 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
V
ANALOG INPUT
Full-scale input voltage span (1)
Absolute input voltage range
Ci
Input capacitance (2)
IIlkg
Input leakage current
0
+IN
–0.20
TA = 125°C
VDD+0.20
V
21
pF
40
nA
8
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
8
Bits
±0.15
0.3
LSB (3)
–0.3
±0.1
0.3
LSB
–0.5
±0.15
0.5
LSB
–0.5
±0.15
0.5
LSB
480
INL
Integral nonlinearity
–0.3
DNL
Differential nonlinearity
EO
Offset error (4) (5) (6)
EG
Gain error (5)
SAMPLING DYNAMICS
Conversion time
25-MHz SCLK
450
Acquisition time
1.5 MSPS mode, Figure 3
206
Maximum throughput rate
25-MHz SCLK
ns
ns
1.25
Aperture delay
MHz
5
ns
Step Response
160
ns
Overvoltage recovery
160
ns
DYNAMIC CHARACTERISTICS
THD
Total harmonic distortion (7)
100 kHz
SINAD
Signal-to-noise and distortion
100 kHz
49
49.5
SFDR
Spurious free dynamic range
100 kHz
65
77
dB
Full power bandwidth
At –3 dB
15
MHz
–67.5
–65
dB
dB
DIGITAL INPUT/OUTPUT
Logic family — CMOS
VIH
High-level input voltage
VDD = 2.35 V to 5.25 V
VDD–0.4
5.25
VDD = 5 V
0.8
VDD = 3 V
0.4
VIL
Low-level input voltage
VOH
High-level output voltage
At Isource = 200 µA
VOL
Low-level output voltage
At Isink = 200 µA
VDD–0.2
0.4
V
V
V
POWER SUPPLY REQUIREMENTS
+VDD
Supply voltage
Supply current (normal mode)
2.35
3.3
At VDD = 2.35 V to 5.25 V, 1.25-MHz
throughput
Power dissipation at 1.25 MHz
throughput
(1)
(2)
(3)
(4)
(5)
(6)
(7)
mA
6
1.5
SCLK off
1
SCLK on (25 MHz)
200
VDD = 5 V
8
10
VDD = 3 V
3.8
6
Ideal input span; does not include gain or offset error.
Refer Figure 36 for details on sampling circuit
LSB means least significant bit
Measured relative to an ideal full-scale input
Offset error and gain error ensured by characterization.
First transition of 000H to 001H at (Vref/28)
Calculated on the first nine harmonics of the input frequency
V
2
At VDD = 2.35 V to 5.25 V, static state
Power down state supply current
5.25
µA
mW
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
ADS7888 SPECIFICATIONS (continued)
+VDD = 2.35 V to 5.25 V, TA = –40°C to 125°C, fsample = 1.25 MHz
PARAMETER
TEST CONDITIONS
Power dissipation in static state
TYP
MAX
VDD = 5 V
MIN
5.5
7.5
VDD = 3 V
3
4.5
UNIT
mW
Power down time
0.1
µs
Power up time
0.8
µs
Invalid conversions after power up
1
TEMPERATURE RANGE
Specified performance
–40
125
°C
TIMING REQUIREMENTS (see Figure 1)
All specifications typical at TA = –40°C to 125°C, VDD = 2.35 V to 5.25 V, unless otherwise specified.
TEST CONDITIONS (1)
PARAMETER
ADS7887
tconv
Conversion time
ADS7888
tq
Minimum quiet time needed from bus 3-state to start
of next conversion
td1
Delay time, CS low to first data (0) out
tsu1
Setup time, CS low to SCLK low
td2
Delay time, SCLK falling to SDO
th1
Hold time, SCLK falling to data valid (2)
td3
Delay time, 16th SCLK falling edge to SDO 3-state
tw1
Pulse duration, CS
td4
Delay time, CS high to SDO 3-state, Figure 3
twH
Pulse duration, SCLK high
twL
Pulse duration, SCLK low
Frequency, SCLK
MIN
TYP
MAX
VDD = 3 V
14 × tSCLK
VDD = 5 V
14 × tSCLK
VDD = 3 V
12 × tSCLK
ns
12 × tSCLK
VDD = 5V
VDD = 3 V
40
VDD = 5 V
40
ns
VDD = 3 V
15
25
VDD = 5 V
13
25
VDD = 3 V
10
VDD = 5 V
10
VDD = 3 V
15
25
VDD = 5 V
13
25
VDD < 3 V
7
VDD > 5 V
5.5
10
25
VDD = 5 V
8
20
VDD = 3 V
25
40
VDD = 5 V
25
40
17
30
VDD = 5 V
15
25
0.4 × tSCLK
0.4 × tSCLK
VDD = 3 V
0.4 × tSCLK
VDD = 5 V
0.4 × tSCLK
ns
ns
VDD = 3 V
VDD = 5 V
ns
ns
VDD = 3 V
VDD = 3 V
ns
ns
ns
ns
ns
VDD = 3 V
25
VDD = 5 V
25
Delay time, second falling edge of clock and CS to
enter in powerdown (use min spec not to accidently
enter in powerdown) Figure 4
VDD = 3 V
-2
5
td5
VDD = 5 V
-2
5
Delay time, CS and 10th falling edge of clock to
enter in powerdown (use max spec not to accidently
enter in powerdown) Figure 4
VDD = 3 V
2
-5
td6
VDD = 5 V
2
-5
(1)
(2)
UNIT
MHz
ns
ns
3-V Specifications apply from 2.35 V to 3.6 V, and 5-V specifications apply from 4.75 V to 5.25 V.
With 50-pf load.
7
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
DEVICE INFORMATION
SOT23/SC70 PACKAGE
(TOP VIEW)
VDD
1
6
CS
GND
2
5
SDO
VIN
3
4
SCLK
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
NO.
DESCRIPTION
VDD
1
–
Power supply input also acts like a reference voltage to ADC.
GND
2
–
Ground for power supply, all analog and digital signals are referred with respect to this pin.
VIN
3
I
Analog signal input
SCLK
4
I
Serial clock
SDO
5
O
Serial data out
CS
6
I
Chip select signal, active low
ADS7887 NORMAL OPERATION
The cycle begins with the falling edge of CS. This point is indicated as a in Figure 1. With the falling edge of CS,
the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion
is in progress. The data word contains 4 leading zeros, followed by 10-bit data in MSB first format and padded by
2 lagging zeros.
The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until
the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is padded
with two lagging zeros as shown in Figure 1. On the 16th falling edge of SCLK, SDO goes to the 3-state
condition. The conversion ends on the 14th falling edge of SCLK. The device enters the acquisition phase on the
first rising edge of SCLK after the 13th falling edge. This point is indicated by b in Figure 1.
CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by
pulling CS low until the end of the quiet time (tq) after SDO goes to 3-state. To continue normal operation, it is
necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase
and no valid data is available in the next cycle. (Also refer to power down mode for more details.) CS going high
any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.
The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as
high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from
another circuit with different supply levels. Also, this relaxes the restriction on power up sequencing. However,
the digital output levels (VOH and VOL) are governed by VDD as listed in the SPECIFICATIONS table.
a
tconv
tw1
b
CS
tsu1
1
SCLK
4
0
13
6
5
15
14
16
th1
td2
td1
SDO
2
0
0
D9
td3
D8
D1
D0
0
0
tq
1/throughput
Figure 1. ADS7887 Interface Timing Diagram
8
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
ADS7888 NORMAL OPERATION
The cycle begins with the falling edge of CS . This point is indicated as a in Figure 2. With the falling edge of CS,
the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion
is in progress. The data word contains 4 leading zeros, followed by 8-bit data in MSB first format and padded by
4 lagging zeros.
The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until
the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is padded
with four lagging zeros as shown in Figure 2. On the 16th falling edge of SCLK, SDO goes to the 3-state
condition. The conversion ends on the 12th falling edge of SCLK. The device enters the acquisition phase on the
first rising edge of SCLK after the 11th falling edge. This point is indicated by b in Figure 2.
CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by
pulling CS low until the end of the quiet time (tq) after SDO goes to 3-state. To continue normal operation, it is
necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase
and no valid data is available in the next cycle. (Also refer to power down mode for more details.) CS going high
any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.
The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as
high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from
another circuit with different supply levels. Also, this relaxes the restriction on power up sequencing. However,
the digital output levels (VOH and VOL) are governed by VDD as listed in the SPECIFICATIONS section.
a
tconv
tw1
b
CS
tsu1
1
SCLK
4
0
11
6
5
15
12
16
th1
td2
td1
SDO
2
0
0
td3
D7
D6
D0
D1
0
0
0
tq
1/throughput
Figure 2. ADS7888 Interface Timing Diagram
As shown in Figure 3, the ADS7888 can achieve 1.5-MSPS throughput. CS can be pulled high after the 12th
falling edge (with a 25-MHz SCLK). SDO goes to 3-state after the LSB (as CS is high). CS can be pulled low at
the end of the quiet time (tq) after SDO goes to 3-state.
a
tw1
tconv
b
CS
tsu1
td4
1
SCLK
4
0
12
11
6
5
th1
td2
td1
SDO
2
0
0
D7
th1
D6
D1
D0
tq
1/throughput
Figure 3. ADS7888 Interface Timing Diagram, Data Transfer with 12-Clock Frame
POWER DOWN MODE
The device enters power down mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th
SCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this power down condition as
shown in Figure 4.
9
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
td6
td5
CS
1
2
3
4
5
9
10
16
SCLK
SDO
Figure 4. Entering Power Down Mode
A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of power down mode. For
the device to come to the fully powered up condition it takes 0.8 µs. CS can be pulled high any time after the
10th falling edge as shown in Figure 5. It is not necessary to continue until the 16th clock if the next conversion
starts 0.8 µs after CS going low of the dummy cycle and the quiet time (tq) condition is met.
Device Starts
Powering Up
Device Fully
Powered-Up
CS
SCLK
1
SDO
2
3
4
5
6
7
8
9 10 11 12 13 14 15
16
1
2
3
4
5
6
Invalid Data
8
9
10 11 12 13 14 15 16
Valid Data
Figure 5. Exiting Power Down Mode
10
7
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7887, ADS7888
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
SCLK FREQUENCY
1.80
1.8
1.60
125C
1.4
−40C
1.3
1.2
1.40
1.20
2.35 V VDD
1
0.80
0.60
1
0.8
0.6
0.4
0.40
1.1
1
2.35
I DD − Supply Current − mA
I DD − Supply Current − mA
25C
VDD = 5 V,
fSCLK = 25 MHz,
TA = 25C,
Power Down SCLK = Free Running
1.2
5 V VDD
1.6
1.5
1.4
TA = 25C
fs = 1.25 MSPS,
fSCLK = 25 MHz
0.2
0.20
3.075
3.8
4.525
0
0
5.25
0
5
10
15
20
fSCLK − SCLK Frequency − MHz
VDD − Supply Voltage − V
Figure 6.
25
0
50
100
150 200 250
300 350 400
450
fs − Sample Rate − KSPS
Figure 7.
Figure 8.
ANALOG INPUT
LEAKAGE CURRENT
vs
FREE-AIR TEMPERATURE
30
20
Leakage Current − nA
I DD − Supply Current − mA
1.7
SUPPLY CURRENT
vs
SAMPLE RATE
10
@ 5 V Input
0
−10
−20
@ 0 V Input
−30
−40
−40 −20
20
60
80 100
0
40
TA − Free-Air Temperature − C
120
Figure 9.
11
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7887
SIGNAL-TO-NOISE
AND DISTORTION
vs
SUPPLY VOLTAGE
62
61.7
61.5
61.3
61.1
60.9
60.7
60.5
1
10
100
fi − Input Frequency − kHz
61.7
61.6
61.5
61.4
61.3
61.2
−82
−83
−84
−85
−86
−87
−88
−89
61.1
3.075
3.8
4.525
−90
5.25
1
10
fi − Input Frequency − kHz
100
Figure 11.
Figure 12.
TOTAL HARMONIC DISTORTION
vs
SUPPLY VOLTAGE
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE
vs
SUPPLY VOLTAGE
85
−82
−83
−84
−85
−86
−87
−88
−89
85
fs = 1.25 MSPS,
TA = 25C,
VDD = 5 V
84.5
SFDR − Spurious Free Dynamic Range − dB
fs = 1.25 MSPS,
fi = 100 kHz,
TA = 25C
SFDR − Spurious Free Dynamic Range − dB
84
83.5
83
82.5
82
81.5
81
80.5
2.35
3.075
3.8
4.525
VDD − Supply Voltage − V
5.25
100
84
83
82.5
82
81.5
81
80.5
3.8
3.075
4.525
VDD − Supply Voltage − V
Figure 13.
Figure 14.
Figure 15.
OFFSET ERROR
vs
SUPPLY VOLTAGE
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
GAIN ERROR
vs
SUPPLY VOLTAGE
0.8
fs = 1.25 MSPS,
VDD = 5 V
0.8
E O − Offset Error − LSBs
0.2
0
−0.2
−0.4
0.4
0.2
0
−0.2
0.4
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.6
−0.8
−0.8
−0.8
3.075
3.8
4.525
VDD − Supply Voltage − V
Figure 16.
5.25
−1
−40
fs = 1.25 MSPS,
TA = 25C
0.6
0.6
0.4
5.25
1
1
fs = 1.25 MSPS,
TA = 25C
0.6
−1
2.35
fs = 1.25 MSPS,
fi = 100 kHz,
TA = 25C
83.5
fi − Input Frequency − kHz
1
0.8
10
1
84.5
80
2.35
80
−90
E G − Gain Error − LSBs
THD − Total Harmonic Distortion − dB
61.8
Figure 10.
−81
E O − Offset Error − LSBs
fs = 1.25 MSPS,
TA = 25C,
VDD = 5 V
−81
VDD − Supply Voltage − V
−80
12
−80
fs = 1.25 MSPS,
fi = 100 kHz,
TA = 25C
61.9
61
2.35
1000
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
THD − Total Harmonic Distortion − dB
fs = 1.25 MSPS,
TA = 25C,
VDD = 5 V
61.9
SINAD − Signal-to-Noise and Distortion − dB
SINAD − Signal-to-Noise and Distortion − dB
SIGNAL-TO-NOISE
AND DISTORTION
vs
INPUT FREQUENCY
−20
0
20
40
60
80
100 120
TA − Free-Air Temperature − °C
Figure 17.
−1
2.35
3.075
3.8
4.525
VDD − Supply Voltage − V
Figure 18.
5.25
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7887 (continued)
GAIN ERROR
vs
FREE-AIR TEMPERATURE
1
0.8
fs = 1.25 MSPS,
VDD = 5 V
E G − Gain Error − LSBs
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
−40 −20
0
20
40
60
80
100
120
TA − Free-Air Temperature − °C
Figure 19.
DNL − LSBs
DNL
0.5
0.4
0.3
0.2
0.1
VDD = 2.35 V,
fs = 1.25 MSPS,
TA = 25C
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
256
512
768
1024
768
1024
Output Code
Figure 20.
INL − LSBs
INL
0.5
0.4
0.3
0.2
0.1
VDD = 2.35 V,
fs = 1.25 MSPS,
TA = 25C
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
256
512
Output Code
Figure 21.
13
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7887 (continued)
FFT
0
VDD = 2.35 V,
fs = 1.25 MSPS,
TA = 25C
fi = 100 kHz,
8192 Points
Amplitude − dB
−20
−40
−60
−80
−100
−120
−140
0
125000
250000
375000
fi − Input Frequency − kHz
Figure 22.
14
500000
625000
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7888
SIGNAL-TO-NOISE
AND DISTORTION
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE
AND DISTORTION
vs
SUPPLY VOLTAGE
49.8
49.7
49.6
49.5
49.4
49.3
49.2
49.1
1
10
100
fi − Input Frequency − kHz
fs = 1.25 MSPS,
fi = 100 kHz,
TA = 25C
49.9
49.8
49.7
49.6
49.5
49.4
49.3
49.2
49.1
VDD = 5 V,
fs = 1.25 MSPS,
TA = 25C
−65.5
−66
−66.5
−67
−67.5
−68
−68.5
−69
−69.5
49
2.35
1000
THD − Total Harmonic Distortion − dB
49.9
SINAD − Signal-to-Noise and Distortion − dB
−70
3.075
3.8
4.525
VDD − Supply Voltage − V
5.25
1
10
fi − Input Frequency − kHz
100
Figure 23.
Figure 24.
Figure 25.
TOTAL HARMONIC DISTORTION
vs
SUPPLY VOLTAGE
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE
vs
SUPPLY VOLTAGE
−66
−66.5
−67
−67.5
−68
−68.5
−69
−69.5
−70
2.35
3.075
3.8
4.525
79.5
79
78.5
78
77.5
77
76.5
76
75.5
75
5.25
VDD = 5 V,
fs = 1.25 MSPS,
TA = 25C
1
VDD − Supply Voltage − V
10
84
82
81
80
79
78
77
76
75
2.35
100
fi = 100 kHz,
fs = 1.25 MSPS,
TA = 25C
83
3.075
3.8
4.525
Figure 26.
Figure 27.
Figure 28.
OFFSET ERROR
vs
SUPPLY VOLTAGE
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
GAIN ERROR
vs
SUPPLY VOLTAGE
0.3
0.3
fs = 1.25 MSPS,
TA = 25C
0.2
E O − Offset Error − LSBs
0.2
0.1
0
−0.1
−0.2
fs = 1.25 MSPS,
TA = 25C
fs = 1.25 MSPS,
VDD = 5 V
0.2
0.1
0
−0.1
3.8
4.525
VDD − Supply Voltage − V
Figure 29.
5.25
−0.3
−40
0.1
0
−0.1
−0.2
−0.2
3.075
5.25
VDD − Supply Voltage − V
fi − Input Frequency − kHz
0.3
−0.3
2.35
SFDR − Spurious Free Dynamic Range − dB
−65.5
85
80
fi = 100 kHz,
fs = 1.25 MSPS,
TA = 25C
SFDR − Spurious Free Dynamic Range − dB
−65
E G − Gain Error − LSBs
SINAD − Signal-to-Noise and Distortion − dB
fs = 1.25 MSPS,
TA = 25C,
VDD = 5 V
49
THD − Total Harmonic Distortion − dB
−65
50
50
E O − Offset Error − LSBs
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
−7
26
59
92
TA − Free-Air Temperature − °C
Figure 30.
125
−0.3
2.35
3.075
3.8
4.525
VDD − Supply Voltage − V
5.25
Figure 31.
15
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7888 (continued)
GAIN ERROR
vs
FREE-AIR TEMPERATURE
0.3
fs = 1.25 MSPS,
TA = 25C
E G − Gain Error − LSBs
0.2
0.1
0
−0.1
−0.2
−0.3
−40
−7
26
59
92
125
TA − Free-Air Temperature − °C
Figure 32.
DNL
0.5
DNL − LSBs
0.4
0.3
VDD = 2.35 V,
fs = 1.25 MSPS,
TA = 25C
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
64
128
192
256
192
256
Output Code
Figure 33.
INL − LSBs
INL
0.5
0.4
0.3
0.2
0.1
VDD = 2.35 V,
fs = 1.25 MSPS,
TA = 25C
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
64
128
Output Code
Figure 34.
16
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7888 (continued)
FFT
0
TA = 25C
fi = 100 kHz,
8192 Points
Amplitude − dB
−20
−40
−60
−80
−100
−120
0
125000
250000
375000
500000
625000
fi − Input Frequency − kHz
Figure 35.
17
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
APPLICATION INFORMATION
VDD
20 60 IN
16 pF
60 5 pF
GND
Figure 36. Typical Equivalent Sampling Circuit
Driving the VIN and VDD Pins of the ADS7887 and ADS7888
The VIN input to the ADS7887 and ADS7888 should be driven with a low impedance source. In most cases
additional buffers are not required. In cases where the source impedance exceeds 200 Ω, using a buffer would
help achieve the rated performance of the converter. The THS4031 is a good choice for the driver amplifier
buffer.
The reference voltage for the ADS7887 and ADS7888 A/D converters are derived from the supply voltage
internally. The devices offer limited low-pass filtering functionality on-chip. The supply to these converters should
be driven with a low impedance source and should be decoupled to the ground. A 1-µF storage capacitor and a
10-nF decoupling capacitor should be placed close to the device. Wide, low impedance traces should be used to
connect the capacitor to the pins of the device. The ADS7887 and ADS7888 draw very little current from the
supply lines. The supply line can be driven by either:
• Directly from the system supply.
• A reference output from a low drift and low drop out reference voltage generator like REF3030 or REF3130.
The ADS7887 and ADS7888 can operate off a wide range of supply voltages. The actual choice of the
reference voltage generator would depend upon the system. Figure 38 shows one possible application
circuit.
• A low-pass filtered version of the system supply followed by a buffer like the zero-drift OPA735 can also be
used in cases where the system power supply is noisy. Care should be taken to ensure that the voltage at
the VDD input does not exceed 7 V (especially during power up) to avoid damage to the converter. This can
be done easily using single supply CMOS amplifiers like the OPA735. Figure 39 shows one possible
application circuit.
VDD
1 F
VDD
CS
VIN
SDO
GND
SCLK
10 nF
Figure 37. Supply/Reference Decoupling Capacitors
5V
REF3030
IN
1 F
3V
OUT
VDD
CS
VIN
SDO
GND
SCLK
GND
1 F
10 nF
Figure 38. Using the REF3030 Reference
18
ADS7887
ADS7888
www.ti.com
SLAS468 – JUNE 2005
APPLICATION INFORMATION (continued)
5V
C1
R1
10 7V
_
R2
VDD
CS
VIN
SDO
GND
SCLK
+
1 F
1 F
10 nF
Figure 39. Buffering with the OPA735
19
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS7887SDBVR
ACTIVE
SOT-23
DBV
6
3000
TBD
Call TI
Call TI
ADS7887SDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
ADS7887SDBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
ADS7887SDCKR
ACTIVE
SC70
DCK
6
3000
TBD
Call TI
Call TI
ADS7887SDCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
ADS7887SDCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
ADS7888SDBVR
ACTIVE
SOT-23
DBV
6
3000
TBD
Call TI
Call TI
ADS7888SDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
ADS7888SDBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
ADS7888SDCKR
ACTIVE
SC70
DCK
6
3000
TBD
Call TI
Call TI
ADS7888SDCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
ADS7888SDCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
6
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-3/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2005, Texas Instruments Incorporated