BB ADS852

®
ADS852
PRELIMINARY INFORMATION
SUBJECT TO CHANGE
WITHOUT NOTICE
14-Bit, 65MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
TM
● FLEXIBLE CLOCKING:
Differential or Single-Ended
Accepts Sine or Square Wave Clocking
Down to 0.5Vp-p
Variable Threshold Level
FEATURES
● HIGH DYNAMIC RANGE:
High SFDR: 100dB at 20MHz fIN
High SNR: 75dB at 20MHz fIN
● PREMIUM TRACK/HOLD:
High Bandwidth: 1GHz
Low Jitter: 0.25pS rms
Differential or Single-Ended Inputs
Selectable Full-Scale Input Range
APPLICATIONS
● BASESTATION WIDEBAND RADIOS:
CDMA, GSM, TDMA, 3G, AMPS, NMT
● TEST INSTRUMENTATION
● CCD IMAGING
DESCRIPTION
The ADS852 is a high-dynamic range 14-bit, 65MHz
pipelined analog-to-digital converter. It includes a highbandwidth linear track/hold that gives excellent spurious
performance up to and beyond the Nyquist rate. This highbandwidth track/hold also has a low jitter of only 0.25pS
rms, leading to excellent SNR performance. The clock input
can accept a low level differential sine wave or square wave
signal down to 0.5Vp-p, further improving the SNR performance. It also accepts a single-ended clock signal and has
flexible threshold levels.
The ADS852 has a 4Vp-p differential input range (2Vp-p x
2 inputs, +16dBm) for optimum signal-to-noise ratio. The
differential operation gives the lowest even-order harmonic
components. A lower input voltage of 3Vp-p or 2Vp-p can
also be selected using the internal references, further optimizing SFDR. Alternatively, a single-ended input range can
be used by tying the IN input to the common-mode voltage
if desired.
The ADS852 also provides an over-range flag that indicates
when the input signal has exceeded the converter’s full-scale
range. This flag can also be used to reduce the gain of the
front end signal conditioning circuitry. It also employs
digital error correction techniques to provide excellent differential linearity for demanding imaging applications. The
ADS852 is available in a small 48-lead TQFP package.
+VS
CLK
ADS852
Timing Circuitry
CLK
2Vp-p
IN
14-Bit
Pipelined
A/D Core
T/H
2Vp-p
IN
Error
Correction
Logic
3-State
Outputs
CM
(+2.5V)
OVR
Reference Ladder
and Driver
Reference and
Mode Select
REFT
VREF SEL1 SEL2
D0
•
•
•
D13
REFB
OE VDRV
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1998 Burr-Brown Corporation
PDS-1442
Printed in U.S.A. June, 1998
SPECIFICATIONS
At TA = full specified temperature range, differential input range = 1.5V to 3.5V, sampling rate = 65MHz, and external reference, unless otherwise noted.
ADS852Y
PARAMETER
CONDITIONS
MIN
RESOLUTION
SPECIFIED TEMPERATURE RANGE
ANALOG INPUT
Standard Differential Input Range
Optional Single-Ended Input Range
Common-Mode Voltage
Optional Input Ranges
Analog Input Bias Current
Track-Mode Input Bandwidth
Input Impedance
Ambient Air
(2Vp-p x 2, +16dBm)
4Vp-p
DIGITAL INPUTS
Convert Command (Start Conversion)
Logic Family (Other Clock Inputs)
High Level Input Current(4) (VIN = 5V)
Low Level Input Current (VIN = 0V)
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
DIGITAL OUTPUTS
Logic Family
Logic Coding
Low Output Voltage (IOL = 50µA to 1.6mA)
High Output Voltage, (IOH = 50µA to 0.5mA)
Low Output Voltage, (IOL = 50µA to 1.6mA)
High Output Voltage, (IOH = 50µA to 1.6mA)
3-State Enable Time
3-State Disable Time
Output Capacitance
–3dBFS
Bits
°C
1.5
0.5
3.5
4.5
±0.5
±0.5
Guaranteed
±0.5
Samples/s
Clk Cyc
±1.0
LSB
LSB
±2.0
LSBs
105
100
100
dBFS(2)
dBFS
dBFS
–95
dBc
75
75
75
dBFS
dBFS
dBFS
75
75
74
TBD
3
0.25
2
5
dB
dB
dBFS
LSBs rms
ns
ps rms
ns
ns
+0.5
+VS
+3V/+5V Logic Compatible CMOS
100
10
+2.0
+1.0
5
Vp-p
Input Grounded
VDRV = 3V
VDRV = 5V
OE = L
OE = H
®
2
V
V
V
V
µA
GHz
MΩ || pF
65M
7
Rising Edge of Convert Clock
UNITS
–40 to +85
1M
ACCURACY (Internal Reference, = 2V, Unless Otherwise Noted)
Zero Error (Referred to –FS)
at 25°C
Zero Error Drift (Referred to –FS)
Gain Error(5)
at 25°C
Gain Error Drift(5)
Gain Error(6)
at 25°C
Gain Error Drift(6)
Power Supply Rejection of Gain
∆ VS = ±5%
Internal REF Tolerance
Deviation from Ideal
External REF Voltage Range
Reference Input Resistance
ADS852
MAX
2.5
2Vp-p (+10dBm) or 3Vp-p (+13dBm)
1
1
1.25 || 9
Selectable
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 2.2MHz
f = 20MHz
No Missing Codes
Integral Nonlinearity Error, f = 1MHz
Spurious Free Dynamic Range(1)
f = 2.2MHz
f = 20MHz
f = 31MHz
Two-Tone Intermodulation Distortion(3)
f = 4.5MHz and 5.5MHz (–7dB each tone)
Signal-to-Noise Ratio (SNR)
f = 2.2MHz
f = 20MHz
f = 31MHz
Signal-to-(Noise + Distortion) (SINAD)
f = 2.2MHz
f = 20MHz
f = 31MHz
Output Noise
Aperture Delay Time
Aperture Jitter
Overvoltage Recovery Time
Full-Scale Step Acquisition Time
TYP
14 Guaranteed
µA
µA
V
V
pF
+3V/+5V Logic Compatible CMOS
Straight Offset Binary
+0.2
+2.5
+0.2
+2.5
20
40
2
10
5
V
V
V
V
ns
ns
pF
0.5
12
±1.5
38
±0.75
20
68
±10
2
1.0
%FS
ppm/°C
%FS
ppm/°C
%FS
ppm/°C
dB
mV
V
kΩ
0.9
3.0
±2.5
±1.5
±50
2.025
SPECIFICATIONS (CONT)
At TA = full specified temperature range, differential input range = 1.5V to 3.5V, sampling rate = 65MHz, and external reference, unless otherwise noted.
ADS852Y
PARAMETER
POWER SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Output Driver Supply Current (VDRV)
Power Dissipation: VDRV = 5V
VDRV = 3V
Power Down
Thermal Resistance, θJA
48-Lead TQFP
CONDITIONS
MIN
TYP
MAX
UNITS
Operating
Operating
+4.75
+5.0
120
12
670
650
20
+5.25
V
mA
mA
mW
mW
mW
Operating
740
720
°C/W
NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone
intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental
envelope. (4) A 50kΩ pull-down resistor is inserted internally. (5) Includes internal reference. (6) Excludes internal reference.
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
+VS ....................................................................................................... +6V
Analog Input ........................................................... (–0.3V) to (+VS +0.3V)
Logic Input ............................................................. (–0.3V) to (+VS +0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
ADS852Y
48-Lead TQFP
xxx
TEMPERATURE
RANGE
–40°C to +85°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
3
ADS852
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O
DESIGNATOR
BYP
+VS
+VS
+VS
GND
CLK
CLK
GND
GND
OVR
DV
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
DESCRIPTION
PIN
Bypass Point
Supply Voltage
Supply Voltage
Supply Voltage
Ground
Clock Input
Complementary Clock Input
Ground
Ground
Overrange Indicator
Data Valid Pulse: HI = Data Vaild
Most Significant Bit (MSB)
Data Bit 12
Data Bit 11
Data Bit 10
Data Bit 9
Data Bit 8
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Least Significant Bit (LSB)
I/O
DESIGNATOR
26
27
28
VDRV
GND
OE
29
30
I
I
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PD
BTC
GND
SEL2
SEL1
VREF
GND
GND
GND
GND
REFN
CM
REFP
GND
GND
IN
GND
IN
+VS
+VS
I
I
DESCRIPTION
Output Bit Driver Voltage Supply
Ground
Output Enable: HI = High Impedance;
LO or Floating: Normal Operation
Power Down: HI = Power Down; LO = Normal
HI = Binary Two’s Complement;
LO = Straight Binary
Ground
Reference Select 2: See Table
Reference Select 1: See Table
Internal Reference Voltage
Ground
Ground
Ground
Ground
Bottom Reference Voltage Bypass
Common-Mode Voltage (mid-scale)
Top Reference Voltage Bypass
Ground
Ground
Complementary Analog Input
Ground
Analog Input
Supply Voltage
Supply Voltage
+VS
+VS
IN
GND
IN
GND
GND
REFP
CM
REFN
GND
GND
PIN DIAGRAM
48
47
46
45
44
43
42
41
40
39
38
37
BYP
1
36 GND
+VS
2
35 GND
+VS
3
34 VREF
+VS
4
33 SEL1
GND
5
32 SEL2
CLK
6
CLK
7
30 BTC
GND
8
29 PD
GND
9
28 OE
31 GND
ADS852Y
OVR 10
27 GND
DV 11
26 VDRV
13
14
15
16
17
18
19
20
21
22
23
24
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
25 D0 (LSB)
D12
D13 (MSB) 12
®
ADS852
4
TIMING DIAGRAM
N+2
N+1
Analog In
N+4
N+3
N
tD
N+5
tL
tCONV
N+7
N+6
tH
Clock
7 Clock Cycles
t2
Data Out
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
Data Invalid
SYMBOL
t CONV
tL
tH
tD
t1
t2
t1
DESCRIPTION
MIN
Convert Clock Period
Clock Pulse Low
Clock Pulse High
Aperture Delay
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
15.4
7.6
7.6
TYP
MAX
UNITS
1µs
ns
ns
ns
ns
ns
ns
t CONV /2
t CONV /2
3
3.9
12
TABLE, REFERENCE/FULL SCALE RANGE SELECT
DESIRED
FULL SCALE RANGE
SEL1
SEL2
INTERNAL
VREF
4Vp-p (2Vp-p x 2, +16dBm)
3Vp-p (1.5Vp-p x 2, +13dBm)
2Vp-p (1Vp-p x 2, +10dBm)
GND
GND
VREF
GND
+VS
GND
2V
1.5V
1V
For External Reference Operation, tie VREF to +VS, the full scale range will be 2X the reference value. For instance, selecting a 2V External Reference will set
the full scale values of 1.5V to 3.5V for both IN and IN inputs.
®
5
ADS852