OPA820 SBOS303A − JUNE 2004 − REVISED JULY 2004 Unity-Gain Stable, Low-Noise, Voltage-Feedback Operational Amplifier FEATURES D D D D D D DESCRIPTION HIGH BANDWIDTH (240MHz, G = +2) HIGH OUTPUT CURRENT (±110mA) LOW INPUT NOISE (2.5nV/√Hz) LOW SUPPLY CURRENT (5.6mA) FLEXIBLE SUPPLY VOLTAGE Dual ±2.5V to ±6V Single +5V to +12V EXCELLENT DC ACCURACY Maximum 25°C Input Offset Voltage = ±750µV Maximum 25°C Input Offset Current = ±400nA APPLICATIONS D D D D D D D D D LOW-COST VIDEO LINE DRIVERS ADC PREAMPLIFIERS ACTIVE FILTERS LOW-NOISE INTEGRATORS PORTABLE TEST EQUIPMENT OPTICAL CHANNEL AMPLIFIERS LOW-POWER, BASEBAND AMPLIFIERS CCD IMAGING CHANNEL AMPLIFIERS OPA650 AND OPA620 UPGRADE The OPA820 provides a wideband, unity-gain stable, voltage-feedback amplifier with a very low input noise voltage and high output current using a low 5.6mA supply current. At unity-gain, the OPA820 gives > 800MHz bandwidth with < 1dB peaking. The OPA820 complements this high-speed operation with excellent DC precision in a low-power device. A worst-case input offset voltage of ±750µV and an offset current of ±400nA give excellent absolute DC precision for pulse amplifier applications. Minimal input and output voltage swing headroom allow the OPA820 to operate on a single +5V supply with > 2VPP output swing. While not a rail-to-rail (RR) output, this swing will support most emerging analog-to-digital converter (ADC) input ranges with lower power and noise than typical RR output op amps. Exceptionally low dG/dP (0.01%/0.03°) supports low-cost composite video line driver applications. Existing designs can use the industry-standard pinout SO-8 package while emerging high-density portable applications can use the SOT23-5. Offering the industry’s lowest thermal impedance in a SOT package, along with full specification over both the commercial and industrial temperature ranges, gives solid performance over a wide temperature range. RELATED PRODUCTS SINGLES DUALS TRIPLES QUADS OPA354 OPA690 — — — OPA2354 OPA2690 OPA2652 OPA2822 — — OPA3690 — — — OPA4354 — — — OPA4820 FEATURES CMOS RR Output High Slew Rate SOT23-8 Low Noise Quad OPA820 +5V +5V 2kΩ RS 0.1µF 24.9Ω VIN REFT (+3V) 2kΩ IN OPA820 50Ω 100pF ADS850 14−Bit 10MSPS −5V 402Ω 2kΩ IN 0.1µF 402Ω 2kΩ (+2V) REFB (+1V) VREF SEL AC-Coupled, 14-Bit ADS850 Interface Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2004, Texas Instruments Incorporated ! ! www.ti.com "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ABSOLUTE MAXIMUM RATINGS(1) Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6.5VDC Internal Power Dissipation . . . . . . . . . . . . See Thermal Information Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2V Input Common-Mode Voltage Range . . . . . . . . . . . . . . . . . . . . ±VS Storage Temperature Range . . . . . . . . . . . . . . . . . −40°C to +125°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C ESD Rating Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . +3000V Charge Device Model (CDM) . . . . . . . . . . . . . . . . . . . . +1000V Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING OPA820 SO-8 D −45°C to +85°C OPA820 OPA820ID Rails, 100 ″ ″ ″ ″ ″ OPA820IDR Tape and Reel, 2500 OPA820 SOT23-5 DBV −45°C to +85°C NSO OPA820IDBVT Tape and Reel, 250 ″ ″ ″ ″ ″ OPA820IDBVR Tape and Reel, 3000 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY (1) For the most current specification and package information, refer to our web site at www.ti.com. PIN CONFIGURATION 1 8 NC Inverting Input 2 7 +VS Noninverting Input 3 6 Output −VS 4 5 NC SOT Output 1 −VS 2 Noninverting Inut 3 5 NC Top View +VS 4 Inverting Input 2 NSO 1 NC = No Connection 5 4 SO 3 Top View Pin Orientation/Package Marking 2 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. OPA820ID, IDBV TYP PARAMETER AC PERFORMANCE Small-Signal Bandwidth Gain-Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise Time and Fall Time Settling Time to 0.02% to 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise Differential Gain Differential Phase DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Input Offset Voltage Drift Input Bias Current Average Input Bias Current Drift Input Offset Current Inverting Input Bias Current Drift INPUT Common-Mode Input Range (CMIR)(5) Common-Mode Rejection Ratio Input Impedance Differential Mode Common Mode OUTPUT Output Voltage Swing Output Current Short-Circuit Output Current Closed-Loop Output Impedance POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (−PSRR) THERMAL CHARACTERISTICS Specification: ID, IDBV Thermal Resistance, qJA D SO-8 DBV SOT23-5 MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C(2) −40°C to +85°C(2) 170 23 220 160 21 204 155 20 200 192 186 180 −85 −90 −95 −110 2.5 1.7 0.01 0.03 −81 −85 −90 −105 2.7 2.6 −80 −83 −89 −102 2.8 2.8 66 ±0.2 62 ±0.75 −9 −17 ±100 ±400 VCM = 0V, Input-Referred ±4.0 85 ±3.8 76 VCM = 0V VCM = 0V 18 0.8 6 1.0 No Load RL = 100Ω VO = 0 Output Shorted to Ground G = +2, f ≤ 100kHz ±3.7 ±3.6 ±110 ±125 0.04 CONDITIONS +25°C G = +1, VO = 0.1VPP, RF = 0Ω G = +2, VO = 0.1VPP G = +10, VO = 0.1VPP G ≥ 20 G = +2, VO = 0.1VPP VO = 0.1VPP, RF = 0 G = +2, VO = 2VPP G = +2, 2V Step G = +2, VO = 0.2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 1MHz, VO = 2VPP RL = 200Ω RL ≥ 500Ω RL = 200Ω RL ≥ 500Ω f > 100kHz f > 100kHz G = +2, PAL, VO = 1.4VPP, RL = 150Ω G = +2, PAL, VO = 1.4VPP, RL = 150Ω 800 240 30 280 38 0.5 85 240 1.5 22 18 VO = 0V, Input-Referred VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V UNITS MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns typ min min min typ typ typ min typ typ typ C B B B C C C B C C C −79 −81 −88 −100 2.9 3.0 dBc dBc dBc dBc nV/√Hz pA/√Hz % ° max max max max max max typ typ B B B B B B C C 61 ±1.0 4 −19 30 ±600 5 60 ±1.2 4 −23 50 ±700 5 dB mV µV/°C µΑ nA/°C nA nA/°C min max max max max max max A A B A B A B ±3.7 75 ±3.6 73 V dB min min A A kΩ pF MΩ pF typ typ C C V V mA mA Ω min min min typ typ A A A C C V v mA mA dB typ max max min min C A A A A °C typ C °C/W °C/W typ typ C C ±3.5 ±3.5 ±90 ±3.45 ±3.45 ±80 ±3.4 ±3.4 ±75 ±6.0 5.75 5.45 64 ±6.0 6.2 5.0 63 ±6.0 6.4 4.8 62 ±5 VS = ±5V VS = ±5V Input Referred 5.6 5.6 72 −40 to +85 Junction-to-Ambient Junction-to-Ambient 125 150 TEST LEVEL MIN/ MAX (3) (1) Junction temperature = ambient for +25°C specifications. Junction temperature = ambient at low temperature limits; junction temperature = ambient +9°C at high temperature limit for over temperature. Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V CM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ± CMIR limits. (2) (3) 3 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 ELECTRICAL CHARACTERISTICS: VS = +5V Boldface limits are tested at +25°C. RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. OPA820ID, IDBV TYP PARAMETER AC PERFORMANCE Small-Signal Bandwidth Gain-Bandwidth Product Peaking at a Gain of 1 Large-Signal Bandwidth Slew Rate Rise Time and Fall Time Settling Time to 0.02% to 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Input Offset Voltage Drift Input Bias Current Average Input Bias Current Drift Input Offset Current Inverting Input Bias Current Drift INPUT Least Positive Input Voltage Most Positive Input Voltage Common-Mode Rejection Ratio (CMRR) Input Impedance Differential Mode Common Mode OUTPUT Most Positive Output Voltage Least Positive Output Voltage Output Current Short-Circuit Output Current Closed-Loop Output Impedance POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (+PSRR) THERMAL CHARACTERISTICS Specification: ID, IDBV Thermal Resistance, qJA D SO-8 DBV SOT23-5 MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C(2) −40°C to +85°C(2) 168 21 200 155 20 190 151 19 185 145 140 135 −80 −83 −100 −98 2.5 1.6 −76 −79 −92 −95 2.8 2.5 −75 −77 −91 −93 2.9 2.7 65 ±0.3 60 ±1.1 −8 −16 ±100 ±400 VCM = 2.5V, Input-Referred 0.9 4.5 83 1.1 4.2 74 VCM = 2.5V VCM = 2.5V 15 1 5 1.3 No Load RL = 100Ω to 2.5V No Load RL = 100Ω to 2.5V VO = 2.5V Output Shorted to Ground G = +2, f ≤ 100kHz +3.9 +3.8 +1.2 +1.2 ±105 ±115 0.04 CONDITIONS +25°C G = +1, VO = 0.1VPP, RF = 0Ω G = +2, VO = 0.1VPP G = +10, VO = 0.1VPP G ≥ 20 VO = 0.1VPP, RF = 0Ω G = +2, VO = 2VPP G = +2, 2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 1MHz, VO = 2VPP RL = 200Ω RL ≥ 500Ω RL = 200Ω RL ≥ 500Ω f > 100kHz f > 100kHz 550 230 28 260 0.5 70 200 1.7 24 21 VO = 2.5V, RL = 100Ω VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V UNITS MHz MHz MHz MHz dB MHz V/µs ns ns ns typ min min min typ typ min typ typ typ C B B B C C B C C C −74 −75 −90 −92 3.0 2.9 dBc dBc dBc dBc nV/√Hz pA/√Hz max max max max max max B B B B B B 59 ±1.4 4 −18 30 ±600 5 58 ±1.6 4 −22 50 ±700 5 dB mV µV/°C µΑ nA/°C nA nA/°C min max max max max max max A A B A B A B 1.2 4.1 73 1.3 4.0 72 V V dB min max min A A A kΩ pF MΩ pF typ typ C C V V V V mA mA Ω min min max max min typ typ A A A A A C C V V mA mA dB typ max max min typ C A A A C °C typ C °C/W °C/W typ typ C C +3.8 +3.7 +1.3 +1.3 ±80 +3.75 +3.65 +1.35 +1.35 ±70 +3.7 +3.6 +1.4 +1.4 ±65 +12 5.4 4.4 +12 5.5 4.25 +12 5.6 4.1 +5 VS = +5V VS = +5V Input-Referred 5.0 5.0 68 −40 to +85 Junction-to-Ambient Junction-to-Ambient 125 150 TEST LEVEL MIN/ MAX (3) (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +7°C at high temperature limit for over temperature. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ± CMIR limits. 4 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 TYPICAL CHARACTERISTICS: VS = ±5V RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE 3 0 G = −1 0 G = +5 −3 Normalized Gain (dB) G = +2 −6 G = +10 −9 −12 VO = 0.1VPP RL = 100Ω See Figure 1 −15 G = −2 −3 G = −5 −6 −9 G = −10 −12 VO = 0.1VPP RL = 100Ω See Figure 2 −15 −18 −18 1M 10M 100M 1G 1 10 Frequency (Hz) NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE 9 VO = 0.5VPP −3 VO = 1VPP 0 Gain (dB) Gain (dB) VO = 0.5VPP 0 3 VO = 2VPP −3 VO = 4VPP −6 VO = 1VPP −6 VO = 2VPP −9 VO = 4VPP −12 G = +2 RL = 100Ω See Figure 1 −9 G = −1 RL = 100Ω See Figure 2 −15 −12 −18 1 10 100 500 1 10 Frequency (MHz) 0.2 1.5 1.0 0.1 0.5 Small Signal ± 100mV Left Scale 0 −0.1 0 −0.5 −0.2 −1.0 G = +2 See Figure 1 −1.5 −0.4 −2.0 Time (10ns/div) Small−Signal Output Voltage (100mV/div) Large Signal ± 1V Right Scale 0.3 500 INVERTING PULSE RESPONSE 2.0 Large−Signal Output Voltage (500mV/div) 0.4 100 Frequency (MHz) NONINVERTING PULSE RESPONSE Small−Signal Output Voltage (100mV/div) 500 INVERTING LARGE−SIGNAL FREQUENCY RESPONSE 3 6 −0.3 100 Frequency (MHz) 0.4 0.3 2.0 G = −1 See Figure 2 1.5 0.2 1.0 0.1 0 −0.1 −0.2 −0.3 0.5 Small Signal ± 100mV Left Scale Large Signal ± 1V Right Scale −0.4 0 −0.5 −1.0 −1.5 −2.0 Large−Signal Output Voltage (500mV/div) Normalized Gain (dB) INVERTING SMALL−SIGNAL FREQUENCY RESPONSE 3 G = +1 RF = 0Ω Time (10ns/div) 5 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 TYPICAL CHARACTERISTICS: VS = ±5V (continued) RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE f = 1MHz VO = 2VPP G = +2V/V −75 −80 2nd−Harmonic −85 −90 3rd−Harmonic −95 See Figure 1 −100 100 1MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE −75 Harmonic Distortion (dBc) Harmonic Distortion (dBc) −70 −80 2nd−Harmonic −85 −90 3rd−Harmonic −95 −100 See Figure 1 −105 2.5 1k 3.0 3.5 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 2nd−Harmonic −75 −80 −85 −90 3rd−Harmonic −95 6.0 f = 1MHz R L = 200Ω G = +2V/V −80 −85 −90 2nd−Harmonic −95 −100 3rd−Harmonic See Figure 1 See Figure 1 −105 0.1 1 −110 0.1 10 1 HARMONIC DISTORTION vs NONINVERTING GAIN f = 1MHz RL = 200Ω VO = 2VPP −75 −80 HARMONIC DISTORTION vs INVERTING GAIN −70 2nd−Harmonic Harmonic Distortion (dBc) −70 −85 −90 3rd−Harmonic −95 −100 −105 1 −75 2nd−Harmonic −80 −85 3rd−Harmonic −90 −95 −100 10 Gain (V/V) f = 1MHz RL = 200Ω VO = 2VPP See Figure 2 See Figure 1 −110 10 Output Voltage (VPP) Frequency (MHz) Harmonic Distortion (dBc) 5.5 −105 −100 6 5.0 −75 VO = 2VPP RL = 100Ω G = +2V/V −70 4.5 HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs FREQUENCY −65 4.0 Supply Voltage (±VS) Resistance (Ω) −60 VO = 2VPP RL = 200Ω G = +2V/V 1 10 Gain (| V/V| ) "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 TYPICAL CHARACTERISTICS: VS = ±5V (continued) RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. TWO−TONE, 3RD−ORDER INTERMODULATION INTERCEPT INPUT VOLTAGE AND CURRENT NOISE 100 50 PI 10 Voltage Noise (2.5nV/√Hz) PO O P A 82 0 5 0Ω 2 00 Ω Intercept Point (+dBm) Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) 45 40 40 2Ω 40 2Ω 35 30 25 20 Current Noise (1.7pA/√Hz) 1 100 1k 10k 100k 1M 15 10M 0 Frequency (Hz) 5 Normalized Gain to Capacitive Load (dB) RS (Ω) 0dB Peaking Targeted 10 1 100 8 5 CL = 47pF 4 CL = 100pF 3 2 RS VI 1 50Ω VO OPA 820 CL 0 1kΩ(1) 4 02Ω −1 402Ω −2 NOTE: (1) 1kΩ is o ptional. −3 1 1000 10 100 400 Frequency (MHz) OPEN−LOOP GAIN AND PHASE 80 CMRR 80 70 70 60 Open−Loop Gain (dB) Common−Mode Rejection Ratio (dB) Power−Supply Rejection Ratio (dB) 30 CL = 22pF 6 CMRR AND PSRR vs FREQUENCY 60 25 CL = 10pF 7 Capacitive Load (pF) 90 20 FREQUENCY RESPONSE vs CAPACITIVE LOAD RECOMMENDED RS vs CAPACITIVE LOAD 10 15 Frequency (MHz) 100 1 10 +PSRR 50 40 0 −20 20 log (AOL) −40 −60 50 −80 40 ∠AOL 30 −100 20 −120 20 10 −140 10 0 −160 30 −PSRR 0 1k 10k 100k 1M Frequency (Hz) 10M 100M −10 100 1k 10k 100k 1M Frequency (Hz) 10M 100M 1G Open−Loop Phase (_) 10 −180 7 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 TYPICAL CHARACTERISTICS: VS = ±5V (continued) RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. OUTPUT VOLTAGE AND CURRENT LIMITATIONS Output Current Power Limit Limit 3 1 Output Impedance (Ω) RL = 100Ω 2 VO (V) 10 RL = 25Ω 0 RL = 50Ω −1 −2 −3 Output Current −4 0.1 1W Internal Limit −5 −150 1 Power Limit −100 0.01 −50 0 50 100 150 1k 10k 100k I O (mA) 4 Input Right Scale 4 2 2 1 Output Left Scale 0 0 −2 −1 −2 RL = 100Ω G = +2V/V See Figure 1 Output Voltage (1V/div) 3 Input Voltage (1V/div) Output Voltage (2V/div) 6 −6 −3 −8 5 4 4 3 3 Input Right Scale 2 1 0 0 Output Left Scale −1 −2 −3 −5 0.12 0.24 0.10 0.20 0.08 0.16 dP Negative Video 0.12 0.08 0.02 Input Offset Voltage (mV) 0.28 Differential Phase (_) Differential Gain (%) 0.32 0.04 20 0.5 10 10x Input Offset Current (IOS) Right Scale 0 0 Input Offset Voltage (VOS) Left Scale −0.5 −10 Input Bias Current (IB) Right Scale 0.04 dG Positive Video 2 3 Video Loads 8 1.0 0.36 0.14 1 −4 TYPICAL DC DRIFT OVER TEMPERATURE dG Negative Video 0 −3 −5 0.40 dP Positive Video −2 Time (40ns/div) 0.16 0.06 −1 R L = 100Ω G = −1V/V See Figure 2 COMPOSITE VIDEO dG/dP G = +2V/V 2 1 Time (40ns/div) 0.18 100M 5 −4 −4 0.20 10M INVERTING OVERDRIVE RECOVERY NONINVERTING OVERDRIVE RECOVERY 8 −4 1M Frequency (Hz) Input Voltage (1V/div) 4 CLOSED−LOOP OUTPUT IMPEDANCE vs FREQUENCY 1W Internal 0 4 −1.0 −50 −25 0 25 50 75 Ambient Temperature (_C) 100 −20 125 Input Bias and Offset Current (µV) 5 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 TYPICAL CHARACTERISTICS: VS = ±5V (continued) RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. COMMON−MODE INPUT RANGE AND OUTPUT SWING vs SUPPLY VOLTAGE SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 12 5 Left Scale 9 75 6 Supply Current Right Scale 50 3 Voltage Range (V) Sink/Source Output Current 100 6 Supply Current (mA) Output Current (mA) 125 +VIN 4 −VIN 3 +VOUT 2 −VOUT 1 25 −50 −25 0 25 50 75 100 0 125 0 2.5 Ambient Temperature (_ C) 3.5 4.0 5.0 5.5 6.0 TYPICAL INPUT OFFSET VOLTAGE DISTRIBUTION 2500 Mean = −30µV Standard Deviation = 80µV Total Count = 6115 Common−Mode Input Impedance 2000 Count 1M 100k 1500 1000 Differential Input Impedance 500 10k −730 −660 −580 −510 −440 −370 −290 −220 −150 −70 0 70 150 220 290 370 440 510 580 660 730 0 1k 1k 10k 100k 1M 10M 100M Frequency (Hz) Input Offset Voltage (µV) TYPICAL INPUT OFFSET CURRENT DISTRIBUTION 2000 1800 1600 Mean = 26nA Standard Deviation = 57nA Total Count = 6115 1400 1200 1000 800 600 400 200 0 −380 −342 −304 −266 −228 −190 −152 −114 −76 −38 0 38 76 114 152 190 228 266 304 342 380 100 Count Input Impedance (Ω) 4.5 Supply Voltage (±VS ) COMMON−MODE AND DIFFERENTIAL INPUT IMPEDANCE 10M 3.0 Input Offset Current (nA) 9 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 TYPICAL CHARACTERISTICS: VS = +5V RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE 3 INVERTING SMALL−SIGNAL FREQUENCY RESPONSE G = +1 G = +2 −3 Normalized Gain (dB) G = +5 −6 G = +10 −9 −12 VO = 0.1VPP RL = 100Ω See Figure 3 −15 G = −1 0 G = −2 −3 G = −5 −6 G = −10 −9 −12 VO = 0.1VPP RL = 100Ω See Figure 4 −15 −18 −18 1M 10M 100M 1G 1 10 Frequency (Hz) NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE 9 −3 VO = 2VPP Gain (dB) Normalized Gain (dB) VO = 0.5VPP 0 VO = 1VPP 0 VO = 4VPP −3 −6 VO = 1VPP −6 VO = 2VPP −9 VO = 4VPP −12 G = +2V/V RL = 100Ω See Figure 3 −9 −12 1 G = −1 RL = 100Ω See Figure 4 −15 −18 10 100 600 1 10 Frequency (MHz) Small Signal ± 100mV Left Scale 2.5 2.4 2.5 2.0 2.3 1.5 G = +2 See Figure 3 1.0 2.1 0.5 Time (10ns/div) 10 3.0 Small−Signal Output Voltage (100mV/div) 3.5 2.6 2.2 4.0 Large−Signal Output Voltage (500mV/div) Small−Signal Output Voltage (100mV/div) 2.7 500 INVERTING PULSE RESPONSE 4.5 Large Signal ± 1V Right Scale 100 Frequency (MHz) NONINVERTING PULSE RESPONSE 2.9 2.8 500 INVERTING LARGE−SIGNAL FREQUENCY RESPONSE 3 VO = 0.5VPP 6 3 100 Frequency (MHz) 2.9 2.8 4.5 G = −1 See Figure 4 4.0 2.7 3.5 2.6 2.5 3.0 Small Signal ± 100mV Left Scale 2.4 2.3 2.2 2.5 2.0 Large Signal ± 1V Right Scale 2.1 1.5 1.0 0.5 Time (10ns/div) Large−Signal Output Voltage (500mV/div) Normalized Gain (dB) 0 3 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 TYPICAL CHARACTERISTICS: VS = +5V (continued) RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs LOAD RESISTANCE f = 1MHz VO = 2VPP G = +2V/V 2nd−Harmonic −80 −60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) −75 −85 −90 −95 3rd−Harmonic −100 G = +2V/V R L = 200Ω VO = 2VPP −70 −80 −90 3rd−Harmonic −100 See Figure 3 −105 100 2nd−Harmonic See Figure 3 −110 1k 0.1 1 HARMONIC DISTORTION vs OUTPUT VOLTAGE VO = 2VPP f = 1MHz G = +2V/V RL = 200Ω −80 HARMONIC DISTORTION vs NONINVERTING GAIN −60 2nd−Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) −70 10 Frequency (MHz) Resistance (Ω) −90 3rd−Harmonic −100 f = 1MHz RL = 200Ω VO = 2VPP −70 2nd−Harmonic −80 −90 3rd−Harmonic −100 See Figure 3 See Figure 3 −110 0.1 1 −110 10 1 10 Output Voltage Swing (VPP) Gain (V/V) TWO−TONE, 3RD−ORDER INTERMODULATION INTERCEPT HARMONIC DISTORTION vs INVERTING GAIN 40 f = 1MHz RL = 200Ω VO = 2VPP −75 +5V 806Ω 0.01µF 2nd−Harmonic Intercept Point (+dBm) Harmonic Distortion (dBc) −70 −80 −85 3rd−Harmonic −90 −95 PI 35 806Ω 57.6Ω PO OPA820 200Ω 402Ω 402Ω 30 0.01µF 25 20 See Figure 4 −100 1 10 Gain (| V/V| ) 15 0 5 10 15 20 25 30 Frequency (MHz) 11 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 TYPICAL CHARACTERISTICS: VS = +5V (continued) RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. FREQUENCY RESPONSE vs CAPACITIVE LOAD RECOMMENDED RS vs CAPACITIVE LOAD Normalized Gain to Capacitive Load (dB) 100 10 1 1 10 100 CL = 10pF 7 6 5 CL = 22pF 4 CL = 47pF 3 CL = 100pF 2 +5V 0.01µF 1 806Ω RS VI 57.6Ω 0 806Ω CL −1 402Ω −2 1 10 SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 5 0 Input Offset Voltage (VOS) Left Scale −0.5 −5 −1.0 −10 Input Bias Current (IB) Right Scale 25 50 75 100 Output Current (mA) 10x Input Offset Current (IOS) Right Scale Input Bias and Offset Current (µV) Input Offset Voltage (mV) 10 1.0 0 −15 125 12 100 9 Source Output Current Sink Output Current 75 50 3 25 −50 −25 0 25 50 75 100 0 125 Ambient Temperature (_ C) TYPICAL INPUT OFFSET CURRENT DISTRIBUTION TYPICAL INPUT OFFSET VOLTAGE DISTRIBUTION 3500 2000 Mean = −490µV Standard Deviation = 90µV Total Count = 6115 1800 1600 2500 1400 2000 1200 Count Count 6 Supply Current Ambient Temperature (_C) 3000 300 125 15 −25 100 Frequency (MHz) TYPICAL DC DRIFT OVER TEMPERATURE −1.5 −50 NOTE: (1) 1kΩis optional. 0.01µF −3 1000 1.5 0 1kΩ(1) 402Ω Capacitive Load (pF) 0.5 VO OPA820 1500 Mean = 43nA Standard Deviation = 50nA Total Count = 6115 1000 800 600 1000 400 500 200 0 12 −1.08 −0.97 −0.86 −0.76 −0.65 −0.54 −0.43 −0.32 −0.22 −0.11 0 0.11 0.22 0.32 0.43 0.54 0.65 0.76 0.86 0.97 1.08 −380 −342 −304 −266 −228 −190 −152 −114 −76 −38 0 38 76 114 152 190 228 266 304 342 380 0 Input Offset Voltage (mV) Input Offset Current (nA) Supply Current (mA) RS (Ω) 0dB Peaking Targeted 8 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 APPLICATIONS INFORMATION +5V WIDEBAND VOLTAGE-FEEDBACK OPERATION 0.1µF RT 205Ω 0.01µF 50Ω Source +5V +VS + 0.1µF 2.2µF 50Ω Source VIN RS 50Ω Load 50Ω VO 50Ω OPA820 RF 402Ω RG 402Ω 0.1µF 2.2µF + −VS −5V Figure 1. Gain of +2, High-Frequency Application and Characterization Circuit WIDEBAND INVERTING OPERATION Operating the OPA820 as an inverting amplifier has several benefits and is particularly useful when a matched 50Ω source and input impedance is required. Figure 2 shows the inverting gain of −1 circuit used as the basis of the inverting mode typical characteristics. 50Ω VO 50Ω Load OPA820 RG 402Ω RF 402Ω VI RM 57.6Ω 0.1µF Figure 1 shows the gain of +2 configuration used as the basis for most of the typical characteristics. Most of the curves were characterized using signal sources with 50Ω driving impedance and with measurement equipment presenting 50Ω load impedance. In Figure 1, the 50Ω shunt resistor at the VI terminal matches the source impedance of the test generator while the 50Ω series resistor at the VO terminal provides a matching resistor for the measurement equipment load. Generally, data sheet specifications refer to the voltage swings at the output pin (VO in Figure 1). The 100Ω load, combined with the 804Ω total feedback network load, presents the OPA820 with an effective load of approximately 90Ω in Figure 1. 2.2µF + Proper PC board layout and careful component selection will maximize the performance of the OPA820 in all applications, as discussed in the following sections of this data sheet. + The combination of speed and dynamic range offered by the OPA820 is easily achieved in a wide variety of application circuits, providing that simple principles of good design practice are observed. For example, good power-supply decoupling, as shown in Figure 1, is essential to achieve the lowest possible harmonic distortion and smooth frequency response. 2.2µF −5V Figure 2. Inverting G = −1 Specifications and Test Circuit In the inverting case, just the feedback resistor appears as part of the total output load in parallel with the actual load. For the 100Ω load used in the typical characteristics, this gives a total load of 80Ω in this inverting configuration. The gain resistor is set to get the desired gain (in this case 402Ω for a gain of −1) while an additional input matching resistor (RM) can be used to set the total input impedance equal to the source if desired. In this case, RM = 57.6Ω in parallel with the 402Ω gain setting resistor gives a matched input impedance of 50Ω. This matching is only needed when the input needs to be matched to a source impedance, as in the characterization testing done using the circuit of Figure 2. The OPA820 offers extremely good DC accuracy as well as low noise and distortion. To take full advantage of that DC precision, the total DC impedance looking out of each of the input nodes must be matched to get bias current cancellation. For the circuit of Figure 2, this requires the 205Ω resistor shown to ground on the noninverting input. The calculation for this resistor includes a DC-coupled 50Ω source impedance along with RG and RM. Although this resistor will provide cancellation for the bias current, it must be well decoupled (0.01µF in Figure 2) to filter the noise contribution of the resistor and the input current noise. As the required RG resistor approaches 50Ω at higher gains, the bandwidth for the circuit in Figure 2 will far exceed the bandwidth at that same gain magnitude for the noninverting circuit of Figure 1. This occurs due to the lower noise gain for the circuit of Figure 2 when the 50Ω source impedance is included in the analysis. For instance, at a signal gain of −10 (RG = 50Ω, RM = open, RF = 499Ω) the noise gain for the circuit of Figure 2 will be 1 + 499Ω/(50Ω + 50Ω) = 6 as a result of adding the 50Ω source in the noise gain equation. This gives considerable higher bandwidth than the noninverting gain of +10. Using the 240MHz gain bandwidth product for the OPA820, an inverting gain of −10 from a 50Ω source to a 50Ω RG gives 55MHz bandwidth, whereas the noninverting gain of +10 gives 30MHz. 13 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 WIDEBAND SINGLE-SUPPLY OPERATION Figure 4 shows the AC-coupled, single +5V supply, gain of −1V/V circuit configuration used as a basis for the +5V only Typical Characteristic curves. In this case, the midpoint DC bias on the noninverting input is also decoupled with an additional 0.01µF decoupling capacitor. This reduces the source impedance at higher frequencies for the noninverting input bias current noise. This 2.5V bias on the noninverting input pin appears on the inverting input pin and, since RG is DC blocked by the input capacitor, will also appear at the output pin. Figure 3 shows the AC-coupled, single +5V supply, gain of +2V/V circuit configuration used as a basis for the +5V only Electrical and Typical Characteristics. The key requirement for single-supply operation is to maintain input and output signal swings within the useable voltage ranges at both the input and the output. The circuit of Figure 3 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 806Ω resistors) to the noninverting input. The input signal is then AC-coupled into this midpoint voltage bias. The input voltage can swing to within 0.9V of the negative supply and 0.5V of the positive supply, giving a 3.6VPP input signal range. The input impedance matching resistor (57.6Ω) used in Figure 3 is adjusted to give a 50Ω input match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1. This puts the input DC bias voltage (2.5V) on the output as well. On a single +5V supply, the output voltage can swing to within 1.3V of either supply pin while delivering more than 80mA output current giving 2.4V output swing into 100Ω (5.6dBm maximum at the matched load). The single-supply test circuits of Figure 3 and Figure 4 show +5V operation. These same circuits can be used over a singlesupply range of +5V to +12V. Operating on a single +12V supply, with the Absolute Maximum Supply voltage specification of +13V, gives adequate design margin for the typical ±5% supply tolerance. +5V +VS + 0.1µF 50Ω Source 0.01µF 6.8µF 806Ω DIS VI 57.6Ω VO OPA820 806Ω 100Ω VS/2 RF 402Ω RG 402Ω 0.01µF Figure 3. AC-Coupled, G = +2V/V, Single-Supply Specifications and Test Circuit +5V +VS + 0.1µF 6.8µF 806Ω DIS 0.01µF 806Ω RG 0.01µF 402Ω OPA820 VO 100Ω VS/2 RF 402Ω VI Figure 4. AC-Coupled, G = −1V/V, Single-Supply Specifications and Test Circuit 14 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 BUFFERING HIGH-PERFORMANCE ADCs To achieve full performance from a high dynamic range ADC, considerable care must be exercised in the design of the input amplifier interface circuit. The example circuit on the front page shows a typical AC-coupled interface to a very high dynamic range converter. This AC-coupled example allows the OPA820 to be operated using a signal range that swings symmetrically around ground (0V). The 2VPP swing is then level-shifted through the blocking capacitor to a midscale reference level, which is created by a well-decoupled resistive divider off the converter’s internal reference voltages. To have a negligible effect (1dB) on the rated spurious-free dynamic range (SFDR) of the converter, the amplifier’s SFDR should be at least 18dB greater than the converter. The OPA820 has minimal effect on the rated distortion of the ADS850, given its 79dB SFDR at 2VPP, 1MHz. The > 90dB (< 1MHz) SFDR for the OPA820 in this configuration implies a < 3dB degradation (for the system) from the converter’s specification. For further SFDR improvement with the OPA820, a differential configuration is suggested. Successful application of the OPA820 for ADC driving requires careful selection of the series resistor at the amplifier output, along with the additional shunt capacitor at the ADC input. To some extent, selection of this RC network will be determined empirically for each converter. Many highperformance CMOS ADCs, such as the ADS850, perform better with the shunt capacitor at the input pin. This capacitor provides low source impedance for the transient currents produced by the sampling process. Improved SFDR is often obtained by adding this external capacitor, whose value is often recommended in this converter data sheet. The external capacitor, in combination with the built-in capacitance of the ADC input, presents a significant capacitive load to the OPA820. Without a series isolation resistor, an undesirable peaking or loss of stability in the amplifier may result. 335Ω Since the DC bias current of the CMOS ADC input is negligible, the resistor has no effect on overall gain or offset accuracy. Refer to the typical characteristic RS vs Capacitive Load to obtain a good starting value for the series resistor. This will ensure flat frequency response to the ADC input. Increasing the external capacitor value will allow the series resistor to be reduced. Intentionally bandlimiting using this RC network can also be used to limit noise at the converter input. VIDEO LINE DRIVING Most video distribution systems are designed with 75Ω series resistors to drive a matched 75Ω cable. In order to deliver a net gain of 1 to the 75Ω matched load, the amplifier is typically set up for a voltage gain of +2, compensating for the 6dB attenuation of the voltage divider formed by the series and shunt 75Ω resistors at either end of the cable. The circuit of Figure 1 applies to this requirement if all references to 50Ω resistors are replaced by 75Ω values. Often, the amplifier gain is further increased to 2.2, which recovers the additional DC loss of a typical long cable run. This change would require the gain resistor (RG) in Figure 1 to be reduced from 402Ω to 335Ω. In either case, both the gain flatness and the differential gain/phase performance of the OPA820 will provide exceptional results in video distribution applications. Differential gain and phase measure the change in overall small-signal gain and phase for the color sub-carrier frequency (3.58MHz in NTSC systems) versus changes in the large-signal output level (which represents luminance information in a composite video signal). The OPA820, with the typical 150Ω load of a single matched video cable, shows less than 0.01%/0.01° differential gain/phase errors over the standard luminance range for a positive video (negative sync) signal. Similar performance would be observed for multiple video signals, as shown in Figure 5. 402Ω 75Ω Transmission Line 75Ω VOUT OPA820 Video Input 75Ω 75Ω 75Ω VOUT 75Ω 75Ω VOUT High output current drive capability allows three back−terminated 75Ωtransmission lines to be simultaneously driven. 75Ω Figure 5. Video Distribution Amplifier 15 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 SINGLE OP AMP DIFFERENTIAL AMPLIFIER The voltage-feedback architecture of the OPA820, with its high common-mode rejection ratio (CMRR), will provide exceptional performance in differential amplifier configurations. Figure 6 shows a typical configuration. The starting point for this design is the selection of the RF value in the range of 200Ω to 2kΩ. Lower values reduce the required RG, increasing the load on the V2 source and on the OPA820 output. Higher values increase output noise as well as the effects of parasitic board and device capacitances. Following the selection of RF, RG must be set to achieve the desired inverting gain for V2. Remember that the bandwidth will be set approximately by the gain bandwidth product (GBP) divided by the noise gain (1 + RF/RG). For accurate differential operation (that is, good CMRR), the ratio R2/R1 must be set equal to RF/RG. This approach saves board space, cost, and power compared to using two additional OPA820 devices, and still achieves very good noise and distortion performance as a result of the moderate loading on the input amplifiers. +5V V1 OPA2822 R F1 500Ω RG 500Ω Power−supply decoupling not shown. +5V 500Ω OPA820 R F1 500Ω 500Ω VO −5V 500Ω 500Ω +5V OPA2822 Power−supply decoupling not shown. R1 V1 50Ω R2 OPA820 RG RF V2 VO = when RF (V − V2) RG 1 R2 RF = R1 RG −5V Figure 6. High-Speed, Single Differential Amplifier Usually, it is best to set the absolute values of R2 and R1 equal to RF and RG, respectively; this equalizes the divider resistances and cancels the effect of input bias currents. However, it is sometimes useful to scale the values of R2 and R1 in order to adjust the loading on the driving source, V1. In most cases, the achievable low-frequency CMRR will be limited by the accuracy of the resistor values. The 85dB CMRR of the OPA820 itself will not determine the overall circuit CMRR unless the resistor ratios are matched to better than 0.003%. If it is necessary to trim the CMRR, then R2 is the suggested adjustment point. THREE OP AMP DIFFERENCING (Instrumentation Topology) The primary drawback of the single op amp differential amplifier is its relatively low input impedances. Where high impedance is required at the differential input, a standard instrumentation amplifier (INA) topology may be built using the OPA820 as the differencing stage. Figure 7 shows an example of this, in which the two input amplifiers are packaged together as a dual voltage-feedback op amp, the OPA2822. 16 V2 − 5V Figure 7. Wideband 3-Op Amp Differencing Amplifier In this circuit, the common-mode gain to the output is always 1, because of the four matched 500Ω resistors, whereas the differential gain is set by (1 + 2RF1/RG), which is equal to 2 using the values in Figure 7. The differential to single-ended conversion is still performed by the OPA820 output stage. The high-impedance inputs allow the V1 and V2 sources to be terminated or impedance-matched as required. If the V1 and V2 inputs are already truly differential, such as the output from a signal transformer, then a single matching termination resistor may be used between them. Remember, however, that a defined DC signal path must always exist for the V1 and V2 inputs; for the transformer case, a center-tapped secondary connected to ground would provide an optimum DC operating point. DAC TRANSIMPEDANCE AMPLIFIER High-frequency Digital-to-Analog Converters (DACs) require a low-distortion output amplifier to retain their SFDR performance into real-world loads. See Figure 8 for a single-ended output drive implementation. In this circuit, only one side of the complementary output drive signal is used. The diagram shows the signal output current connected into the virtual ground-summing junction of the OPA820, which is set up as a transimpedance stage or I-V converter. The unused current output of the DAC is connected to ground. If the DAC requires its outputs to be terminated to a compliance voltage other than ground for operation, then the appropriate voltage level may be applied to the noninverting input of the OPA820. "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 C1 150pF VO = ID RF OPA820 +5V High−Speed DAC R1 124Ω RF R2 505Ω V1 C2 100pF CF CD ID VO OPA820 RF 402Ω GBP →Gain Bandwidth Product (Hz) for the OPA820. Power−supply decoupling not shown. −5V RG 402Ω ID Figure 9. 5MHz Butterworth Low-Pass Active Filter Figure 8. Wideband, Low-Distortion DAC Transimpedance Amplifier Another type of filter, a high-Q bandpass filter, is shown in Figure 10. The transfer function for this filter is: The DC gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance (CD) will produce a zero in the noise gain for the OPA820 that may cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise-gain peaking. To achieve a flat transimpedance frequency response, this pole in the feedback network should be set to: 1 + 2pR FCF GBP Ǹ4pR C F D GBP Ǹ2pR C F (3) R3 R 2R 4R 5C 1C 2 (4) 1 1 with w O2 + and wO + 1 Q R 1C 1 (1) which will give a corner frequency f−3dB of approximately: f *3dB + R )R s R 3R C4 V OUT 1 4 1 + 1 V IN s2 ) s R C ) R (2) ACTIVE FILTERS Most active filter topologies will have exceptional performance using the broad bandwidth and unity-gain stability of the OPA820. Topologies employing capacitive feedback require a unity-gain stable, voltage-feedback op amp. Sallen-Key filters simply use the op amp as a noninverting gain stage inside an RC network. Either current- or voltage-feedback op amps may be used in Sallen-Key implementations. Figure 9 shows an example Sallen-Key low-pass filter, in which the OPA820 is set up to deliver a low-frequency gain of +2. The filter component values have been selected to achieve a maximally-flat Butterworth response with a 5MHz, −3dB bandwidth. The resistor values have been slightly adjusted to compensate for the effects of the 240MHz bandwidth provided by the OPA820 in this configuration. This filter may be combined with the ADC driver suggestions to provide moderate (2-pole) Nyquist filtering, limiting noise, and out-of-band harmonics into the input of an ADC. This filter will deliver the exceptionally low harmonic distortion required by high SFDR ADCs such as the ADS850 (14-bit, 10MSPS, 82dB SFDR). (5) For the values chosen in Figure 10: fO + D R3 R 2 4R 5C 1C 2 and wO ] 1MHz 2p (6) Q = 100 See Figure 11 for the frequency response of the filter shown in Figure 10. R3 500Ω OPA820 C2 1000pF R1 15.8kΩ R2 158Ω R4 500Ω R5 158Ω OPA820 VOUT VIN C1 1000pF Figure 10. High-Q 1MHz Bandpass Filter 17 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 Gain (dB) OPERATING SUGGESTIONS OPTIMIZING RESISTOR VALUES 6 0 −6 −12 −18 −24 −30 −36 −42 −48 −54 −60 −66 −72 100k 1M 10M 100M Frequency (Hz) Figure 11. High-Q 1MHz Bandpass Filter Frequency Response DESIGN-IN TOOLS DEMONSTRATION BOARDS Two PC boards are available to assist in the initial evaluation of circuit performance using the OPA820 in its two package styles. Both of these are available, free, as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown in the table below. LITERATURE REQUEST NUMBER PRODUCT PACKAGE BOARD PART NUMBER OPA820ID SO-8 DEM-OPA68xU SBOU010 OPA820IDBV SOT23-5 DEM-OPA6xxN SBOU009 Go to the TI web site (www.ti.com) to request evaluation boards in the OPA820 product folder. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often a quick way to analyze the performance of the OPA820 and its circuit designs. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can play a major role on circuit performance. A SPICE model for the OPA820 is available through the TI web page (www.ti.com). The applications department is also available for design assistance. These models predict typical small-signal AC, transient steps, DC performance, and noise under a wide variety of operating conditions. The models include the noise terms found in the electrical specifications of the data sheet. These models do not attempt to distinguish between the package types in their small-signal AC performance. 18 Since the OPA820 is a unity-gain stable, voltage-feedback op amp, a wide range of resistor values may be used for the feedback and gain-setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. Usually, the feedback resistor value should be between 200Ω and 1kΩ. Below 200Ω, the feedback network will present additional output loading which can degrade the harmonic distortion performance of the OPA820. Above 1kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional band limiting in the amplifier response. A direct short is suggested as a feedback for AV = +1V/V. A good rule of thumb is to target the parallel combination of RF and RG (see Figure 1) to be less than about 200Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network, and thus a zero in the forward response. Assuming a 2pF total parasitic on the inverting node, holding RF || RG < 200Ω will keep this pole above 400MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest. In the inverting configuration, an additional design consideration must be noted. RG becomes the input resistor and therefore the load impedance to the driving source. If impedance matching is desired, RG may be set equal to the required termination value. However, at low inverting gains, the resulting feedback resistor value can present a significant load to the amplifier output. For example, an inverting gain of 2 with a 50Ω input matching resistor (= RG) would require a 100Ω feedback resistor, which would contribute to output loading in parallel with the external load. In such a case, it would be preferable to increase both the RF and RG values, and then achieve the input matching impedance with a third resistor to ground (see Figure 2). The total input impedance becomes the parallel combination of RG and the additional shunt resistor. BANDWIDTH vs GAIN Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the GBP shown in the specifications. Ideally, dividing GBP by the noninverting signal gain (also called the noise gain, or NG) will predict the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high-gain configurations. At low signal gains, most amplifiers will exhibit a more complex response with lower phase margin. The OPA820 is optimized to give a maximally-flat, 2nd-order Butterworth response in a gain of 2. In this configuration, the OPA820 has approximately 64° of phase margin and will show a typical −3dB bandwidth of 240MHz. When the phase margin is 64°, the closed-loop bandwidth is approximately √2 greater than the value predicted by dividing GBP by the noise gain. "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +10, the 30MHz bandwidth shown in the Electrical Characteristics agrees with that predicted using the simple formula and the typical GBP of 280MHz. OUTPUT DRIVE CAPABILITY The OPA820 has been optimized to drive the demanding load of a doubly-terminated transmission line. When a 50Ω line is driven, a series 50Ω into the cable and a terminating 50Ω load at the end of the cable are used. Under these conditions, the cable impedance will appear resistive over a wide frequency range, and the total effective load on the OPA820 is 100Ω in parallel with the resistance of the feedback network. The electrical characteristics show a ±3.6V swing into this load—which will then be reduced to a ±1.8V swing at the termination resistor. The ±75mA output drive over temperature provides adequate current drive margin for this load. Higher voltage swings (and lower distortion) are achievable when driving higher impedance loads. A single video load typically appears as a 150Ω load (using standard 75Ω cables) to the driving amplifier. The OPA820 provides adequate voltage and current drive to support up to three parallel video loads (50Ω total load) for an NTSC signal. With only one load, the OPA820 achieves an exceptionally low 0.01%/0.03° dG/dP error. DRIVING CAPACITIVE LOADS One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. A high-speed, high open-loop gain amplifier like the OPA820 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. In simple terms, the capacitive load reacts with the open-loop output resistance of the amplifier to introduce an additional pole into the loop and thereby decrease the phase margin. This issue has become a popular topic of application notes and articles, and several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS vs Capacitive Load and the resulting frequency response at the load. The criterion for setting the recommended resistor is maximum bandwidth, flat frequency response at the load. Since there is now a passive low-pass filter between the output pin and the load capacitance, the response at the output pin itself is typically somewhat peaked, and becomes flat after the roll-off action of the RC network. This is not a concern in most applications, but can cause clipping if the desired signal swing at the load is very close to the amplifier’s swing limit. Such clipping would be most likely to occur in pulse response applications where the frequency peaking is manifested as an overshoot in the step response. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA820. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA820 output pin (see the Board Layout section). DISTORTION PERFORMANCE The OPA820 is capable of delivering an exceptionally low distortion signal at high frequencies and low gains. The distortion plots in the Typical Characteristics show the typical distortion under a wide variety of conditions. Most of these plots are limited to 100dB dynamic range. The OPA820 distortion does not rise above −90dBc until either the signal level exceeds 0.9V and/or the fundamental frequency exceeds 500kHz. Distortion in the audio band is ≤ −100dBc. Generally, until the fundamental signal reaches very high frequencies or powers, the 2nd-harmonic will dominate the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration this is the sum of RF + RG, whereas in the inverting configuration this is just RF (see Figure 1). Increasing the output voltage swing increases harmonic distortion directly. Increasing the signal gain will also increase the 2nd-harmonic distortion. Again, a 6dB increase in gain will increase the 2nd- and 3rd-harmonic by 6dB even with a constant output power and frequency. Finally, the distortion increases as the fundamental frequency increases because of the roll-off in the loop gain with frequency. Conversely, the distortion will improve going to lower frequencies down to the dominant open-loop pole at approximately 100kHz. Starting from the −85dBc 2nd-harmonic for 2VPP into 200Ω, G = +2 distortion at 1MHz (from the Typical Characteristics), the 2nd-harmonic distortion will not show any improvement below 100kHz and will then be: −100dB − 20log (1MHz/100kHz) = −105dBc 19 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 NOISE PERFORMANCE The OPA820 complements its low harmonic distortion with low input noise terms. Both the input-referred voltage noise and the two input-referred current noise terms combine to give a low output noise under a wide variety of operating conditions. Figure 12 shows the op amp noise analysis model with all the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. ENI EO OPA820 RS IBN (9µA typ into the pins) but with a very close match between the two input currents—typically 100nA input offset current. The total output offset voltage may be considerably reduced by matching the source impedances looking out of the two inputs. For example, one way to add bias current cancellation to the circuit of Figure 1 would be to insert a 175Ω series resistor into the noninverting input from the 50Ω terminating resistor. When the 50Ω source resistor is DC-coupled, this will increase the source impedance for the noninverting input bias current to 200Ω. Since this is now equal to the impedance looking out of the inverting input (RF || RG), the circuit will cancel the gains for the bias currents to the output leaving only the offset current times the feedback resistor as a residual DC error term at the output. Using a 402Ω feedback resistor, this output error will now be less than ±0.4µA × 402Ω = ±160µV at 25°C. THERMAL ANALYSIS The OPA820 will not require heatsinking or airflow in most applications. Maximum desired junction temperature would set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed +150°C. ERS RF √4kTRS 4kT RG √4kTRF I BI RG 4kT = 1.6E − 20J at 290_ K Figure 12. Op Amp Noise Analysis Model The total output spot noise voltage is computed as the square root of the squared contributing terms to the output noise voltage. This computation is adding all the contributing noise powers at the output by superposition, then taking the square root to get back to a spot noise voltage. Equation 3 shows the general form for this output noise voltage using the terms presented in Figure 12. EO + Ǹƪ ƫ Note that it is the power in the output stage and not in the load that determines internal power dissipation. E2NI ) ǒI BNR SǓ ) 4kTR S NG 2 ) ǒI BIR FǓ ) 4kTR FNG 2 2 (7) Dividing this expression by the noise gain (NG = 1 + RF/RG) will give the equivalent input referred spot noise voltage at the noninverting input, as shown in Equation 4. EN + Ǹ E2NI ) ǒIBNRSǓ ) 4kTR S ) 2 ǒ Ǔ IBIRF NG As a worst-case example, compute the maximum TJ using an OPA820IDBV (SOT23-5 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C. PD = 10V(6.4mA) + 52/(4 × (100Ω || 800Ω)) = 134mW 2 ) 4kTR F NG Maximum TJ = +85°C + (134mW × 150°C/W) = 105°C (8) Evaluating these two equations for the OPA820 circuit presented in Figure 1 will give a total output spot noise voltage of 6.44nV/√Hz and an equivalent input spot noise voltage of 3.22nV/√Hz. DC OFFSET CONTROL The OPA820 can provide excellent DC signal accuracy because of its high open-loop gain, high common-mode rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full advantage of this low input offset voltage, careful attention to input bias current cancellation is also required. The high-speed input stage for the OPA820 has a moderately high input bias current 20 Operating junction temperature (TJ) is given by TA + PD × qJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this worst-case condition, PDL = VS2/(4 × RL), where RL includes feedback network loading. BOARD LAYOUT Achieving optimum performance with a high-frequency amplifier such as the OPA820 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 b) Minimize the distance (< 0.25”) from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA820. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ, this parasitic capacitance can add a pole and/or a zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load-driving considerations. It has been suggested here that a good starting point for design would be to set RG || RF = 200Ω. Using this setting will automatically keep the resistor noise terms low, and minimize the effect of their parasitic capacitance. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA820 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary onboard, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA820 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and input impedance of the destination device; this total effective impedance should be set to match the trace impedance. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA820 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA820 onto the board. 21 "#$ www.ti.com SBOS303A − JUNE 2004 − REVISED JULY 2004 INPUT AND ESD PROTECTION The OPA820 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 13. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the OPA820), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. Figure 14 shows an example protection circuit for I/O voltages that may exceed the supplies. +VCC +5V 50Ω Source External Pin Power−supply decoupling not shown. 174Ω V1 50Ω 50Ω D1 D2 OPA820 VO −VCC Figure 13. Internal ESD Protection RF 301Ω 50Ω RG 301Ω −5V D1 = D2 IN5911 (or equivalent) Figure 14. Gain of +2 with Input Protection 22 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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