OPA2652 ® OPA 265 2 For most current data sheet and other product information, visit www.burr-brown.com Dual, 700MHz, Voltage-Feedback OPERATIONAL AMPLIFIER TM FEATURES DESCRIPTION ● WIDEBAND BUFFER: 700MHz, G = +1 The OPA2652 is a dual, low-cost, wideband voltagefeedback amplifier intended for price sensitive applications. It features a high gain bandwidth product of 200MHz on only 5.5mA/chan quiescent current. Intended for operation on ±5V supplies, it will also support applications on a single supply from +6V to +12V with 140mA output current. Its classical differential input, voltage-feedback design allows wide application in active filters, integrators, transimpedance amplifiers, and differential receivers. ● WIDEBAND LINE DRIVER: 200MHz, G = +2 ● HIGH OUTPUT CURRENT: 140mA ● LOW SUPPLY CURRENT: 5.5mA/Ch ● ULTRA-SMALL PACKAGE: SOT23-8 ● LOW dG/dφ : 0.05%/0.03° ● HIGH SLEW RATE: 335V/µsec ● SUPPLY VOLTAGE: ±3V to ±6V The OPA2652 is internally compensated for unity gain stability. It has exceptional bandwidth (700MHz) as a unity gain buffer, with little peaking (0dB typically). Excellent DC accuracy is achieved with a low 1.5mV input offset voltage and 300nA input offset current. APPLICATIONS ● A/D DRIVERS ● CONSUMER VIDEO ● ACTIVE FILTERS ● PULSE DELAY CIRCUITS ● LOW COST UPGRADE TO THE AD8056 OR EL2210 200Ω 402Ω RELATED PRODUCTS SINGLES DUALS TRIPLES QUADS NOTES OPA650 OPA2650 — OPA4650 ±5V Spec OPA680 OPA2680 OPA3680 — +5V Capable OPA631 OPA2631 — — +3V Capable OPA634 OPA2634 — — +3V Capable 24.9Ω 0.1µF +5V – 22pF +5V 1.00kΩ 1/2 OPA2652 +In 0.1µF VIN CM 133Ω –In ADS807 12-Bit 53MHz 1.00kΩ 200Ω 402Ω 24.9Ω 0.1µF + 22pF 1/2 OPA2652 133Ω –5V Differential ADC Driver International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 2000 Burr-Brown Corporation PDS-1588B Printed in U.S.A. June, 2000 SPECIFICATIONS: VS = ±5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figures 1 and 2 for AC performance only. OPA2652U, E TYP PARAMETER AC PERFORMANCE Small-Signal Bandwidth Gain Bandwidth Product Bandwidth for 0.1dB Flatness Peaking at a Gain of +1 Slew Rate Rise/Fall Time Large Signal Bandwidth SFDR Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Channel-to-Channel Crosstalk DC PERFORMANCE(4) Open-Loop Voltage Gain Input Offset Voltage Average Offset Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT(4) Common-Mode Input Range Common-Mode Rejection Ratio Input Impedance Differential Common Mode OUTPUT Voltage Output Swing Output Current, Sourcing Output Current, Sinking Closed-Loop Output Impedance CONDITIONS +25°C (Figures 1 and 2) G = +1, RF = 25Ω, VO = 200mVp-p G = +2, VO = 200mVp-p G = +5, VO = 200mVp-p G ≥ +10 VO = 200mVp-p G = +1, RF = 25Ω,VO = 200mVp-p 4V Step 200mV Step 4V Step VO = 4Vp-p VO = 2Vp-p, 5MHz f > 1MHz f > 1MHz NTSC, RL = 150Ω NTSC, RL = 150Ω f = 5MHz 700 200 45 200 50 0 335 2.0 10 50 66 8 1.4 0.05 0.03 –100 GUARANTEED +25°C(2) 0°C to 70°C(3) –40°C to +85°C(3) UNITS MIN/ MAX TEST LEVEL(1) MHz MHz MHz MHz MHz dB V/µs ns ns MHz dB nV/√Hz pA/√Hz % degrees dBc typ typ typ typ typ typ typ typ typ typ typ typ typ typ typ typ C C C C C C C C C C C C C C C C dB mV µV/°C µA µA/°C µA µA/°C min max max max max max max A A B A B A B V dB min min A A kΩ || pF MΩ || pF typ typ C C V V mA mA Ω min min min min typ A A A A C V V mA mA dB typ max max min min C A A A A VCM = 0V 63 ±1.5 56 ±7 55 54 4 15 5 20 7 25 ±0.3 ±1.0 ±1.4 ±2.0 ±4.0 95 ±3.0 75 ±2.8 ±2.7 VCM = 0V 35 || 1 18 || 1 ±3.0 ±2.5 140 140 0.06 1kΩ Load 100Ω Load VO = 0V VO = 0V f < 100kHz ±2.4 ±2.2 100 100 85 85 75 75 ±6 14 8 ±6 15.5 7.5 POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power Supply Rejection Ratio (–PSRR) THERMAL CHARACTERISTICS Specified Operating Temperature Range Thermal Resistance, θJA U SO-8 E SOT23-8 ±5 ±6 13.2 8.8 54 Total Both Channels Total Both Channels Input Referred 11 11 58 U, E Package Junction-to-Ambient –40 to +85 °C typ C 125 150 °C/W °C/W typ typ C C NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for 25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive-out-of node. VCM is the input common-mode voltage. ® OPA2652 2 ELECTROSTATIC DISCHARGE SENSITIVITY PIN CONFIGURATION Top View SO-8 SOT23-8 OPA2652 Out A 1 8 +VS –In A 2 7 Out B +In A 3 6 –In B –VS 4 5 +In B Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. SOT23-8 Marking / Pin Orientation ABSOLUTE MAXIMUM RATINGS Supply Voltage ................................................................................. ±6.5V Internal Power Dissipation ........................... See Thermal Characteristics Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range ......................................... –40°C to +125°C Lead Temperature (SO-8) ............................................................. +260°C Junction Temperature (TJ ) ........................................................... +175°C ESD Rating (Human Body Model) .................................................. 2000V (Machine Model) ........................................................... 200V C52 Pin 1 PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER OPA2652U SO-8 Surface Mount 182 –40°C to +85°C OPA2652U OPA2652U Rails " " " " OPA2652U/2K5 Tape and Reel SOT23-8 Surface Mount 348 –40°C to +85°C C52 OPA2652E/250 Tape and Reel " " " " OPA2652E/3K Tape and Reel " OPA2652E " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /3K indicates 3000 devices per reel). Ordering 3000 pieces of “OPA2652U/3K” will get a single 3000-piece Tape and Reel. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA2652 TYPICAL PERFORMANCE CURVES: VS = ±5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figures 1 and 2. NON-INVERTING SMALL-SIGNAL FREQUENCY RESPONSE INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 6 6 –3 G = +2 –6 –9 G = +5 –12 –15 G = +10 –18 G = –1 0 –3 G = –2 –6 –9 –12 G = –5 –15 –18 –21 G = –10 –21 –24 –24 1M 10M 100M 1G 1M 10M 100M 1G Frequency (Hz) Frequency (Hz) NON-INVERTING LARGE-SIGNAL FREQUENCY RESPONSE INVERTING LARGE-SIGNAL FREQUENCY RESPONSE 6 6 G = +2 3 G = –1 3 Normalized Gain (dB) VO ≤ 1Vp-p 0 –3 –6 –9 VO = 2Vp-p –12 –15 VO = 4Vp-p –18 VO = 0.5Vp-p 0 –3 –6 VO = 1.0Vp-p –9 –12 –15 VO = 2.0Vp-p –18 –21 –21 –24 –24 10M 100M 1M 1G 10M 100M Frequency (Hz) Frequency (Hz) NON-INVERTING PULSE RESPONSE INVERTING PULSE RESPONSE G = –1 Output Voltage (50mV/div) 200mVp-p Output Voltage (800mV/div) G = +2 4Vp-p Time (5ns/div) 4Vp-p 200mVp-p Time (5ns/div) ® OPA2652 1G 4 Output Voltage (50mV/div) 1M Output Voltage (800mV/div) Normalized Gain (dB) VO = 0.2Vp-p 3 0 Normalized Gain (dB) Normalized Gain (dB) G = +1 RF = 25Ω VO = 0.2Vp-p 3 TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figures 1 and 2. HARMONIC DISTORTION vs NON-INVERTING GAIN HARMONIC DISTORTION vs INVERTING GAIN –50 –50 VO = 2Vp-p f = 5MHz 3rd Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) VO = 2Vp-p f = 5MHz –60 2nd Harmonic –70 –80 –90 –60 2nd Harmonic –70 –80 –90 1 10 1 10 Gain Magnitude (V/V) Gain Magnitude (V/V) HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE –50 –50 VO = 2Vp-p Harmonic Distortion (dBc) Harmonic Distortion (dBc) f = 5MHz –60 3rd Harmonic –70 2nd Harmonic –80 –60 3rd Harmonic –70 –80 2nd Harmonic –90 –90 0.1 1 0.1 4 1 10 20 Frequency (MHz) Output Voltage (Vp-p) HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs SUPPLY VOLTAGE –50 –50 VO = 2Vp-p f = 5MHz VO = 2Vp-p f = 5MHz Harmonic Distortion (dBc) Harmonic Distortion (dBc) 3rd Harmonic –60 3rd Harmonic –70 2nd Harmonic –80 –90 –60 3rd Harmonic –70 2nd Harmonic –80 –90 100 ±3 1000 RL (Ω) ±4 ±5 ±6 Supply Voltage (V) ® 5 OPA2652 TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figures 1 and 2. TWO-TONE, 3rd-ORDER SPURIOUS LEVEL COMPOSITE VIDEO dG/dφ 0.30 dφ, Positive Video 0.25 –60 20MHz dG/dφ (%/°) 3rd-Order Spurious Level (dBc) –50 10MHz –70 5MHz 2MHz 0.20 dφ, Negative Video 0.15 0.10 –80 1MHz dG, Positive Video 0.05 Load Power at matched 50Ω load –90 dG, Negative Video 0.00 –8 –6 –4 –2 0 2 4 1 2 Single-Tone Load Power (dBm) INPUT VOLTAGE AND CURRENT NOISE DENSITY –30 Crosstalk, Input-Referred (dB) Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) 4 CHANNEL-TO-CHANNEL CROSSTALK 100 Voltage Noise = 8.0nV/√Hz 10 Current Noise = 1.4pA/√Hz 1 –40 –50 –60 –70 –80 –90 100 1k 10k 100k 1M 10M 10 100 Frequency (Hz) RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD Normalized Gain to Capacitive Load (dB) 60 50 40 30 20 10 0 1 10 100 2 G = +2 1 CL = 10pF 0 CL = 22pF –1 CL = 100pF –2 –3 –4 1/2 OPA2652 –5 RS VO CL = 47pF CL –6 1kΩ –7 –8 0 1000 10M 100M Frequency (Hz) Capacitive Load (pF) ® OPA2652 1000 Frequency (MHz) 70 RS (Ω) 3 Number of 150Ω Loads 6 1G TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figures 1 and 2. CMRR AND PSRR vs FREQUENCY OPEN-LOOP GAIN AND PHASE 90 70 60 CMRR Open-Loop Gain (dB) 80 +PSRR 70 –PSRR 60 0 50 40 30 –30 Open-Loop Phase 50 –60 40 –90 30 –120 20 –150 Open-Loop Gain 10 –180 Open-Loop Phase (°) Power Supply Rejection Ratio (dB) Common-Mode Rejection Ratio (dB) 100 20 0 10 –210 –10 0 1k 10k 100k 1M 10M 100M –240 10k 100k 1M Frequency (Hz) 10M 100M 1G Frequency (Hz) CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY OUTPUT VOLTAGE AND CURRENT LIMITATIONS 100 5 200Ω 4 Output Impedance (Ω) 1/2 OPA2652 10 3 ZO 2 VO (V) 402Ω 402Ω 1 Output Current Limited 1W Internal Power Limit 1 100Ω Load Line 0 50Ω Load Line 20Ω Load Line 10Ω Load Line –1 –2 0.1 –3 Output Current Limit 1W Internal Power Limit –4 0.01 10k 100k 1M 10M –5 –200 100M 400M –150 –100 –50 Frequency (Hz) NON-INVERTING OVERDRIVE RECOVERY Output Voltage (V) 3 VIN G = +2 5 2.0 4 1.5 VOUT 2 1.0 1 0 0 Input and Output Voltage (V) 4 50 100 150 200 INVERTING OVERDRIVE RECOVERY 2.5 Input Voltage (V) 5 0 IO (mA) VIN 3 2 1 0 –1 0.50 –2 –0.5 –3 –1.0 –4 –2.0 –4 –5 –2.5 –5 Time (20ns/div) G = –1 –1 –2 VOUT –3 Time (20ns/div) ® 7 OPA2652 TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figures 1 and 2. SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 250 25 Sourcing Output Current 1 0 Output Current (mA) 200 IOS –1 –2 –3 VOS Sinking Output Current 150 15 100 10 Quiescent Supply Current (Both Channels) 50 IB –4 –5 20 –6 5 0 –40 –20 0 20 40 60 80 100 0 –40 –20 Ambient Temperature (°C) 0 20 6 Positive Common-Mode Input Range 5 Negative Common-Mode Input Range 4 3 2 Negative Output Voltage Range 1 Positive Output Voltage Range ±3 ±4 ±5 Supply Voltage (V) ® OPA2652 60 Ambient Temperature (°C) COMMON-MODE INPUT VOLTAGE RANGE AND OUTPUT SWING vs SUPPLY VOLTAGE 0 40 8 ±6 80 100 Supply Current (mA) 4 3 2 Voltage Range (V) Input Offset Voltage (mV) Input Bias and Offset Current (µA) TYPICAL DC DRIFT OVER TEMPERATURE 6 5 APPLICATIONS INFORMATION An additional resistor (174Ω) is included in series with the non-inverting input. Combined with the 25Ω DC source resistance looking back towards the signal generator, this gives an input bias current cancelling resistance that matches the 201Ω source resistance seen at the inverting input (see the DC Accuracy and Offset Control section). In addition to the usual power supply decoupling capacitors to ground, a 0.1µF capacitor is included between the two power supply pins. In practical PC board layouts, this optional-added capacitor will typically improve the 2nd harmonic distortion performance by 3dB to 6dB. WIDEBAND VOLTAGE FEEDBACK OPERATION The OPA2652 is a dual low power, wideband voltage feedback operational amplifier. Each channel is internally compensated to provide unity gain stability. The OPA2652’s voltage feedback architecture features true differential and fully symmetrical inputs. This minimizes offset errors, making the OPA2652 well suited for implementing filter and instrumentation designs. As a dual operational amplifier, OPA2652 is an ideal choice for designs requiring multiple channels where reduction of board space, power dissipation and cost are critical. Its AC performance is optimized to provide a gain bandwidth product of 200MHz and a fast rise time of 2.0ns, which is an important consideration in high speed data conversion applications. The low DC input offset of ±1.5mV and drift of ±5µV/°C support high accuracy requirements. In applications requiring a higher slew rate and wider bandwidth, such as video and high bit rate digital communications, consider the dual current feedback OPA2658, or OPA2681. Figure 2 shows the DC-coupled gain of –1, bipolar supply circuit configuration which is the basis of the Specifications and Typical Performance Curves at G = –1. The input impedance matching resistor (57.6Ω) used for testing gives a 50Ω input load. A resistor (205Ω) connects the non-inverting input to ground. This provides the DC source resistance matching to cancel outputs errors due to input bias current. Figure 1 shows the DC-coupled, gain of +2, dual power supply circuit configuration used as the basis of the ±5V Specifications and Typical Performance Curves. This is for one channel. The other channel is connected similarly. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins, while output powers (dBm) are at the matched 50Ω load. For the circuit of Figure 1, the total effective load will be 100Ω || 804Ω. Two optional components are included in Figure 1. +5V + 0.1µF 0.1µF RB 205Ω 50Ω +5V 0.1µF 6.8µF Source 6.8µF + RO VO 49.9Ω 1/2 OPA2652 50Ω Load RG 402Ω VO = –1 VI RF 402Ω VI RM 57.6Ω 0.1µF + 6.8µF 50Ω Source 174Ω VI 49.9Ω VO 1/2 OPA2652 0.1µF 49.9Ω –5V 50Ω Load FIGURE 2. DC-Coupled, G = –1, Bipolar Supply, Specification and Test Circuit. RF 402Ω DIFFERENTIAL ADC DRIVER RG 402Ω + 6.8µF The circuit on the front page shows an OPA2652 driving the ADS807 A/D converter differentially, at a gain of +2V/V. The outputs are AC-coupled to the converter to adjust for the difference in supply voltages. The 133Ω resistors at the noninverting inputs minimize DC offset errors. The differential topology minimizes even-order distortion products, such as second-harmonic distortion. 0.1µF –5V FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit. ® 9 OPA2652 BANDPASS FILTER VIDEO LINE DRIVER Figure 3 shows a single OPA2652 implementing a sixthorder bandpass filter. This filter cascades two second-order Sallen-Key sections with transmission zeros, and a double real pole section. It has 0.3dB of ripple, –3dB frequencies of 450kHz and 11MHz, and –23dB frequencies of 315kHz and 16MHz. The 20.0Ω resistor isolates the first OPA2652 output from capacitive loading. This improves stability with minimal impact on the filter response. Figure 4 shows the nominal response simulated by SPICE. Figure 5 shows the OPA2652 used as a video line driver. Its outstanding differential gain and phase allow it to be used in studio equipment, while its low cost and SOT23-8 package option will support consumer applications. +5V Video Input 75.0Ω 1/2 OPA2652 75.0Ω Video Output 0 –5V –5 402Ω 402Ω Gain (dB) –10 –15 –20 FIGURE 5. Video Line Driver. –25 PULSE DELAY CIRCUIT Figure 6 shows the OPA2652 used in a pulse delay circuit. This circuit cascades the two op amps in the OPA2652, each forming a single pole, active allpass filter. The overall gain is +1, and the overall delay through the filter is: –30 –35 –40 10k 100k 1M 10M 100M Frequency (Hz) tGD = n(2RC), overall group delay n= 2, the number of cascaded stages FIGURE 4. Nominal Filter Response. 2.2nF 1% Resistors 5% Capacitors +5V 140Ω VIN 2.10kΩ 1.30kΩ 1.0nF 1/2 OPA2652 1.0nF –5V 24.9Ω 143Ω 180pF +5V 200Ω 2.7nF VOUT 158Ω 12pF 150pF 1/2 OPA2652 18pF 100pF 225Ω 100Ω 20.0Ω –5V 24.9Ω 107Ω FIGURE 3. Bandpass Filter. ® OPA2652 10 +5V +5V C C VIN 1/2 OPA2652 R R –5V VO –5V RF 402Ω RG 402Ω 1/2 OPA2652 402Ω 402Ω FIGURE 6. Pulse Delay Circuit. MACROMODELS AND APPLICATIONS SUPPORT RF and RG need to be equal to maintain a constant gain magnitude. The rise and fall times of the input pulses (tr(IN) ) should be slow enough to prevent pre-shoot artifacts in the response. Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for Video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. Check the Burr-Brown web site (www.burr-brown.com) for available SPICE products (not all parts have models). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dφ characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance. tr (IN) ≥ 5RC, minimal pre-shoot SIMPLE BANDPASS FILTER Figure 7 shows the OPA2652 used as simple bandpass filter. The OPA2652 is well suited for this type of circuit because it is very stable at a noise gain of +1. C2 C1 402Ω 402Ω VIN OPERATING SUGGESTIONS VOUT OPTIMIZING RESISTOR VALUES +5V Since the OPA2652 is a unity gain stable voltage feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a non-inverting unity gain follower application, the feedback connection should be made with a 25Ω resistor, not a direct short. This will isolate the inverting input capacitance from the output pin and improve the frequency response flatness. Usually, the feedback resistor value should be between 200Ω and 1.5kΩ. Below 200Ω, the feedback network will present additional output loading which can degrade the harmonic distortion performance of the OPA2652. Above 1.5kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional band-limiting in the amplifier response. 1/2 OPA2652 402Ω –5V FIGURE 7. Inverting Bandpass Filter. DESIGN-IN TOOLS DEMONSTRATION BOARDS PC boards are available to assist in the initial evaluation of circuit performance using the OPA2652. They are available free as unpopulated PC boards delivered with descriptive documentation. The summary information for these boards is shown below: PRODUCT PACKAGE BOARD PART NUMBER OPA2652U OPA2652E 8-Lead SO-8 SOT23-8 DEM-OPA26xU DEM-OPA2652E ORDERING NUMBER MKT-352 MKT-365 A good rule of thumb is to target the parallel combination of RF and RG (Figure 1) to be less than approximately 300Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network, and thus a zero in the forward response. Assuming a 2pF total parasitic on the inverting node, holding RF || RG < 300Ω will keep this pole above 250MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest. Contact the Burr-Brown Applications support line to request this board. ® 11 OPA2652 BANDWIDTH VS GAIN: NON-INVERTING OPERATION tive driving impedance of 50Ω || 57.6Ω = 26.8Ω. This impedance is added in series with RG for calculating the noise gain (NG). The resultant NG is 1.94 for Figure 2, (an ideal 0Ω source would cause NG = 2.00). Voltage feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the specifications. Ideally, dividing GBP by the non-inverting signal gain (also called the Noise Gain, or NG) will predict the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high gain configurations. At low gains (increased feedback factor), most amplifiers will exhibit a wider bandwidth and lower phase margin. The OPA2652 is compensated to give a flat response in a non-inverting gain of 1 (Figure 1). This results in a typical gain of +1 bandwidth of 700MHz, far exceeding that predicted by dividing the 200MHz GBP by NG = 1. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +5, the 45MHz bandwidth shown in the Typical Specifications is close to that predicted using this simple formula. The third important consideration in inverting amplifier design is setting the bias current cancellation resistor on the non-inverting input (RB). If this resistor is set equal to the total DC resistance looking out of the inverting node, the output DC error, due to the input bias currents, will be reduced to (Input Offset Current) • RF. If the 50Ω source impedance is DC-coupled in Figure 2, the total resistance to ground on the inverting input will be 429Ω. Combining this in parallel with the feedback resistor gives 208Ω, which is close to the RB = 205Ω used in Figure 2. To reduce the additional high frequency noise introduced by this resistor, it is sometimes bypassed with a capacitor. As long as RB <300Ω, the capacitor is not required since its total noise contribution will be much less than that of the op amp’s input noise voltage. INVERTING AMPLIFIER OPERATION OUTPUT CURRENT AND VOLTAGE Since the OPA2652 is a general purpose, wideband voltage feedback op amp, all of the familiar op amp application circuits are available to the designer. Inverting operation is one of the more common requirements and offers several performance benefits. Figure 2 shows a typical inverting configuration. The OPA2652 specifications in the spec table, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage • current, or VI product, which is more relevant to circuit operation. Refer to the “Output Voltage and Current Limitations” plot in the Typical Performance Curves. The X and Y axes of this graph show the zero-voltage output current limit and the zerocurrent output voltage limit, respectively. The four quadrants give a more detailed view of the OPA2652’s output drive capabilities, noting that the graph is bounded by a “Safe Operating Area” of 1W maximum internal power dissipation (500mW for each channel). Superimposing resistor load lines onto the plot shows that the OPA2652 can drive ±2.2V into 50Ω or ±2.5V into 100Ω without exceeding the output capabilities, or the 1W dissipation boundary line. In the inverting configuration, three key design consideration must be noted. The first is that the gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PC board trace or other transmission line conductor), RG may be set equal to the required termination value and RF adjusted to give the desired gain. This is the simplest approach and results in optimum bandwidth and noise performance. However, at low inverting gains, the resultant feedback resistor value can present a significant load to the amplifier output. For an inverting gain of –1, setting RG to 50Ω for input matching eliminates the need for RM but requires a 50Ω feedback resistor. This has the interesting advantage that the noise gain becomes equal to 2 for a 50Ω source impedance—the same as the non-inverting circuits considered above. However, the amplifier output will now see the 50Ω feedback resistor in parallel with the external load. In general, the feedback resistor should be limited to the 200Ω to 1.5kΩ range. In this case, it is preferable to increase both the RF and RG values as shown in Figure 2, and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of RG and RM. To maintain maximum output stage linearity, no output short-circuit protection is provided. This will not normally be a problem since most applications include a series matching resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground. However, shorting the output pin directly to the adjacent positive power supply pin will, in most cases, destroy the amplifier. Including a small series resistor (5Ω) in the power supply line will protect against this. Always place the 0.1µF decoupling capacitor directly on the supply pins. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter—including additional external capacitance which may be recommended to improve A/D linearity. A high speed amplifier like the OPA2652 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and influences the bandwidth. For the example in Figure 2, the RM value combines in parallel with the external 50Ω source impedance, yielding an effec- ® OPA2652 12 placed directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 1 shows the general form for the output noise voltage using the terms shown in Figure 10. Equation 1: I R 2 4kTR F 2 E N = E NI 2 + ( I BN R S ) + 4kTR S + BI F + NG NG Dividing this expression by the noise gain (NG = 1+RF /RG ) will give the equivalent input-referred spot noise voltage at the non-inverting input, as shown in Equation 2. Equation 2: The Typical Performance Curves show the recommended RS versus capacitive load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA2652. Long PC board traces, unmatched cables, and connections to multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA2652 output pin (see Board Layout Guidelines). EO = (E NI 2 ) + ( I BN R S ) + 4kTR S NG 2 + ( I BI R F ) + 4kTR F NG 2 2 The OPA2652 provides good distortion performance into a 100Ω load on ±5V supplies. Increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network; in the non-inverting configuration (Figure 1) this is sum of RF + RG, while in the inverting configuration, it is just RF. Also, providing an additional supply decoupling capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). Evaluating these two equations for the OPA2652 circuit and component values shown in Figure 1 will give a total output spot noise voltage of 17nV/√Hz and a total equivalent input spot noise voltage of 8.4nV/√Hz. This is including the noise added by the bias current cancellation resistor (205Ω) on the non-inverting input. This total input-referred spot noise voltage is only slightly higher than the 8nV/√Hz specification for the op amp voltage noise alone. This will be the case as long as the impedances appearing at each op amp input are limited to the previously recommend maximum value of 300Ω. Keeping both (RF || RG) and the non-inverting input source impedance less than 300Ω will satisfy both noise and frequency response flatness considerations. Since the resistor-induced noise is relatively negligible, additional capacitive decoupling across the bias current cancellation resistor (RB) for the inverting op amp configuration of Figure 2 is not required. It is also true that increasing the output voltage swing increases harmonic distortion. DC ACCURACY AND OFFSET CONTROL DISTORTION PERFORMANCE The balanced input stage of a wideband voltage feedback op amp allows good output DC accuracy in a wide variety of applications. Although the high speed input stage does require relatively high input bias current (typically 4µA out of each input terminal), the close matching between them may be used to significantly reduce the output DC error caused by this current. This is done by matching the DC source resistances appearing at the two inputs. This reduces the output DC error due to the input bias currents to the offset current times the feedback resistor. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage and current specifications, gives a worst-case output offset voltage equal to: NOISE PERFORMANCE The OPA2652 input-referred voltage noise (8nV/√Hz), and the two input-referred current noise terms (1.4pA/√Hz), combine to give low output noise under a wide variety of operating conditions. Figure 8 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. ENI 1/2 OPA2652 RS EO ±(NG • VOS(MAX)) ± (RF • IOS(MAX)) = ±(1.94 • 7.0mV) ± (402Ω • 1.0µA) = ±14.0mV IBN ERS RF √ 4kTRS 4kT RG RG IBI (NG = non-inverting signal gain) √ 4kTRF A fine scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are available for introducing DC offset control into an op amp 4kT = 1.6x10–20J at 290°K FIGURE 8. Op Amp Noise Analysis Model. ® 13 OPA2652 circuit. Most of these techniques add a DC current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the non-inverting input may be considered. However, the DC offset voltage on the summing junction will set up a DC current back into the source which must be considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and frequency response flatness. For a DC-coupled inverting amplifier, Figure 9 shows one example of an offset adjustment technique that has minimal impact on the signal frequency response. In this case, the DC offset current is brought into the inverting input node through resistor values that are much larger than the signal path resistors. This will insure that the adjustment circuit has minimal effect on the loop gain and hence the frequency response. Note that it is the power in the output stage, and not into the load, that determines internal power dissipation. As an example, compute the maximum TJ using an OPA2652E (SOT23-8 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and with both outputs driving 2.5VDC into a grounded 100Ω load. PD = 10V • 15.5mA + 2 [52/(4•(100Ω || 804Ω))] = 296mW Maximum TJ = +85°C + (0.30W • 150°C/W) = 130°C. This absolute worst-case condition meets the specified maximum junction temperature. Actual PDL will almost always be less than that considered here. Carefully consider maximum TJ in your application. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high frequency amplifier like the OPA2652 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: +5V Supply Decoupling Not Shown 328Ω 0.1µF 1/2 OPA2652 a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. VO –5V +5V RG 500Ω 5kΩ RF 1kΩ VI 20kΩ ±200mV Output Adjustment 10kΩ Heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. b) Minimize the distance (<0.25") from the power supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. An optional supply decoupling capacitor (0.1µF) across the two power supplies (for bipolar operation) will improve 2nd harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. Operating junction temperature (TJ) is given by TA + PD•θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition, PDL = VS2/(4•RL) where RL includes feedback network loading. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA2652. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axiallyleaded resistors can also provide good high frequency performance. Again, keep their leads and PC board traces as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if 0.1µF 5kΩ VO VI =– RF RG = –2 –5V FIGURE 9. DC-Coupled, Inverting Gain of –2, with Offset Adjustment. THERMAL ANALYSIS ® OPA2652 14 any, as close as possible to the output pin. Other network components, such as non-inverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values >1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. The 402Ω feedback used in the typical performance specifications is a good starting point for design. Note that a 25Ω feedback resistor, rather than a direct short, is suggested for the unity gain follower application. This effectively isolates the inverting input capacitance from the output pin that would otherwise cause additional peaking in the gain of +1 frequency response. bility of the OPA2652 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Recommended RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high speed part like the OPA2652 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2652 onto the board. INPUT AND ESD PROTECTION d) Connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (<5pF) may not need an RS since the OPA2652 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin) If a long trace is required, and the 6dB signal loss intrinsic to a doubly terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the OPA2652 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. The high output voltage and current capa- The OPA2652 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the “Absolute Maximum Ratings” table. All device pins are protected with internal ESD protection diodes to the power supplies as shown in Figure 10. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA2652), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. +V CC External Pin Internal Circuitry –V CC FIGURE 10. Internal ESD Protection. ® 15 OPA2652