VSP3000 ® VSP3 000 12-Bit, 6MHz CCD/CIS SIGNAL PROCESSOR TM FEATURES DESCRIPTION ● 12-BIT, 6MHZ A/D CONVERTER ● GUARANTEED NO MISSING CODES ● 3 CHANNEL, 2MHz COLOR SCAN MODE: Correlated Double Samplers 8-Bit Offset Adjustment DACs 0dB to +13dB PGAs ● A/D INPUT MONITOR ● INTERNAL VOLTAGE REFERENCE ● SINGLE +5V SUPPLY ● 3V OR 5V DIGITAL OUTPUT ● LOW POWER: 475mW typ (3-CH Mode) The VSP3000 is a complete, three-channel image signal processor for Charge Coupled Device (CCD) or Contact Image Sensor (CIS) systems. Each channel contains sensor signal sampling, Black Level adjustment and a programmable gain amplifier. The three inputs are multiplexed into a high speed, 12-bit analog-to-digital converter. Input circuitry can be configured, by digital command, for CCD or CIS sensors. A Black Clamp and Correlated Double Samplers (CDS) are provided for CCD sensors. For CIS devices, the VSP3000 provides a single-ended sampler and a reference input. The VSP3000 is available in a 48-lead LQFP package and operates from 0°C to +85°C with a single +5V supply. APPLICATIONS ● CCD AND CIS COLOR SCANNERS ● FAX AND MULTI-FUNCTION MACHINES ● INDUSTRIAL /MEDICAL IMAGING SYSTEMS CLP CK1 CK2 STRT ADCCK TP0 VREF Bandgap Reference Clamp CM Timing REFT RINP CDS PGA M1 RINN REFB M2 M3 8 5 8-Bit DAC VDRV Clamp GINP CDS 12-Bit A/D MUX PGA GINN 8 B0-B11 (D0-D7, A0-A2) 12 5 8-Bit DAC OE Clamp Configuration Register BINP CDS PGA 3 BINN Offset Register 8 Gain Adjust Register 8-Bit DAC R R G G B 5 8 Register Port 8 P/S WRT B RD 5 SCLK SD 8 VSP3000 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation PDS-1444B Printed in U.S.A. August, 1999 SPECIFICATIONS At TA = full specified temperature range, VDDA = +5V, VDDD = +5V, fADCCK = 6MHz, fCK1 = 2MHz, fCK2 = 2MHz, and PGA gain = 1, unless otherwise specified. VSP3000Y PARAMETER CONDITIONS MIN RESOLUTION SPECIFIED TEMPERATURE RANGE CONVERSION CHARACTERISTICS 3-Channel CDS Mode 3-Channel CIS Mode TYP 12 Bits °C MHz MHz 0.5 3.5 10 GNDA – 0.3 VDDA + 0.3 DYNAMIC CHARACTERISTICS Integral Non-Linearity (INL) Differential Non-Linearity (DNL) No Missing Codes Input-Referred Noise ±1 0.3 12 0.3 PSRR 0.04 DIGITAL OUTPUTS Logic Family Logic Coding VDRV Supply Range Output Voltage, VDRV = +5V Low Level High Level Low Level High Level Output Voltage, VDRV = +3 Low Level High Level 3-State Enable Time 3-State Enable Time Output Capacitance Data Latency Data Output Delay LSB LSB Bits LSBs rms % FSR 10 10 3.5 1 5 µA µA V V pF CMOS Straight Binary +2.7 IOL = 50µA IOH = 50µA IOL = 1.6mA IOH = 0.5mA +5.3 V +0.1 V V V V +4.6 +0.4 +2.4 IOL = 50µA IOH = 50µA OE = LOW OE = HIGH +0.1 +2.5 20 2 5 6 CL = 15pF 40 10 12 0.8 1.5 800 Operating Operating Operating 4.7 ® VSP3000 ±2 0.75 Vp-p pF V CMOS Rising Edge of ADCCK Start Conversion DC ACCURACY Zero Error Gain Error Reference Input Resistance POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation Thermal Resistance, θJA UNITS 0 to +85 6 6 ANALOG INPUTS Full-Scale Input Range Input Capacitance Input Limits DIGITAL INPUTS Logic Family Convert Command High Level Input Current (VIN = VDDD) Low Level Input Current (VIN = 0V) High Level Input Voltage Low Level Input Voltage Input Capacitance MAX 2 5 95 475 75 V V ns ns pF Clock Cycles ns % FS % FS Ω 5.3 102 510 V mA mW C/W ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS VDDA, VDDD,VDRV ................................................................................... +6V Analog Input ....................................................... (–0.3V) to (+VDDA + 0.3V) Logic Input ......................................................... (–0.3V) to (+VDDD + 0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) VSP3000Y 48-Lead LQFP 340 0°C to +85°C VSP3000Y " " " " " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(2) TRANSPORT MEDIA VSP3000Y VSP3000Y/2K 250-Piece Tray Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP3000Y/2K” will get a single 2000piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. DEMO BOARD ORDERING INFORMATION PRODUCT PACKAGE VSP3000Y DEM-VSP3000Y The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 VSP3000 VDDA REFT CM REFB GNDA VREF VDDA GNDA TP0 GNDD VDDD VDRV PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 CLP 1 36 B11 (MSB) GNDA 2 35 B10 (A2) RINP 3 34 B9 (A1) RINN 4 33 B8 (A0) GNDA 5 32 B7 (D7) GINP 6 31 B6 (D6) VSP3000Y GINN 7 30 B5 (D5) GNDA 8 29 B4 (D4) BINP 9 28 B3 (D3) BINN 10 27 B2 (D2) GNDA 11 26 B1 (D1) 17 18 19 20 CK1 CK2 GNDD RD WRT P/S 21 22 23 24 OE 16 VDDD 15 SCLK 14 SD 13 ADCCK 25 B0 (D0, LSB) STRT VDDA 12 PIN DESCRIPTIONS PIN DESIGNATOR TYPE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLP GNDA RINP RINN GNDA GINP GINN GNDA BINP BINN GNDA VDDA STRT ADCCK CK1 CK2 GNDD RD WRT P/S DI P AI AI P AI AI P AI AI P P DI DI DI DI P DI DI DI 21 22 23 24 SD SCLK VDDD OE DI DI P DI DESCRIPTION PIN DESIGNATOR TYPE Clamp Enable Analog Ground Red-Channel Analog Input Red-Channel Reference Input Analog Ground Green-Channel Analog Input Green-Channel Reference Input Analog Ground Blue-Channel Analog Input Blue-Channel Reference Input Analog Ground Analog Power Supply, +5V Start Line Scanning A/D Converter Clock Input Sample Reference Clock Sample Data Clock Digital Ground Read Signal for Registers Write Signal for Registers Parallel/Serial Port Select. HIGH = Parallel, LOW = Serial Serial Data Input Serial Data Clock Digital Power Supply, +5V A/D Converter Output Enable 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 B0 (D0) LSB B1 (D1) B2 (D2) B3 (D3) B4 (D4) B5 (D5) B6 (D6) B7 (D7) B8 (A0) B9 (A1) B10 (A2) B11 MSB VDRV VDDD GNDD TP0 GNDA VDDA VREF GNDA REFB CM REFT VDDA DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO P P P AO P P AIO P AO AO AO P ® VSP3000 4 DESCRIPTION A/D Output (Bit 0) and Register Data Port (Bit 0) A/D Output (Bit 1) and Register Data Port (Bit 1) A/D Output (Bit 2) and Register Data Port (Bit 2) A/D Output (Bit 3) and Register Data Port (Bit 3) A/D Output (Bit 4) and Register Data Port (Bit 4) A/D Output (Bit 5) and Register Data Port (Bit 5) A/D Output (Bit 6) and Register Data Port (Bit 6) A/D Output (Bit 7) and Register Data Port (Bit 7) A/D Output (Bit 8) and Register Address (Bit 0) A/D Output (Bit 9) and Register Address (Bit 1) A/D Output (Bit 10) and Register Address (Bit 2) A/D Output (Bit 11) Output Driver Voltage Supply Digital Power Supply, +5V Digital Ground A/D Converter Input Monitor Pin Analog Ground Analog Power Supply, +5V Reference Input/Output Analog Ground Bottom Reference Common-Mode Voltage Top Reference Analog Power Supply, +5V TIMING SPECIFICATIONS Timing Specifications = tMIN to tMAX with +5V power supply. SYMBOL PARAMETER MIN TYP 3-Channel Conversion Rate 1-Channel Conversion Rate CK1 Pulse Width CK1 Pulse Width CK2 Pulse Width CK2 Pulse Width ADCCK Pulse Width ADCCK Period Sampling Delay CK1 Falling Edge to CK2 Rising Edge CK1 Falling Edge to CK2 Rising Edge CK2 Falling Edge to CK1 Rising Edge CK2 Falling Edge to CK1 Rising Edge Conversion Delay Start Conversion Time ADCCK Falling Edge to CK1 Rising Edge ADCCK Falling Edge to CK2 Falling Edge ADCCK Falling Edge to CK1 Falling Edge 300 100 20 20 20 20 40 100 10 15 15 70 40 40 20 10 5 5 500 166 125 40 125 40 83 166 tW tRW tDA tWD tSD tSCK tSCKP tSS tSW tPR tRD tRH WRT Pulse Width Address Setup Time Data Setup Time Data Valid Time Data Ready Time Serial Clock Pulse Width Serial Clock Period Serial Ready Time WRT Pulse Setup Time Parallel Ready Time Read Out Delay Read Out Hold Time 30 20 30 50 50 50 15 30 60 100 50 20 50 50 100 200 tOES tOEW tOER t3E tACKD tOEP A/D Converter Output Enable Setup Time OE Pulse Width Output Enable Time 3-State Enable Time Data Output Delay Parallel Port Setup Time MAX UNITS Clock Parameters tCK1AP tCK1BP tCK1A tCK1B tCK2A tCK2B tCCK tCKP tS tCK12A tCK12B tCK21A tCK21B tCNV tST tSET tADCCK2 tADCCK1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 Read/Write Register 30 20 1 ns ns ns ns ns ns ns ns ns ns ns ns Data Output 20 100 20 2 40 10 12 10 ns ns ns ns ns ns ® 5 VSP3000 TIMING DIAGRAMS 3-Channel CCD Mode Timing R1, G1, B1 CCD tS tS STRT tST tCK1AP tCK1A CK1 tSET tCK12A tCK2A CK2 tCK21A tADCCK2 tCCK ADCCK R tCNV tCCK G B R1 G1 B1 tCKP 3-Channel CIS Mode Timing CIS R1, G1, B1 tS STRT tST tSET tCK1A tCK1AP CK1 tCCK ADCCK R tCCK tADCCK1 G tCNV B R1 G1 B1 tCKP 1-Channel CCD Mode Timing Pixel 1 CCD tS tS STRT tCK1BP tCK1B CK1 tSET tCK12B tCK2B tCK21B CK2 tCNV tCCK ADCCK tCCK Pixel 1 tCKP ® VSP3000 6 TIMING DIAGRAMS (Cont) 1-Channel CIS Mode Timing CIS Pixel 1 tS STRT tCK1BP tCK1B CK1 tSET tCNV tCCK ADCCK Pixel 1 tCCK tCKP Timing for A/D Output tOEP P/S tOES tOEW OE t3E tOER Valid DOUT tACKD ADCCK Timing for Parallel Port Writing Timing for Reading tPR tPR P/S A2-A0 P/S Stable Register tRW D7-D0 Stable A2-A0 tDA Stable tRW WRT RD tW Register Valid tDA tRH tRD Valid D7-D0 Valid ® 7 VSP3000 TIMING DIAGRAMS (Cont) Timing for Serial Port Writing P/S tSS tSCK tSCK SCLK tSCKP tSD A2 SD A1 A0 D7 tSW D6 D5 D4 D3 D2 D1 D0 tW WRT tWD Data Valid DOUT Timing Diagram—3-Channel CDS Mode N (N+1) R, G, B CCD (N+2) R, G, B (N+3) R,G, B R, G, B Start CK1 CK2 ADCCK DOUT (N–3) R (N–3) G (N–3) B (N–2) R (N–2) G (N–2) B (N–1) R ® VSP3000 8 (N–1) G (N–1) B NR NG NB (N+1) R (N+1) G TYPICAL PERFORMANCE CURVES At TA = +25°C, VDDA = +5V, VDDD = +5V, fADCCK = 6MHz, and fCK2 = 2MHz, unless otherwise specified. POWER DISSIPATION vs POWER SUPPLY VOLTAGE 3-CHANNEL MODE PGA TRANSFER FUNCTION Sample Quantity, N = 100 600 5.0 4.5 Power Dissipation (mV) 4.0 3.5 2.5 2.0 1.5 1.0 400 300 200 0.5 100 4.70 0 0 5 10 15 20 25 31 4.80 4.90 5.00 5.10 5.20 5.30 Power Supply Voltage (V) PGA Gain Setting POWER DISSIPATION vs POWER SUPPLY VOLTAGE 1-CHANNEL MODE 600 Power Dissipation (mV) Gain 3.0 500 500 400 300 200 100 4.70 4.80 4.90 5.00 5.10 5.20 5.30 Power Supply Voltage (V) ® 9 VSP3000 THEORY OF OPERATION 12-bit A/D converter. The analog MUX can be programmed to cycle between red, green, and blue or blue, green, and red. The VSP3000 can be operated in one of the following four modes: 3-Channel 3-Channel 1-Channel 1-Channel When the STRT signal is HIGH, the conversion is initiated on the rising edge of ADCCK. The STRT signal indicates the first sample for a scan line. When STRT goes LOW, the analog MUX is switched to the first sample of the sequence. CCD Mode CIS Mode CCD Mode CIS Mode As specified in the “3-Channel CIS Mode” timing diagram, the falling edge of CK1 must be in the LOW period of ADCCK. If the falling edge of CK1 is in the HIGH period of ADCCK (note: ADCCK is for sampling the B Channel), the VSP3000 will not function properly. 3-CHANNEL CCD MODE In this mode, the VSP3000 can simultaneously process three output CCD signals. These signals are AC-coupled to the RINP, GINP, and BINP inputs. RINN, GINN, BINN are not used in this mode and should be grounded. The CLP signal enables internal biasing circuitry to clamp these inputs to a proper voltage, enabling internal CDS circuitry to operate properly. VSP3000 inputs may be applied as DC-coupled inputs, which need to be level-shifted to a proper DC level. 1-CHANNEL CCD MODE In this mode, the VSP3000 processes only one CCD signal. The CCD signal is AC-coupled to RINP, GINP, or BINP (as selected by the data in the Configuration Register). RINN, GINN, BINN are not used in this mode and should be grounded. The CLP signal enables internal biasing circuitry to clamp this input to a proper voltage so that internal CDS circuitry can work properly. The VSP3000 input may be applied as a DC-coupled input, which needs to be levelshifted to a proper DC level. The correlated double samplers take two samples of the incoming CCD signals; the CCD reference levels are taken on the falling edge of CK1 and the CCD information is taken on the falling edge of CK2. These two samples are then subtracted by the CDSs and the result is the CDS’ output. The CDS takes two samples of the incoming CCD signal. The CCD reference value is taken on the falling edge of CK1 and the CCD information is taken on the falling edge of CK2. These two samples are then subtracted by the CDS and the result is the CDS’ output. Three channels are used to process three inputs simultaneously. Each consists of a 5-bit PGA (0dB to +13dB) and an 8-bit offset digital-to-analog converter (+50mV to –150mV). A 3-to-1 analog MUX follows the CDS channels and feeds a high performance 12-bit A/D converter. The analog MUX can be programmed to cycle between red, green, and blue or blue, green, and red. In this mode, only one of the three channels is enabled. Each CDS consists of a 5-bit PGA (0dB to +13dB) and an 8-bit offset DAC (+50mV to –150mV). A 3-to-1 analog MUX is inserted between the CDSs and a high performance 12-bit A/ D converter. The analog MUX is not cycling between channels in this mode. Instead, the analog MUX is connected to a specific channel, depending on the data in the Configuration Register. When the STRT signal is HIGH, the conversion is initiated on the rising edge of ADCCK. The STRT signal indicates the first samples for a scan line. When STRT goes LOW, the analog MUX is switched to the first sample of the sequence. As specified in the “3-Channel CCD Mode” timing diagram, the falling edge of CK2 must be in the LOW period of ADCCK. If the falling edge of CK2 is in the HIGH period of ADCCK (note: ADCCK is for sampling the B Channel), the VSP3000 will not function properly. As specified in the “1-Channel CCD Mode” timing diagram, both the active period of CK1 (tCK1B) and the active period of CK2 (tCK2B) must be in the LOW period of ADCCK. If it is in the HIGH period of ADCCK, the VSP3000 will not function properly. 3-CHANNEL CIS MODE 1-CHANNEL CIS MODE In this mode, the VSP3000 is operated as 3-channel samplers and a digitizer. Unlike the CDS mode, VSP3000 takes only one sample on the falling edge of CK1 for each input. Since only one sample is taken, CK2 is grounded in this operation. The input signal is DC-coupled in most cases. For example, for the red channel, RINP is the CIS signal input, and RINN is the CIS reference signal. The same applies to the green channel (GINP and GINN) and blue channel (BINP and BINN). In this mode, the VSP3000 is operated as a 1-channel sampler and digitizer. Unlike the CDS mode, VSP3000 takes only one sample on the falling edge of CK1. Since only one sample is taken, CK2 is grounded in this operation. The input signal is DC-coupled in most cases. Here, the VSP3000 inputs are differential. For example, for the red channel, RINP is the CIS signal input, and RINN is the CIS reference signal. The same applies to the green channel (GINP and GINN) and blue channel (BINP and BINN). In this mode, three CDSs become CIS signal processing circuits (acting like a track-and-hold) to process three inputs simultaneously. Each CIS signal processing circuit consists of a 5-bit PGA (0dB to +13dB) and an 8-bit offset DAC (+50mV to –150mV). A 3-to-1 analog MUX follows the CIS signal processing circuits and feeds a high performance In this mode, the CDS becomes a CIS signal processing circuit (acting like a track-and-hold). Each CIS signal processing circuit consists of a 5-bit PGA (0dB to +13dB) and an 8-bit offset DAC (+50mV to –150mV). A 3-to-1 analog MUX follows the CIS signal processing circuits and feeds a ® VSP3000 10 high performance 12-bit A/D converter. The analog MUX is not cycling between channels in this mode. Instead, the analog MUX is connected to a specific channel, depending on the data in the Configuration Register. VCLAMP, is derived from the reference. VCLAMP depends on the value of VREF; if VREF is set to 1V, VCLAMP is 2.5V and if VREF is set to 1.5V, VCLAMP is 3V. There are many factors that determine the size of the input coupling capacitors including CCD signal swing, voltage droop across the input capacitor since the last clamp interval, leakage current of the VSP3000 input circuitry, and the time period of CK1. Figure 2 shows a simplified equivalent circuit of the VSP3000 inputs. In this equivalent circuit, the input coupling capacitor, CIN, and the sampling capacitor, C1, are constructed as a capacitor divider (during CK1). For AC analysis, op amp inputs are grounded. Therefore, the sampling voltage, VS (during CK1) is: As specified in the “1-Channel CIS Mode” timing diagram, the active period of CK1 (tCK1B) must be in the LOW period of ADCCK. If it is in the HIGH period of ADCCK, the VSP3000 will not function properly. ANALOG PGA There is one analog PGA on each channel. Each analog PGA is controlled by a 5-bit PGA gain register. The analog PGA gain varies from 1 to 4.44 (0dB to +13dB). The transfer function of the PGA is: VS = (CIN/CIN + C1)) • VIN From this equation, we see that a larger value of CIN makes VS closer to VIN. In other words, the input signal VIN will be attenuated less if CIN is large. However, there is a disadvantage to using a large value of CIN: the larger the CIN, the more dummy or optical black pixels must be used to restore the DC component of the input signal. Gain = 4/(4 – 0.1 • X) where X is the integer representation of the 5-bit PGA gain register. Figure 1 shows the PGA transfer function plot. PGA TRANSFER FUNCTION 4.5 CK1 4.0 C1 4pF Gain 3.5 CIN VIN 3.0 2.5 VS OP AMP C2 4pF CLP 2.0 CK2 CK1 1.5 1.0 0 5 10 15 20 25 31 VCLAMP PGA Gain Setting FIGURE 2. Equivalent Circuit of VSP3000 Inputs. PGA TRANSFER FUNCTION 14 CHOOSING CMAX AND CMIN 12 6 As mentioned previously, a large CIN is preferable if there is enough time for the CLP signal to charge up CIN. Typically, 0.01µF to 0.1µF of CIN can be used for most cases. In order to optimize CIN, the following two equations can be used to calculate CMAX and CMIN: 4 CMAX = ( tCK1 • N)/[RSW • ln (VD/VERROR)] Gain (dB) 10 8 where, tCK1 is the time when both CK1 and CLP are HIGH and N is the number of black pixels, RSW is the total switch resistance, VD is the droop across CIN and VERROR is the difference between VS and VCLAMP. The nominal value of RSW is 4kΩ plus the driver’s impedance. 0.1V should be tolerable for VERROR and still keep the VSP3000 working properly. 2 0 0 5 10 15 20 25 31 PGA Gain Setting FIGURE 1. PGA Transfer Function Plot. CHOOSING AC INPUT COUPLING CAPACITORS CMIN = ( I/VERROR) • t The purpose of the input coupling capacitor is to isolate the DC output of the CCD array from affecting the VSP3000. The internal clamping circuitry restores the necessary DC component to the CCD output signal. The internal clamp voltage, where, I is 10nA, the typical leakage current of the VSP3000 input circuitry and t is the time between clamp pulses. ® 11 VSP3000 PROGRAMMING THE VSP3000 For this example, VREF will be 1V. The VSP3000 consists of three CCD or CIS channels and a 12bit A/D converter. Each channel (red, green, and blue) has its own 8-bit offset and 5-bit gain adjustable registers to be programmed by the user. There is also a 7-bit Configuration Register on-chip to program the different operation modes. These registers are as follows: Bypass VREF with 10µF and 0.1µF capacitors when internal reference mode is used. Example: A 1-channel CIS mode (red channel) with external 1.2V reference: = > D0 = ‘1’, D1 = X, D2 = ‘1’, D4 = ‘0’ and D5 = ‘0’ For this example, VREF will be an input pin, applied with 1.2V. This input will set the full-scale input of the VSP3000 at 2.4V. ADDRESS A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 REGISTER Configuration Register (7-Bit) Red Channel Offset Register (8-Bit) Green Channel Offset Register (8-Bit) Blue Channel Offset Register (8-Bit) Red Channel Gain Register (5-Bit) Green Channel Gain Register (5-Bit) Blue Channel Gain Reigster (5-Bit) Reserved Offset Registers Offset registers control the analog offset input to the channel prior to the PGA. There is an 8-bit Offset Register on each channel. The offset range varies from –150mV to +50mV. The Offset Register uses a Straight Binary code. All ‘0’s correspond to –150mV and all ‘1’s correspond to +50mV of the offset adjustment. These Registers can be accessed by either the parallel or serial port. In the parallel mode, the address and data port are combined with the ADC data output pins. The data bus is assigned as D0 to D7 (pin 25 to pin 32) and the address bus is A0 to A2 (pin 33 to pin 35). In the serial mode, serial data (SD), serial clock (SCLK), and write signal (WRT pin for both parallel and serial writing) are assigned. The following table shows how to access these modes. OE P/S 0 0 1 1 0 1 0 1 PGA Gain Registers The PGA Gain Registers control the analog gain to the channels prior to the A/D converter. There is a 5-bit PGA Gain Register on each channel. The gain range varies from 1 to 4.44 (0dB to +13dB). The PGA Gain Register is a Straight Binary code. All ‘0’s correspond to analog gain of 0dB and all ‘1’s correspond to the analog gain of 13dB. MODE Offset and Gain Calibration Sequence A/D Data Output Enabled, Serial Mode Enabled Prohibit Mode A/D Data Output Disabled, Serial Mode Enabled A/D Data Output Disabled, Parallel Mode Enabled When the VSP3000 is powered on, it will be initialized as a 3-channel CDS, 1V internal (2V full scale) reference mode with analog gain of 1. This mode is commonly used for CCD scanner applications. The calibration procedure is done at the very beginning of the scan. Once calibration is done, registers on VSP3000 will keep this information (offset and gain for each channel) during the operation. Configuration Register The Configuration Register is designed as follows: To calibrate the VSP3000, use the following procedure: BIT LOGIC ‘0’ LOGIC ‘1’ D0 D1 D2 D3 CDS Mode VREF = 1V Internal Reference 3-Channel, D4 and D5 Disabled CIS Mode VREF = 1.5V External Reference 1-Channel, D4 and D5 Enabled D4 D5 0 0 Red Channel 0 1 Green Channel 1 0 Blue Channel 1 1 XXXXXXXX D6 D7 R > G > B MUX Sequence XXXXXXXX Step 1: Set the VSP3000 to the proper mode. Step 2: Set analog PGA gain to 1 (code: 00H) and offset to 0mV (code: C0H). Step 3: Scan a dark line. Step 4: Calculate the pixel offsets according to the ADC output. Step 5: Readjust input Offset Registers. Step 6: Scan a white line. B > G > R MUX Sequence XXXXXXXX Step 7: Calculate gain. It will be the ADC full scale divided by the ADC output when the white line is scanned. Step 8: Set the Gain Register. If the ADC output is not close to full scale, go back to Step 3. The calibration is complete if the output is close to full scale. For Reading/Writing to the Configuration Register, the address will be: A2 = ‘0’, A1 = ‘0’, and A0 = ‘0’ Example: A 3-channel CDS with internal reference VREF = 1V (2V fullscale input), the mode will be: = > D0 = ‘0’, D1 = ‘0’and D3 = ‘0’ ® VSP3000 12 STRT BNC4 BNC3 BNC2 BNC1 R4 50Ω R3 50Ω R2 50Ω R1 50Ω TP1 ADCCK BNC5 JP3 C3 0.1µF JP2 C2 0.1µF JP1 C1 0.1µF TP3 TP2 TP1 R5 50Ω TP5 BINN GINN RINN CLP CK1 BNC6 + C18 10µF BINP 9 R6 50Ω TP6 CM CK1 ADCCK C9 0.1µF TP0 VDRV VSP3000 CK2 BNC7 R7 50Ω TP7 RD WRT P/S SD C10 0.1µF (LSB) B0 (D0) 25 B1 (D1) 26 B2 (D2) 27 B3 (D3) 28 B4 (D4) 29 B5 (D5) 30 B6 (D6) 31 B7 (D7) 32 B8 (A0) 33 B9 (A1) 34 B10 (A2) 35 (MSB) B11 36 SCLK OE 13 14 15 16 17 18 19 20 21 22 23 24 12 VDDA 11 GNDA 10 BINN GNDA 8 GINN GINP 6 7 GNDA RINN 5 4 RINP GNDA 2 3 CLP 1 REFT 48 47 46 45 44 43 42 41 40 39 38 37 C8 0.1µF C7 10µF + REFB CK2 C17 0.1µF C6 0.1µF GNDA GNDD JP4 C5 0.1µF VREF RD VDDA STRT VDDA WRT + C16 10µF C4 0.1µF GNDA P/S VDD TP0 SD VDRV C15 0.1µF VDRV GNDD SCLK VDDD VDDD 13 OE VDDD VDDA C11 0.1µF VDDD R10 1kΩ R8 1kΩ C12 0.1µF 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 IDT74FCT541T IDT74FCT541T VDDA VDD C13 0.1µF 23 14 20 19 18 17 16 C14 0.1µF 21 13 39 33 19 15 17 12 15 13 11 11 20 19 18 17 16 R11 1kΩ 7 14 R9 1kΩ 5 13 9 3 12 15 1 11 40 38 37 36 35 34 33 32 31 30 OE ADCCK B0 (LSB) B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 (MSB) 29 28 27 26 25 24 22 20 18 15 14 12 10 8 6 4 2 EVALUATION BOARD SCHEMATIC VSP3000 ®