SN75HVD08, SN65HVD08 www.ti.com SLLS550A – NOVEMBER 2002 – REVISED MAY 2003 WIDE SUPPLY RANGE RS-485 TRANSCEIVER FEATURES • • • • • • • Operates With a 3-V to 5.5-V Supply Consumes Less Than 90 mW Quiescent Power Open-Circuit, Short Circuit, and Idle-Bus Failsafe Receiver 1/8th Unit-Load (up to 256 nodes on the bus) Bus-Pin ESD Protection Exceeds 16 kV HBM Driver Output Voltage Slew-Rate Limited for Optimum Signal Quality at 10 Mbps Electrically Compatible With ANSI TIA/EIA-485 Standard The wide supply voltage range and low quiescent current requirements allow the SN65HVD08s to operate from a 5-V power bus in the cable with as much as a 2-V line voltage drop. Busing power in the cable can alleviate the need for isolated power to be generated at each connection of a ground-isolated bus. The driver differential outputs and receiver differential inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or not powered. The drivers and receivers have active-high and active-low enables respectively, which can be externally connected together to function as a direction control. APPLICATIONS • • • • • D or P PACKAGE (TOP VIEW) Data Transmission With Remote Stations Powered From the Host Isolated Multipoint Data Buses Industrial Process Control Networks Point-of-Sale Networks Electric Utility Metering DESCRIPTION R RE DE D 1 8 2 7 3 6 4 5 VCC B A GND LOGIC DIAGRAM (Positive Logic) The SN65HVD08 combines a 3-state differential line driver and differential line receiver designed for balanced data transmission and interoperation with ANSI TIA/EIA-485-A and ISO-8482E standard-compliant devices. A D B DE RE R Remote (One of n Shown) Host 5 V Power Direct Connection to Host Isolation Barrier SN65HVD08 5 V Return Power Bus and Return Resistance Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2003, Texas Instruments Incorporated SN75HVD08, SN65HVD08 www.ti.com SLLS550A – NOVEMBER 2002 – REVISED MAY 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION SPECIFIED TEMPERATURE RANGE PACKAGE SN65HVD08D –40°C to 85°C SOIC VP08 SN65HVD08P –40°C to 85°C PDIP 65HVD08 SN75HVD08D 0°C to 70°C SOIC VN08 SN75HVD08P 0°C to 70°C PDIP 75HVD08 PART NUMBER PACKAGE MARKING PACKAGE DISSIPATION RATINGS TA≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING SOIC (D) 710 mW 5.7 mW/°C 369 mW PDIP (P) 1000 mW 8 mW/°C 520 mW PACKAGE ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) (2) UNIT Supply voltage, VCC -0.3 V to 6 V Voltage range at A or B -9 V to 14 V Input voltage range at D, DE, R or RE -0.5 V to VCC + 0.5 V Voltage input range, transient pulse, A and B, through 100 Ω Electrostatic discharge Human Body Model (3) Charged-Device Model (4) -25 V to 25 V A, B, and GND 16 kV All pins 4 kV All pins Continuous total power dissipation Storage temperature, Tstg (1) (2) (3) (4) 1 kV See Dissipation Rating Table -65°C to 150°C Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VCC Input voltage at any bus terminal (separately or common mode), VI (1) High-level input voltage, VIH Low-level input voltage, VIL Driver, driver enable, and receiver enable inputs Differential input voltage, VID High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA (1) 2 Driver Receiver NOM MAX UNIT 3 5.5 V –7 12 V 2.25 VCC 0 0.8 –12 12 –60 mA –8 Driver 60 Receiver V 8 SN75HVD08 0 70 SN65HVD08 –40 85 The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. mA °C SN75HVD08, SN65HVD08 www.ti.com SLLS550A – NOVEMBER 2002 – REVISED MAY 2003 ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS |VOD| Driver differential output voltage magnitude RL= 60 Ω, 375 Ω on each output to -7 V to 12 V, See Figure 1 ∆|VOD| Change in magnitude of driver differential output voltage RL= 54 Ω VOC(PP) Peak-to-peak driver common-mode output voltage Center of two 27-Ω load resistors, See Figure 2 VIT+ Positive-going receiver differential input voltage threshold VIT- Negative-going receiver differential input voltage threshold Vhys Receiver differential input voltage threshold hysteresis(VIT+ - VIT-) VOH Receiver high-level output voltage IOH = -8 mA VOL Receiver low-level output voltage IOL = 8 mA IIH Driver input, driver enable, and receiver enable high-level input current IIL Driver input, driver enable, and receiver enable low-level input current IOS Driver short-circuit output current MIN TYP MAX UNIT 1.5 VCC V –0.2 0.2 V 0.5 –10 Bus input current (disabled driver) mV 35 7 V < VO < 12 V VI = -7 V Supply current mV 2.4 V 0.4 V –100 100 µA –100 100 µA –265 265 mA 130 –100 VI = 12 V, VCC = 0 V VI = -7 V. VCC = 0 V ICC mV –200 VI = 12 V II V µA 130 –100 Receiver enabled, driver disabled, no load 10 Driver enabled, receiver disabled, no load 16 mA Both disabled Both enabled, no load 5 µA 16 mA DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX tPHL Driver high-to-low propagation delay time 18 40 tPLH Driver low-to-high propagation delay time 18 40 tr Driver 10%-to-90% differential output rise time 10 55 tf Driver 90%-to-10% differential output fall time tSK(P) Driver differential output pulse skew, |tPHL - tPLH| ten Driver enable time tdis Driver disable time RL = 54 Ω, CL = 50 pF,See Figure 3 10 UNIT ns 55 2.5 Receiver enabled, See Figures 4 and 5 55 ns Receiver disabled, See Figures 4 and 5 6 µs Receiver enabled, See Figures 4 and 5 90 ns 3 SN75HVD08, SN65HVD08 www.ti.com SLLS550A – NOVEMBER 2002 – REVISED MAY 2003 RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS tPHL Receiver high-to-low propagation delay time tPLH Receiver low-to-high propagation delay time tr Receiver 10%-to-90% differential output rise time tf Receiver 90%-to-10% differential output fall time tSK(P) Receiver differential output pulse skew, |tPHL - tPLH| ten Receiver enable time tdis Receiver disable time MIN TYP MAX UNIT 70 70 CL = 15 pF, See Figure 6 5 ns 5 4.5 Driver enabled, See Figure 7 15 ns Driver disabled, See Figure 8 6 µs Driver enabled, See Figure 7 20 ns PARAMETER MEASUREMENT INFORMATION 375 Ω ±1% VCC DE D A VOD 0 or 3 V 60 Ω ±1% + _ B –7 V < V(test) < 12 V 375 Ω ±1% Figure 1. Driver VOD With Common-Mode Loading Test Circuit VCC DE Input D 27 Ω ± 1% A VA B VB VOC(PP) 27 Ω ± 1% B A CL = 50 pF ±20% VOC ∆VOC(SS) VOC CL Includes Fixture and Instrumentation Capacitance Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω Figure 2. Test Circuit and Definitions for the Driver Common-Mode Output Voltage 3V VCC DE D Input Generator VI 50 Ω CL = 50 pF ±20% A B VOD RL = 54 Ω ± 1% CL Includes Fixture and Instrumentation Capacitance 1.5 V VI tPLH tPHL 90% VOD 90% 0V 10% tr Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω Figure 3. Driver Switching Test Circuit and Voltage Waveforms 4 1.5 V ≈2V 0V 10% ≈ –2 V tf SN75HVD08, SN65HVD08 www.ti.com SLLS550A – NOVEMBER 2002 – REVISED MAY 2003 Parameter Measurement Information (continued) A 3V D 3V S1 VO VI 1.5 V 1.5 V B DE Input Generator VI CL = 50 pF ±20% 50 Ω CL Includes Fixture and Instrumentation Capacitance 0V 0.5 V RL = 110 Ω ± 1% tPZH VOH VO 2.3 V ≈0V tPHZ Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω Figure 4. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms 3V A 3V D VI ≈3V 1.5 V VI S1 1.5 V VO DE Input Generator RL = 110 Ω ± 1% 50 Ω 0V B tPZL tPLZ ≈3V CL = 50 pF ±20% 0.5 V CL Includes Fixture and Instrumentation Capacitance VO 2.3 V VOL Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω Figure 5. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms A Input Generator R VI 50 Ω 1.5 V 0V B VO CL = 15 pF ±20% RE CL Includes Fixture and Instrumentation Capacitance Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω 3V 1.5 V VI 1.5 V 0V tPLH VO tPHL 90% 90% 1.5 V 10% tr VOH 1.5 V 10% V OL tf Figure 6. Receiver Switching Test Circuit and Voltage Waveforms 5 SN75HVD08, SN65HVD08 www.ti.com SLLS550A – NOVEMBER 2002 – REVISED MAY 2003 Parameter Measurement Information (continued) 3V VCC A DE 0 V or 3 V R D VO B RE Input Generator VI A 1 kΩ ± 1% S1 CL = 15 pF ±20% B CL Includes Fixture and Instrumentation Capacitance 50 Ω Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω 3V VI 1.5 V 1.5 V 0V tPZH tPHZ VOH –0.5 V VOH D at 3 V S1 to B 1.5 V VO ≈0V tPZL tPLZ ≈ VCC VO 1.5 V VOL +0.5 V D at 0 V S1 to A VOL Figure 7. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled 6 SN75HVD08, SN65HVD08 www.ti.com SLLS550A – NOVEMBER 2002 – REVISED MAY 2003 Parameter Measurement Information (continued) VCC A 0 V or 1.5 V R B 1.5 V or 0 V B CL Includes Fixture and Instrumentation Capacitance 50 Ω VI S1 CL = 15 pF ±20% RE Input Generator A 1 kΩ ± 1% VO Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω 3V 1.5 V VI 0V tPZH VOH A at 1.5 V B at 0 V S1 to B 1.5 V VO GND tPZL ≈ VCC 1.5 V VO A at 0 V B at 1.5 V S1 to A VOL Figure 8. Receiver Enable Time From Standby (Driver Disabled) DEVICE INFORMATION Function Tables DRIVER INPUT ENABLE D DE A OUTPUTS H L X Open H H L H H L Z H B L H Z L RECEIVER (1) DIFFERENTIAL INPUTS ENABLE (1) OUTPUT (1) VID = VA - VB RE R VID≤ -0.2 V -0.2 V < VID < -0.01 V -0.01 V ≤ VID X Open Circuit Short Circuit L L L H L L L ? H Z H H H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate 7 SN75HVD08, SN65HVD08 www.ti.com SLLS550A – NOVEMBER 2002 – REVISED MAY 2003 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS D and RE Inputs DE Input VCC VCC 100 kΩ 1 kΩ 1 kΩ Input Input 100 kΩ 9V 9V A Input B Input VCC VCC 16 V 100 kΩ 16 V 36 kΩ 180 kΩ 180 kΩ Input Input 16 V 36 kΩ 36 kΩ 100 kΩ 16 V A and B Outputs 36 kΩ R Output VCC VCC 16 V 5Ω Output Output 9V 16 V 8 SN75HVD08, SN65HVD08 www.ti.com SLLS550A – NOVEMBER 2002 – REVISED MAY 2003 TYPICAL CHARACTERISTICS DIFFERENTIAL OUTPUT VOLTAGE vs SUPPLY VOLTAGE DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE 4 70 D and DE at VCC RL = 54 Ω 60 I O – Driver Output Current – mA 3.5 Differential Output Voltage – V TA = 25°C DE at VCC D at VCC RL = 54 Ω TA = –40°C TA = 25°C 3 TA = 85°C 2.5 2 1.5 50 40 30 20 10 3 3.5 4 4.5 5 VCC – Supply Voltage – V 0 0.6 1.2 1.8 2.4 3 3.6 4.2 VCC – Supply Voltage – V 4.8 Figure 10. RMS SUPPLY CURRENT vs SIGNALING RATE LOGIC INPUT THRESHOLD VOLTAGE vs SUPPLY VOLTAGE TA = 25°C D, DE or RE input 100 80 60 40 2.5 5 Signaling Rate – Mbps Figure 11. 5.4 2.5 RL = 54 Ω CL = 50 pF VCC = 5 V TA = 25°C RE at VCC DE at VCC 0 0 6 Figure 9. 120 I CC – RMS Supply Current – mA 5.5 Logic Input Threshold Voltage – V 1 2.5 7.5 10 2 Positive Going 1.5 Negative Going 1 0.5 0 2.5 3.5 4.5 5.5 VCC – Supply Voltage – V 6.5 Figure 12. 9 SN75HVD08, SN65HVD08 www.ti.com SLLS550A – NOVEMBER 2002 – REVISED MAY 2003 APPLICATION INFORMATION As electrical loads are physically distanced from their power source, the effects of supply and return line impedance and the resultant voltage drop must be accounted. If the supply regulation at the load cannot be maintained to the circuit requirements, it forces the use of remote sensing, additional regulation at the load, bigger or shorter cables, or a combination of these. The SN65HVD08 eases this problem by relaxing the supply requirements to allow for more variation in the supply voltage over typical RS-485 transceivers. SUPPLY SOURCE IMPEDANCE In the steady state, the voltage drop from the source to the load is simply the wire resistance times the load current as modeled in Figure 13. RS IL + + RL VL = VS – 2RSIL VS – RS – Figure 13. Steady-State Circuit Model For example, if you were to provide 5-V ±5% supply power to a remote circuit with a maximum load requirement of 0.1 A (one SN65HVD08), the voltage at the load would fall below the 4.5-V minimum of most 5-V circuits with as little as 5.8 m of 28-GA conductors. Table 1 summarizes wire resistance and the length for 4.5 V and 3 V at the load with 0.1 A of load current. The maximum lengths would scale linearly for higher or lower load currents. Under dynamic load requirements, the distributed inductance and capacitance of the power lines may not be ignored and decoupling capacitance at the load is required. The amount depends upon the magnitude and frequency of the load current change but, if only powering the SN65HVD08, a 0.1 µF ceramic capacitor is usually sufficient. OPTO-ISOLATED DATA BUSES Long RS-485 circuits can create large ground loops and pick up common-mode noise voltages in excess of the range tolerated by standard RS-485 circuits. A common remedy is to provide galvanic isolation of the data circuit from earth or local grounds. Transformers, capacitors, or phototransistors most often provide isolation of the bus and the local node. Transformers and capacitors require changing signals to transfer the information over the isolation barrier and phototransistors (opto-isolators) can pass steady-state signals. Each of these methods incurs additional costs and complexity, the former in clock encoding and decoding of the data stream and the latter in requiring an isolated power supply. Quite often, the cost of isolated power is repeated at each node connected to the bus as shown in Figure 14. The possibly lower-cost solution is to generate this supply once within the system and then distribute it along with the data line(s) as shown in Figure 15. DC-to-DC Converter Opto Isolators Local Power Source Rest of Board Table 1. Maximum Cable Lengths for Minimum Load Voltages at 0.1 A Load WIRE SIZE RESISTANCE 4.5 V LENGTH AT 0.1 A 3-v LENGTH AT 0.1 A 28 Gage 0.213 Ω/m 5.8 m 41.1 m 24 Gage 0.079 Ω/m 15.8 m 110.7 m 22 Gage 0.054 Ω/m 23.1 m 162.0 m 20 Gage 0.034 Ω/m 36.8 m 257.3 m 18 Gage 0.021 Ω/m 59.5 m 416.7 m DC-to-DC Converter Opto Isolators Local Power Source Rest of Board Figure 14. Isolated Power at Each Node 10 SN75HVD08, SN65HVD08 www.ti.com SLLS550A – NOVEMBER 2002 – REVISED MAY 2003 AN OPTO ALTERNATIVE The ISO150 is a two-channel, galvanically isolated data coupler capable of data rates of 80 Mbps. Each channel can be individually programmed to transmit data in either direction. Local Power Source Opto Isolators Rest of Board Data is transmitted across the isolation barrier by coupling complementary pulses through high-voltage 0.4-pF capacitors. Receiver circuitry restores the pulses to standard logic levels. Differential signal transmission rejects isolation-mode voltage transients up to 1.6 kV/ms. SN65HVD08 ISO150 avoids the problems commonly associated with opto-couplers. Optically-isolated couplers require high current pulses and allowance must be made for LED aging. The ISO150's Bi-CMOS circuitry operates at 25 mW per channel with supply voltage range matching that of the SN65HVD08 of 3 V to 5.5 V. Local Power Source Opto Isolators Rest of Board Figure 16 shows a typical circuit. Figure 15. Distribution of Isolated Power The features of the SN65HVD08 are particularly good for the application of Figure 15. Due to added supply source impedance, the low quiescent current requirements and wide supply voltage tolerance allow for the poorer load regulation. –5 V +5 V Data (I/O) SN65HVD08 D D2A R/T2A ISO150 GA VSB R/T2B D2B DE A B Bus Channel 1 RE R Side A Side B Channel 2 D1A R/T1A VSA GA R/T1B D1B DE/RE +5 V “1” +5 V Figure 16. Isolated RS-485 Interface 11 MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. 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