NX2710 SINGLE CHANNEL PWM CONTROLLER WITH NMOS LDO CONTROLLER AND 5V BIAS REGULATOR ADVANCE DATA SHEET Pb Free Product DESCRIPTION The NX2710 controller IC is a compact synchronous Buck controller IC with 16 lead SOIC package designed for step down DC to DC converter applications with feedforward functionality. Voltage feedforward provides fast response, good line regulation and nearly constant power stage gain under wide voltage input range. The NX2710 controller is optimized to convert single supply up to 24V bus voltage to as low as 0.8V output voltage. Internal UVLO keeps the regulator off until the supply voltage exceeds 9V where internal digital soft starts get initiated to ramp up output. The NX2710 employs programmable current limiting and FB UVLO followed by HICCUP feature. Other features include: 5V gate drive, Programmable frequency from 300kHz to 1MHz, Adaptive deadband control, Internal digital soft start; Vcc under voltage lockout and shutdown capability via comp pin. FEATURES n n n Bus voltage operation from 9V to 24V 5V bias regulator available Excellent dynamic response with input voltage feed-forward and voltage mode control Programmable switching frequency up to 1MHz Internal Digital Soft Start Function Programmable hiccup current limit Shutdown by pulling COMP pin low NMOS LDO controller available Start into precharged output Pb-free and RoHS compliant n n n n n n n APPLICATIONS n n n Notebook PC Graphic Card on board converters On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V Set Top Box and LCD Display n TYPICAL APPLICATION DO3316P-102 MBR0530T1 1uF 8 VIN BST VIN1 +12V 2*16SVP330M 1 0.1uF 1ohm HDRV 2 Q1 0.75uH 9 SW 16 REGCS 10 13 +5V 10uF REGOUT VCC 1uF 5k 11 NX2710 OCP 12 3.3nF LDRV 4 GND Fb Comp VOUT1 +1.2V@25A 8.06k 2*(560uF,7mohm) 7.5k Q2 1.2k 3 14 2.5k 15 15nF 15k 680pF VIN2 +3.3V REGFB 1.65k LDO OUT 6 LDO FB 7 MTD3055 82pF 0 5 RT 5k 5k 150uF 18mohm VOUT2 +1.6V@2A Figure1 - Typical application of NX2710 ORDERING INFORMATION Device NX2710CSTR Rev. 1.3 08/07/07 Temperature 0 to 70o C Package SOIC -16L Frequency 300kHz to 1MHz Pb-Free Yes 1 NX2710 ABSOLUTE MAXIMUM RATINGS VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V VIN to GND .......................................................... -0.3V to 25V BST, HDRV, REGCS to GND Voltage .................. -0.3V to 35V SW to GND ......................................................... -2V to 35V REGOUT to GND ................................................. 0.2 to 16V All other pins ....................................................... -0.3V to 6.5V Storage Temperature Range ................................. -65oC to 150oC Operating Junction Temperature Range ................ -40oC to 125oC ESD Susceptibility .............................................. 2kV CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION 16-LEAD PLASTIC SOIC θ JA ≈ 83o C/W BST HDRV GND LDRV RT LDO-OUT LDO-FB VIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SW COMP FB VCC OCP REGSEN REGOUT REGCS ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc =5V, VIN=12V and TA = 0 to 70oC. Typical values refer to TA = 25oC. PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range Operating quiescent current Vcc UVLO VCC-Threshold VCC-Hysteresis Supply Voltage(Vin) Vin Voltage Range Input Voltage Current Rev. 1.3 08/07/07 SYM Test Condition Min VREF VCC IQ TYP MAX 0.8 0.2 4.75 switching is off 3 VCC_UVLO VCC Rising VCC_Hyst VCC Falling Vin V % 5.25 5 4.4 0.2 9 Vin=24V 9 Units V mA V V 25 10 V mA 2 NX2710 PARAMETER Vin UVLO Vin-Threshold Vin-Hysteresis Oscillator (Rt) Frequency Frequency Over Vin Ramp-Amplitude Voltage Ramp Offset Ramp/Vin Gain Max Duty Cycle Min on time Error Amplifiers Transconductance Input Bias Current Comp SD threshold Vref and Soft Start Soft Start time High Side Driver (CL=3300pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time SYM Test Condition Min TYP MAX Units Vin_UVLO Vin_Hyst Vin Rising Vin Falling 8.8 0.8 V V FS RT=open 300 KHz % V V V/V % nS -5 VRAMP Vin=20V 5 2 0.8 0.1 90 150 2500 0.3 umho nA V 6.8 mS Ib Tss 100 Fs=300kHz Rsource(Hdrv) I=200mA 1 ohm Rsink(Hdrv) I=200mA 0.8 ohm THdrv(Rise) 10% to 90% THdrv(Fall) 90% to 10% Tdead(L to Ldrv going Low to Hdrv going H) High, 10% to 10% 50 50 30 ns ns ns Rsource(Ldrv) I=200mA 1 ohm Rsink(Ldrv) I=200mA 0.5 ohm 50 50 30 ns ns ns 32 uA Low NSide Driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rise Time Fall Time Deadband Time OCP Adjust OCP current setting FBUVLO Feedback UVLO threshold Over temperature Threshold Hysteresis Rev. 1.3 08/07/07 TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10% percent of nominal 65 70 150 20 75 % °C °C 3 NX2710 PARAMETER LDO Controller FB Pin- Bias Current LDO FB Voltage LDO FB UVLO High Output Voltage Low Output Voltage High Output Source Current 5V AUX REG Current limit threshold FB Pin- Bias Current RegFb Voltage Regout Output Voltage High SYM Test Condition LDO_OUT=LDO_FB percent of nominal VIN=12V, LDO_FB=0.7V IO_SOURCE=1.4mA Min TYP 65 0.8 70 10.2 VIN=12V, LDO_FB=0.9V IO_SINK=1.4mA Regout=RegFb VIN=12V, RegFb=1.1V IO_SOURCE=1.4mA Regout Output Voltage Low VIN=12V, IO_SINK=1.4mA Open Loop Gain GBNT(Note1) RegFb=1.4V 50 MAX Units 100 nA V % V 75 0.2 V 3 mA 100 0 1.25 11 mV uA V V 0.2 V DB Note 1: This parameter is guaranteed by design but not tested in production(GBNT). Rev. 1.3 08/07/07 4 NX2710 PIN DESCRIPTIONS PIN SYMBOL PIN DESCRIPTION VCC This pin supplies the internal 5V bias circuit. . A high freq 1uF ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. BST This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF ceramic capacitor is placed as close as possible to and connected to this pin and SW pin. GND Power ground. FB This pin is the error amplifiers inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage. COMP This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. SW HDRV LDRV VIN This pin is connected to source of high side FETs and provide return path for the high side driver. High side gate driver output. Low side gate driver output. Bus voltage input provides power supply to oscillator, VIN UVLO signal and 5V regulator controller. RT LDO FB LDO OUT REGCS REGOUT REGSEN OCP Rev. 1.3 08/07/07 Oscillator's frequency can be set by using an external resistor from this pin to GND. LDO controller feedback input. If the LDOFB pin is pulled below 0.7*Vref, an internal comparator after certain delay and pulls down LDOOUT pin and initiates the HICCUP circuitry. LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The maximum rating of this pin is 16V. This pin is 5V regulator current limit pin. It compares the voltage drop on the resistor which is connected between Vin and REGCS pin with internal offset 100mV. 1ohm resistor sets the current limit 100mA. The output of the 5V regulator controller that drives a low current low cost external bipolar transistor or an external MOSFET to regulate the voltage at Vcc pin derived from bus voltage. This eliminates an otherwise external regulator needed in applications where 5V is not available. Feedback pin of the 5V regulator controller. A resistor divider is connected from the output of the 5V regulator to this pin to complete the loop. This pin is connected to the drain of the external low side MOSFET and is the input of the over current protection(OCP) comparator. An internal current source is flown to the external resistor which sets the OCP voltage across the Rdson of the low side MOSFET. Current limit point is this voltage divided by the Rds-on. 5 NX2710 BLOCK DIAGRAM RegCs VIN Regout + Ref 100mV Regsen 4.4/4.2 Bias 1.25V Generator 0.8V VCC EN POR BST START 6/5.75 three cycle delay COMP 0.3V START Digital start Up START Reset dominant Hiccup START R S DrvH Q FET Drivers VIN SS_1/4_done OSC Dis_EA DRVL S R Vp Vp Disable SS_done Q POR Hiccup FB VCC HDin SS_half_done RT SW LDIN HDIN 70%*Vp 3 cycle filter FB 3 cycle filter R Hiccup logic 0.6V CLAMP OCP 32uA LDIN START COMP VCC Dis_EA GND EN 0.6V SS_1/4_done 70%*Vp 3 cycle filter VpLDO Vp LDO_out LDO_FB Figure 2 - Simplified block diagram of the NX2710 Rev. 1.3 08/07/07 6 NX2710 DO3316P-102 2* 10uF MBR0530T1 8 VIN 1uF BST VIN1 +12V 16MV1500WG 1 0.1uF 1ohm HDRV 2 Q1 0.75uH 9 SW 16 REGCS 5k 2N3904 +5V 1uF 10 10 13 REGOUT VCC 1uF 5k 11 NX2710 OCP 12 3.3nF LDRV 4 GND Fb Comp VOUT1 +1.2V@25A 6k 2*(560uF,7mohm) 7.5k Q2 1.2k 3 14 15 2.5k 15nF 15k 680pF VIN2 +3.3V REGFB 100uF 1.65k 5 RT LDO OUT 6 LDO FB 7 MTD3055 150pF 470 1k 220uF 39mohm VOUT2 +2.5V@2A Figure 3 - Simplified Demo board schematic Rev. 1.3 08/07/07 7 NX2710 BUS R23 12V 1 0 C25 C21 0.1u 1u D1 MBR0530T1 C12 8 R22 0 REG_CS BST C9 1 HDRV 2 HDRV R34 op UG1 M1 GND1 C2 0.1u REG_SENSE SW 5V GND5 GND2 GND6 PWR_OK -5V 5VSB 5V2 12V1 5V3 NTD70N03R R13 2 GND2 16 12 NTD70N03R M2 UG2 D5 op 18 19 5V 20 5V JVOUT 1 R4 R15 MTD3055 D3 D4 L2 VOUT VOUT 2 C14 OP C15 C19 R18 1k GNDOUT LG1 M3 NTD110N02R 4 LG2 M4 R17 NTD110N02R 10 0 VDD R16 LG3 M5 NTD110N02R 0 C13 470p LDO_OUT M11 UG1 4 LDO_OUT op LD R V 1 LDRV 6 4SEPC560MX 4SEPC560MX op 0 C1 1u M7 2 PG0077.801 D2 R14 0.1u L1 1 SW 6k 3 12V 12V2 ATX-12V 17 op VCC NX2710 3 13 OCP 4 12V 12V1 C17 16 LDO_IN M12 UG2 4 15n 2.5k 1 2 3 R19 C16 1.2k 3.3n SW R21 15k op C5 680p R2 M13 LG1 4 op R3 open 3 R30 op COMP C4 8 7 6 5 9 RT 15 op 5 LDO_FB SW 7.5k 8 7 6 5 9 R32 474 R20 14 C3 op GND C24 FB 8 7 6 5 9 C8 150p 2 3 4 5 R33 1k 1 2 3 R31 0 7 0.1u 15 GND1 ATX con 0 1 10 GNDLDO 1 1k 8 7 6 5 9 R28 1.65k LDO_OUT panasonic FM 220uF JLDO C23 1 14 GND4 MH1 PS_ON J2 R5 8 7 6 5 9 11 R1 VOUT 10u 5V1 13 SW R27 C22 100u 9 GND3 0 5k 2 8 C10 -12V GND 5 4 3 2 REG_OUT R12 C7 op JP1 6 3.3V2 3.3V 12 MH2 10 R26 op 3.3V 5V 12V 10 4.99k C26 1u 5 C11 7 10u R25 VCC 4 open Q1 MBR3904 M6 op 5V 16MV1500WG V IN 9 2 VDD op U1 3 11 3.3V MH1 VCC 3.3V1 MH2 C20 R29 1 3.3V 2 MH2 3.3V 1 L3 DO3316H-102 MH2 1 GND 1 MH1 J1 0 C18 47u MH1 R24 M14 LG2 4 M15 LG3 4 1 2 3 1 2 3 Title 1 2 3 C6 open NX2710 HC APPLICATION Size Document Number Rev 2710-SO-02A Date: Thursday , September 14, 2006 A Sheet 1 of 1 Figure 4 - Demo board schematic based on ORCAD Rev. 1.3 08/07/07 8 NX2710 Bill of Materials Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Rev. 1.3 08/07/07 Quantity 3 4 1 1 1 2 1 1 2 1 1 1 1 1 1 1 2 3 1 1 2 1 1 3 9 1 1 1 1 1 1 1 1 1 Reference C1,C21,C26 C2,C17,C24,C25 C4 C5 C8 C9,C10 C11 C13 C14,C15 C16 C18 C22 C23 D1 L1 L3 M1,M2 M3,M4,M5 M7 Q1 R1,R17 R2 R4 R5,R18,R33 R12,R13,R14,R15,R16,R22, R23,R24,R31 R19 R20 R21 R25 R27 R28 R29 R32 U1 Part 1u 0.1u 15n 680p 150p 10u 16MV1500WG 470p 4SEPC560MX 3.3n 47u 100u panasonic FM 220uF MBR0530T1 PG0077.801 DO3316H-102 NTD70N03R NTD110N02R MTD3055 MBR3904 10 2.5k 6k 1k 0 1.2k 7.5k 15k 4.99k 5k 1.65k 1 474 NX2710 9 NX2710 Demoboard waveforms Figure 5 - Output ripple Figure 7 - Transient response @ LDO Figure 9 - 1.2V over current proteciton Rev. 1.3 08/07/07 Figure 6 - Transient response @ 1.2 output Figure 8 - Soft start Figure 10 - LDO over current protection 10 NX2710 APPLICATION INFORMATION IRIPPLE = Symbol Used In Application Information: VIN = - Input voltage VOUT - Output voltage IOUT - Output current VIN -VOUT VOUT 1 × × LOUT VIN FS ...(2) 12V-1.2V 1.2V 1 × × = 4.8A 0.75uH 12V 300kHz Output Capacitor Selection DVRIPPLE - Output voltage ripple Output capacitor is basically decided by the FS - Switching frequency amount of the output voltage ripple allowed during DIRIPPLE - Inductor current ripple steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load Design Example Power stage design requirements: VIN=12V condition is determined by equation(3). VOUT=1.2V IOUT =25A ∆VRIPPLE = ESR × ∆IRIPPLE + DVRIPPLE <=20mV DVTRAN<=60mV @ 10A step ∆IRIPPLE 8 × FS × COUT ...(3) Where ESR is the output capacitors' equivalent FS=300kHz series resistance,COUT is the value of output capacitors. Typically when large value capacitors are selected Output Inductor Selection The selection of inductor value is based on in- such as Aluminum Electrolytic,POSCAP and OSCON ductor ripple current, power rating, working frequency types are used, the amount of the output voltage ripple and efficiency. Larger inductor value normally means is dominated by the first term in equation(3) and the smaller ripple current. However if the inductance is second term can be neglected. chosen too large, it brings slow response and lower For this example, OSCON are chosen as output efficiency. Usually the ripple current ranges from 20% capacitors, the ESR and inductor current typically de- to 40% of the output current. This is a design freedom termines the output voltage ripple. which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations: V -V V 1 L OUT = IN OUT × OUT × IRIPPLE VIN FS IRIPPLE =k × IOUTPUT ESR desire = ∆VRIPPLE 15mV = = 4.2m Ω ∆IRIPPLE 4.8A If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capaci- ...(1) tor. For example, for 15mV output ripple, OSCON 4SEPC560MX with 7mΩ are chosen. E S R E × ∆ IR I P P L E ∆ VR IPPLE where k is between 0.2 to 0.4. Select k=0.2, then N = 12V-1.2V 1.2V 1 × × 0.2 × 25A 12V 300kHz LOUT =0.72uH Number of Capacitor is calculated as LOUT = Choose LOUT=0.75uH, then Pulse inductor PG0077.801 is a good choice. Current Ripple is calculated as Rev. 1.3 08/07/07 ...(4) N= ...(5) 7m Ω × 4.8A 20mV N =1.68 The number of capacitor has to be round up to a integer. Choose N =2. 11 NX2710 If ceramic capacitors are chosen as output ca- output inductor is smaller than the critical inductance, pacitors, both terms in equation (3) need to be evalu- the voltage droop or overshoot is only dependent on ated to determine the overall ripple. Usually when this the ESR of output capacitor. type of capacitors are selected, the amount of capaci- pacitor such as electrolytic capacitor, the product of tance per single unit is not sufficient to meet the tran- ESR and capacitance is high and L ≤ L crit is true. In sient specification, which results in parallel configura- that case, the transient spec is mostly like to depen- tion of multiple capacitors. capacitor output ripple is : dent on the ESR of capacitor. The amount of ceramic ∆VRIPPLE = ESR × ∆IRIPPLE ∆IRIPPLE + 8 × 300kHz × COUT Using the above equations, although DC ripple spec can be met, however it needs to be studied for transient requirement. For low frequency ca- Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following N= ESR E × ∆Istep ∆Vtran + VOUT × τ2 2 × L × C E × ∆Vtran ...(9) where Based On Transient Requirement Typically, the output voltage droop during transient is specified as ∆V droop < ∆V tran @step load DISTEP 0 if L ≤ L crit τ = L × ∆Istep − ESR E × CE V OUT if L ≥ L crit ...(10) During the transient, the voltage droop during the transient is composed of two sections. One sec- For example, assume voltage droop during tran- tion is dependent on the ESR of capacitor, the other sient is 60mV for 10A load step. section is If the OSCON 4SEPC560MX(560uF, 7mohm ESR) is used, the crticial inductance is given as a function of the inductor, output capacitance as well as input, output voltage. For example, for the L crit = overshoot when load from high load to light load with a DISTEP transient load, if assuming the band- 7mΩ × 560µF ×1.2V = 0.94µH 5A width of system is high enough, the overshoot can be estimated as the following equation. ∆Vovershoot where VOUT = ESR × ∆Istep + × τ2 2 × L × COUT ...(6) τ is the a function of capacitor,etc. 0 if L ≤ L crit τ = L × ∆Istep − ESR × COUT V OUT L ≥ L crit ...(7) where L crit = The selected inductor is 0.75uH which is smaller than critical inductance. In that case, the output voltage transient mainly dependent on the ESR. number of capacitor is N= if ESR × COUT × VOUT ESR E × C E × VOUT = ...(8) ∆Istep ∆I step where ESRE and CE represents ESR and capaci- ESR E × C E × VOUT = ∆Istep ESR E × ∆Istep ∆Vtran 7mΩ × 5A 60mV = 1.296 The number of capacitors has to satisfied both ripple and transient requirement. Overall, we choose N=2. = tance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected Rev. 1.3 08/07/07 12 NX2710 It should be considered that the proposed equa- following figures and equations show how to realize tion is based on ideal case, in reality, the droop or over- the type III compensator by transconductance ampli- shoot is typically more than the calculation. The equa- fier. tion gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic param- Compensator Design 1 2 × π × (R 2 + R3 ) × C3 ...(12) FP1 = 1 2 × π × R3 × C3 ...(13) 1 2 × π × R4 × ...(14) C1 × C2 C1 + C2 The transfer function of type III compensator for transconductance amplifier is given by: Ve 1 − gm × Z f = VOUT 1 + gm × Zin + Z in / R1 sponse, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, frequency between 1/10 and 1/5 of the switching fre- FZ2 = the compensator. shift , and therefore, is unstable by itself. In order to the Bode plot of the closed loop system has crossover ...(11) where FZ1,FZ2,FP1 and FP2 are poles and zeros in Due to the double pole generated by LC filter of achieve accurate output voltage and fast transient re- 1 2 × π × R 4 × C2 FP2 = eters. the power stage, the power system has 180o phase FZ1 = For the voltage amplifier, the transfer function of compensator is quency, phase margin greater than 50o and the gain capacitors usually decide the compensator type. If Ve −Z f = VOUT Zin electrolytic capacitors are chosen as output capacitors, To achieve the same effect as voltage amplifier, type II compensator can be used to compensate the the compensator of transconductance amplifier must system, because the zero caused by output capacitor satisfy this condition: R4>>2/gm. And it would be de- ESR is lower than crossover frequency. Otherwise type sirable if R1||R2||R3>>1/gm can be met at the same III compensator should be chosen. time, crossing 0dB with -20dB/decade. Power stage output Voltage feedforward compensation is used in NX2710 to compensate the output voltage variation caused by input voltage changing. The feedforward Zin Zf C1 Vout funtion is realized by using VIN pin voltage to program the oscillator ramp voltage VOSC=0.1VIN, which pro- R3 R2 vides nearly constant power stage gain under wide voltage input range. A. Type III compensator design For low ESR output capacitors, typically such as C3 C2 R4 Fb gm Ve R1 Vref Sanyo oscap and poscap, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The Rev. 1.3 08/07/07 Figure 11 - Type III compensator using transconductance amplifier 13 NX2710 Case 1: FLC<FO<FESR(for most ceramic or low ESR POSCAP, OSCON) 3. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11). 1 2 × π × FZ1 × R 4 Gain(db) C2 = 1 2 × π × 0.75 × 5.5kHz × 2.5k Ω = 15nF = power stage FLC 40dB/decade loop gain FESR Choose C2=15nF. 4. Calculate C1 by equation (14) with pole Fp2 at one third of the switching frequency. 1 2 × π × R 4 × FP2 C1 ≈ 1 × π × 2 2.5k Ω × 100kHz ≈ 639pF ≈ 20dB/decade compensator Choose C1=680pF. 5. Calculate C3 with the crossover frequency FO at 15kHz. FZ1 FZ2 FO FP1 FP2 C3 = Figure 12 - Bode plot of Type III compensator (FLC<FO<FESR) Typical design example of type III compensator in which the crossover frequency is selected as FLC<FO<FESR and FO<=1/10Fs is shown as the following steps. 1. Calculate the location of LC double pole FLC and ESR zero FESR. FLC = = 1 2 × π × 15kHz × 0.75uH × 1120uF × 10 2.5kΩ =3.2nF = Choose C3=3.3nF. 6. Calculate R3 by equation (13) with Fp1 =FESR. R3 = 1 2 × π × FP1 × C3 1 2 × π × 40.6kHz × 3.3nF = 1.18kΩ = Choose R3 =1.2kΩ. 1 2 × π × LOUT × COUT 1 2 × π × 0.75uH × 1120uF = 5.5kHz FESR = VOSC 2 × π × FO × L × COUT × VIN R4 1 2 × π × ESR × COUT 1 2 × π × 3.5mΩ × 1120uF = 40.6kHz = 7. Calculate R2 by setting compensator zero FZ2 at the LC double pole. R2 = 1 1 1 ×( − ) 2 × π × C3 FZ2 FP1 1 1 1 ×( − ) 2 × π × 3.3nF 5.5kHz 40.6kHz = 7.6k Ω = Choose R2 =7.5kΩ. 8. Calculate R1 . 2. Set R4 equal to 2.5kΩ. Rev. 1.3 08/07/07 14 NX2710 R1 = R 2 × VREF 7.5k Ω × 0.8V = = 15k Ω VOUT -VREF 1.2V-0.8V FLC = Choose R 1=15kΩ. Case 2: 2 × π × LOUT × COUT 1 = 2 × π × 2.2uH × 2000uF = 2.4kHz FLC<FESR<FO(for electrolytic capacitors) FESR = Gain(db) 1 power stage 1 2 × π × ESR × COUT 1 2 × π × 9m Ω × 2000uF = 8.8kHz = FLC 40dB/decade 2. Set R4 equal to 2.5kΩ. FESR 3. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11). loop gain C2 = 20dB/decade 1 2 × π × FZ1 × R 4 1 2 × π × 0.75 × 2.4kHz × 2.5k Ω = 35nF = compensator Choose C2=33nF. 4. Calculate C1 by equation (14) with pole Fp2 at one third of the switching frequency. FZ1 FZ2 FP1 FO FP2 C1 ≈ 1 2 × π × R 4 × FP2 1 2 × π × 2.5k Ω × 66.7kHz ≈ 959pF ≈ Figure 13 - Bode plot of Type III compensator (FLC<FESR<FO) Choose C1=1nF. If electrolytic capacitors are used as output capacitors, typical design example of type III compensator in which the crossover frequency is selected as FLC<FESR<FO and FO<=1/10Fs is shown as the following steps. Here two SANYO MV-WF1000 with 18 mΩ is chosen as output capacitor, output inductor is 2.2uH, output voltage is 1.2V, switching frequency is 200kHz. 1. Calculate the location of LC double pole FLC and ESR zero FESR. Rev. 1.3 08/07/07 5. Calculate R3 with the crossover frequency FO at 15kHz. R3 = VIN ESR × R 4 × VOSC 2 × π × FO × L 9mohm × 2.5kΩ 2 × π × 15kHz × 1uH =1.08kΩ =10 × Choose R3=1.2kΩ. 6. Calculate C3 by equation (13) with Fp1 =FESR. 15 NX2710 1 2 × π × FP1 × R3 power stage Gain(db) C3 = 1 2 × π × 8.8kHz × 1.2k Ω = 14nF = 40dB/decade loop gain Choose C3 =15nF. 20dB/decade 7. Calculate R2 by setting compensator zero FZ2 at the LC double pole. 1 1 1 ×( − ) 2 × π × C3 FZ2 FP1 R2 = compensator Gain 1 1 1 ×( − ) 2 × π × 15nF 2.4kHz 8.8kHz = 3.2k Ω = FZ FLC FESR FO FP Choose R2 =4kΩ. 8. Calculate R1 R1 = . R 2 × VREF 7.5k Ω × 0.8V = = 15k Ω VOUT -VREF 1.2V-0.8V Choose R 1=15kΩ. Figure 14 - Bode plot of Type II compensator Vout B. Type II compensator design R2 Fb If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensa- Ve gm R1 R3 Vref tor can be used to compensate the system. C2 For this type of compensator, FO need to C1 satisfy FLC<FESR<<FO<=1/10Fs. Type II compensator can also be realized by simple RC circuit without feedback as shown in the following figure. R3 and C1 introduce a zero to cancel Figure 15 - Type II compensator with the double pole effect. C2 introduces a pole to sup- transconductance amplifier press the switching noise. The following equations show the compensator pole zero location and constant gain. Gain=gm × Fz = R1 × R3 R1 +R 2 1 2 × π × R3 × C1 Fp ≈ 1 2 × π × R 3 × C2 The following is parameters for type II compensator design. Input voltage is 12V, output voltage is ... (15) 2.5V, output inductor is 2.2uH, output capacitors are two 680uF with 41m Ω electrolytic capacitors. ... (16) 1.Calculate the location of LC double pole FLC and ESR zero FESR. ... (17) FLC = = 1 2 × π × L OUT × COUT 1 2 × π × 2.2uH × 1360uF = 2.9kHz Rev. 1.3 08/07/07 16 NX2710 FESR = 1 2 × π × ESR × COUT 1 2 × π × 20.5m Ω × 1360uF = 5.7kHz The following equation applies to figure16, which shows the relationship between VOUT , VREF and volt- age divider. = 2.Set R2 equal to10kΩ. Using equation 18, the final selection of R1 is 4.7kΩ. Vout R2 Fb 3. Set crossover frequency at 1/10 of the swithing frequency, here FO=30kHz. 4.Calculate R3 value by the following equation. R3 = R1 Vref VOSC 2 × π × FO × L 1 VOUT × × × Vin RESR gm VREF 2 × π × 30kHz × 2.2uH 1 × 20.5m Ω 2.5mA/V 2.5V × 0.8V =2.53kΩ =0.1× Choose R3 =2.55kΩ. Figure 16 - Voltage Divider R 1= R 2 × VR E F V O U T -V R E F ...(18) where R2 is part of the compensator, and the value of R1 value can be set by voltage divider. 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole. 1 C1 = 2 × π × R3 × Fz 1 2 × π × 2.55kΩ × 0.75 × 2.9kHz =28nF = Choose C1=27nF. 6. Calculate C2 by setting compensator pole Fp at half the swithing frequency. C2= 1 π × R 3 × Fs 1 = π × 2 .55k Ω × 300kH z =207pF Choose C2=220pF. Input Capacitor Selection Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as: IRMS = IOUT × D × 1- D D= VOUT VIN ...(19) VIN = 12V, VOUT=1.2V, IOUT=25A, the result of input RMS current is 7.5A. Output Voltage Calculation Output voltage is set by reference voltage and For higher efficiency, low ESR capacitors are recommended. Two Sanyo OS-CON 16SVP330M external voltage divider. The reference voltage is fixed 16V 330uF 16m Ω with 4.72A RMS rating are chosen at 0.8V. The divider consists of two ratioed resistors as input capacitors. so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value. Rev. 1.3 08/07/07 17 NX2710 charge,VHGS is the high side gate source voltage, and Power MOSFETs Selection The NX2710 requires at least two N-Channel power MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter efficiency. In 25A output application, five IRFR3706 can be used, two for high side, three for low side. They have the following parameters: VDS=30V, ID =75A,RDSON =9mΩ,QGATE =23nC. There are two factors causing the MOSFET power loss:conduction loss, switching loss. Over current protection is achieved by sensing current through the low side MOSFET. An internal current source of 32uA flows through an external resistor connected from OCP pin to SW node sets the over current protection threshold. When synchronous FET is on, the voltage at node SW is given as VSW =-IL × RDSON IOCP × ROCP +VSW PHCON =IOUT 2 × D × RDS(ON) × K PTOTAL =PHCON + PLCON Over Current Limit Protection The voltage at pin OCP is given as Conduction loss is simply defined as: PLCON =IOUT 2 × (1 − D) × RDS(ON) × K VLGS is the low side gate source voltage. This power dissipation should not exceed maximum power dissipation of the driver device. When the voltage is below zero, the over current ...(20) occurss as shown in figure 17. vbus where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature I OCP 32uA dependency. As a result, RDS(ON) should be selected for the worst case, in which K approximately equals to duction loss should not exceed package rating or overall SW R OCP o 1.4 at 125 C according to IRFR3706 datasheet. Con- OCP OCP comparator system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated. The over current limit can be set by the following equation: 1 × VIN × IOUT × TSW × FS ...(21) 2 where IOUT is output current, TSW is the sum of TR and TF which can be found in mosfet datasheet, and FS is switching frequency. Swithing loss PSW is frequency dependent. Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET. MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.It is proportional to frequency and is defined as: PSW = Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS Figure 17 - Over Current Protection ...(22) where QHGATE is the high side MOSFETs gate ISET = IOCP × ROCP K × RDSON If two MOSFETs RDSON=6.5mΩ, the worst case thermal consideration K=1.5 and the current limit is set at 40A, then R OCP = ISET × K × R DSON 40A × 1.5 × 6.5m Ω = = 6.1kΩ IOCP 32uA × 2 Choose ROCP=6kΩ. For NX2710, if switching channel goes into hiccup current limit, the LDO will go to hiccup too. LDO Selection Guide NX2710 offers a LDO controller. The selection of MOSFET to meet LDO is more straight forward. The selection is that the Rdson of MOSFET should charge,Q LGATE is the low side MOSFETs gate Rev. 1.3 08/07/07 18 NX2710 meet the dropout requirement. For example. gm is the forward trans-conductance of MOSFET. VLDOIN =3.3V For IRF3706, gm=53. VLDOOUT =2.5V Select Rf1=5kohm. ILoad =2A Output capacitor is Sanyo POSCAP 4TPE150M The maximum Rdson of MOSFET should be R RDSON = (VLDOIN − VLDOOUT ) × I LOAD with 150uF, ESR=25mohm. CC = = (3.3V − 2.5V) / 2A = 0.4Ω 1 53 × 25m Ω × =91pF 4 × π × 100kHz × 5k Ω 1+53 × 25m Ω Most of MOSFETs can meet the requirement. Moreimportant is that MOSFET has to be selected right package to handle the thermal capability. For LDO, Choose CC=100pF. For electrolytic or POSCAP, RC is typically selected to be zero. Rf2 is determined by the desired output voltage. maximum power dissipation is given as PLOSS = (VLDOIN − VLDOOUT ) × I LOAD R f2 = = (3.3V − 2.5V) × 2A = 1.6W Select IR MOSFET IRFR3706 with 9mΩ RDSON is sufficient. R f1 × VREF VLDOOUT − VREF 5kΩ × 0.8V 1.6V − 0.8V =5kΩ = Choose Rf2=5kΩ. When ceramic capacitors or some low ESR bulk LDO Compensation The diagram of LDO controller including VCC capacitors are chosen as LDO output capacitors, the zero caused by output capacitor ESR is so high that regulator is shown in the following figure. crossover frequency FO has to be chosen much higher than zero caused by RC and CC and much lower than + LDO input zero caused by ESR . For example, 10uF ceramic is Vref used as output capacitor. We select Fo=100kHz, Rf1 ESR Rf2 Rc Rf1=5kohm and select Rload MOSFET MTD3055(gm=5S). RC and CC can be calculated as follows. Cc Co RC =R f1 × 2 × π × FO × CO 0.5 × gm 2 × π × 100kHz × 10uF 0.5 × 5S =12.56kΩ =5kΩ × Figure 18 - NX2710 LDO controller. For most low frequency capacitor such as electrolytic, POSCAP, OSCON, etc, the compensation parameter can be calculated as follows. g × ESR 1 CC = × m 4 × π × FO × R f1 1+gm × ESR where FO is the desired crossover frequency. Typically, in this LDO compensation, crossover Choose RC=12.7kΩ. CC = 10 × CO RC × gm 10 × 10uF 12.7kΩ × 5S =1.6nF = Choose CC=1.5nF. frequency FO has to be higher than zero caused by ESR. FO is typically around several tens kHz to a few hundred kHz. For this example, we select Fo=100kHz. Rev. 1.3 08/07/07 19 NX2710 enough. This is very important. The same applies to Current Limit for LDO Current limit of LDO is achieved by sensing the LDO feedback voltage. When LDO_FB pin is below 70% of VREF, the IC goes into hiccup mode. The IC will turn off all the channel for 4096 cycles and start to restart system again. the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. There are two sets of components considered in the layout which are power components and small signal components. Power components usually consist of input capacitors, high-side MOSFET, low-side MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input loop that does not interfere with the more sensitive analog control function. capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to the high switching currents through them. 2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic cap which usually is 1uF need to be practi- cally touching the drain pin of the upper MOSFET, a plane connection is a must. 3. The output capacitors should be placed as close as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not Rev. 1.3 08/07/07 20 NX2710 SOIC16 PACKAGE OUTLINE DIMENSIONS Rev. 1.3 08/07/07 21 NX2710 Rev. 1.3 08/07/07 22 NX2710 Customer Service NEXSEM Inc. 500 Wald Irvine, CA 92618 U.S.A. Tel: (949)453-0714 Fax: (949)453-0713 WWW.NEXSEM.COM Rev. 1.3 08/07/07 23