EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT GENERAL DESCRIPTION EM73963A is an advanced single chip CMOS 4-bit micro-controller. It contains 16K-byte ROM, 372-nibble RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function. EM73963A also equipped with 5 interrupt sources, 3 I/O ports (including 1 input port and 2 bidirection ports), LCD display (40x8), built-in sound generator. It's low power consumption and high speedfeature are further strengten with DUAL, SLOW, IDLE and STOP operation mode for optimized power saving. FEATURES Operation voltage Clock source : 2.4V to 5.5V. : Dual clock system. Low-frequency oscillator is Crystal or RC oscillator (32KHz, connect a external resistor) by mask option and high-frequency oscillator is RC oscillator (connect a external resistor and a capacitor). External clock and internal clock is available by mask option. Oscillation frequency : 480K, 1M, 2M and 4M Hz are both available for high frequency clock by mask option. Instruction set : 107 powerful instructions. Instruction cycle time : Up to 2 µs for 4 MHz (high speed clock). 244 µs for 32768 Hz (low speed clock). ROM capacity : 16K X 8 bits. RAM capacity : 372 X 4 bits. Input port : 1 port (P0.0-P0.3), IDLE/STOP releasing function is available by mask option.(each input pin has a pull-up and pull-down resistor available by mask option). Bidirection port : 2 ports (P4, P8). P4.0 and SOUND are available by mask option. IDLE/STOP release function for P8(0..3) is available by mask option. 12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse width measurement mode. Built-in time base counter : 22 stages. Subroutine nesting : Up to 13 levels. Interrupt : External . . . . . 2 input interrupt sources. Internal . . . . . . 2 Timer overflow interrupts. 1 Time base interrupt. LCD driver : 40 X 8 dots, 1/8 duty, 1/5 bias. Sound effect : Tone generator, random generator and volume control. Power saving function :SLOW, IDLE, STOP operation modes. Package type : Chip form 69 pins. * This specification are subject to be changed without notice. 6.14.2001 1 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT FUNCTION BLOCK DIAGRAM CLK LXIN LXOUT RESET Reset Control Clock Generator Clock Mode Control Timing Generator System Control Data pointer Time Base ROM Timer/Counter (TA,TB) Stack pointer ACC Data Bus Interrupt Control Instruction Decoder Instruction Register Stack ALU RAM Flag Z C PC S HR LR P0.0/WAKEUP0 P0.1/WAKEUP1 P0.2/WAKEUP2 P0.3/WAKEUP3 I/O Control V1~V4 LCD Driver P4.0/SOUND P8.0(INT1)/WAKEUPA P8.1(TRGB)/WAKEUPB P8.2(INT0)/WAKEUPC P8.3(TRGA)/WAKEUPD SOUND SEG0~SEG39 COM0~COM7 SOUND GEN. PIN DESCRIPTIONS Symbol Pin-type Function VDD VSS RESET Power supply (+) Power supply (-) RESET-A System reset input signal, low active mask option : none pull-up CLK OSC-C RC or external clock source connecting pin for high speed clock source. LXIN OSC-B/OSC-F Crystal/RC connecting pin for low speed clock source. LXOUT OSC-B/OSC-F Crystal/RC connecting pin for low speed clock source. P0(0..3)/WAKEUP0..3 INPUT-B 4-bit input port with IDLE/STOP releasing function mask option : wakeup enable, pull-up wakeup enable, none wakeup disable, pull-up wakeup disable, pull-down wakeup disable, none P4.0/SOUND I/O-O 1-bit bidirection I/O port or inverse sound effect output mask option : SOUND enable, push-pull, high current PMOS SOUND disable, open-drain SOUND disable, push-pull, high current PMOS SOUND disable, push-pull, low current PMOS P8.0(INT1)/WAKEUPA I/O-L 2-bit bidirection I/O port with external interrupt sources input and IDLE P8.2(INT0)/WAKEUPC /STOP releasing function mask option : wakeup enable, push-pull wakeup disable, push-pull wakeup disable, open-drain * This specification are subject to be changed without notice. 6.14.2001 2 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT Symbol Pin-type P8.1(TRGB)/WAKEUPB I/O-L P8.3(TRGA)/WAKEUPD SOUND V1, V2, V3, V4 COM0~COM7 SEG0~SEG39 TEST Function 2-bit bidirection I/O port with time/counter A,B external input and IDLE /STOP releasing function mask option : wakeup enable, push-pull wakeup disable, push-pull wakeup disable, open-drain Built-in sound effect output LCD bias voltage input LCD common output pins LCD segment output pins Tie VSS as package type, no connecting as COB type FUNCTION DESCRIPTIONS PROGRAM ROM ( 16K X 8 bits ) 16 K x 8 bits program ROM contains user's program and some fixed data. The basic structure of the program ROM may be categorized into 5 partitions. 1. Address 0000h: Reset start address. 2. Address 0002h - 000Ch : 5 kinds of interrupt service routine entry addresses. 3. Address 000Eh-0086h : SCALL subroutine entry address, only available at 000Eh,0016h,001Eh,0026h, 002Eh, 0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh,0086h. 4. Address 0000h - 07FFh : LCALL subroutine entry address. 5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program and data region. address Bank 0 : 0000h 0002h 0004h 0006h 0008h 000Ah 000Ch 000Eh 0086h Reset start address INT0; interrupt service routine entry address Reserved TRGA TRGB TBI INT1 Subroutine call entry address designated by [LCALL a] instruction SCALL, subroutine call entry address .... .. 07FFh 0800h 0FFFh 1000h Bank 1 1FFFh Data table for [LDAX],[LDAXI] instruction Bank 2 Bank 3 * This specification are subject to be changed without notice. 6.14.2001 3 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT User's program and fixed data are stored in the program ROM. User's program is executed using the PC value to fetch an instruction code. The 16Kx8 bits program ROM can be divided into 4 banks. There are 4Kx8 bits per bank. The program ROM bank is selected by P3(1..0). The program counter is a 13-bit binary counter. The PC and P3 are initialized to "0" during reset. When P3(1..0)=00B, the bank0 and bank1 of program ROM will be selected. P3(1..0)=01B, the bank0 and bank2 will be selected. Address 0000h : : 0FFFh 1000h : : 1FFFh P3=xx00B P3=xx01B P3=xx10B Bank0 Bank0 Bank0 Bank1 Bank2 Bank3 PROGRAM EXAMPLE: BANK 0 : : : LDIA #00H ; set program ROM to bank1 OUTA P3 B XA1 : XA : : : LDIA #01H ; set program ROM to bank2 OUTA P3 B XB1 : XB : : : LDIA #02H ; set program ROM to bank3 OUTA P3 B XC1 : XC : : : B XD XD : : : : ;--------------- -------------------- -------------------- -------------------- -BANK 1 XA1 : : : B XA : XA2 : : START: * This specification are subject to be changed without notice. 6.14.2001 4 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT B XA2 : ;--------------- -------------------- -------------------- -------------------- -BANK 2 XB1 : : : B XB : XB2 : : B XB2 : ;--------------- -------------------- -------------------- -------------------- -BANK 3 XC1 : : : B XC : XC2 : : B XC2 Fixed data can be read out by table-look-up instruction. Table-look-up instruction requires the Data point (DP) to indicate the ROM address in obtaining the ROM code data (Except bank 0) : LDAX LDAXI Acc ← ROM[DP]L Acc ← ROM[DP]H,DP+1 DP is a 12-bit data register that stores the program ROM address as pointer for the ROM code data. User has to initially load ROM address into DP with instructions "STADPL", and "STADPM, STADPH", then to obtain the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI" PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction. LDIA #07h; STADPL ; [DP]L ← 07h STADPM ; [DP]M ← 07h STADPH ; [DP]H ← 07h, Load DP=777h : OUT #00H , P3 ; Set in bank 1 LDL #00h; LDH #03h; LDAX ; ACC ← 6h STAMI ; RAM[30] ← 6h LDAXI ; ACC ← 5h STAM ; RAM[31] ← 5h ; ORG 1777h DATA 56h; DATA RAM (372-nibble ) A total 372 - nibble data RAM is available from address 000 to 17Fh Data RAM includes the zero page region, stacks and data area. * This specification are subject to be changed without notice. 6.14.2001 5 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT Increment Address Bank 0 Increment Zero-page 000h - 00Fh 010h - 01Fh 020h - 02Fh : : : 0C0h - 0CFh 0D0h - 0DFh 0E0h - 0EFh 0F0h - 0F3h Bank 1 Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 Level 9 Level 10 Level 11 Level 12 100h - 10Fh 110h - 11Fh : : : 160h - 16Fh 170h - 17Fh ZERO- PAGE: From 000h to 00Fh is the zero-page location. It is used as the zero-page address mode pointer for the instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y". PROGRAM EXAMPLE: To wirte immediate data "07h" to RAM [03] and to clear bit 2 of RAM [0Eh]. STD #07h, 03h ; RAM[03] ← 07h CLR 0Eh,2 ; RAM[0Eh]2 ← 0 STACK: There are 13 - level (maximum) stack levels that user can use for subroutine (including interrupt and CALL). User can assign any level be the starting stack by providing the level number to stack pointer (SP). When an instruction (CALL or interrupt) is invoked, before enter the subroutine, the previous PC address is saved into the stack. Until returned from those subroutines, the PC value is restored by the data saved in stack. DATA AREA: Except the area used by user's application, the whole RAM can be used as data area for storing and loading general data. ADDRESSING MODE The 372 nibble data memory consists of two banks (bank 0 and bank 1). There are 244x4 bits (address 000h~0F3h) in bank 0 and 128x4 bits (address 100h~17Fh) in bank 1. * This specification are subject to be changed without notice. 6.14.2001 6 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT The bank is selected by P9.3. When P9.3 is cleared to "0", the bank 0 is selected, when P9.3 is set to "1", the bank 1 is selected. The data Memory consists of three Address mode, namely (1) Indirect addressing mode: The address in the bank is specified by the HL registers. P9.3 HR LR RAM address PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h". SEP P9,3 LDL #3h LDH #4h LDAM CLP P9,3 LDL #2h LDH #3h STAM ; P9.3← 1 ; LR← 3 ; HR← 4 ; Acc← RAM[134h] ; P9.3← 0 ; LR← 2 ; HR← 3 ; RAM[023h]← Acc (2) Direct addressing mode: The address in the bank is directly specified by 8 bits of the second byte in the instruction field. instruction field xxxx xxxx P9.3 xxxx xxxx RAM address PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h". SEP P9,3 LDA 43h CLP P9,3 STA 23h ; P9.3← 1 ; Acc← RAM[143h] ; P9.3← 0 ; RAM[023h]← Acc (3) Zero-page addressing mode: The zero-page is in the bank 0 (address 000h~00Fh). The address is the lower 4 bits of the second byte in the instruction field. instruction field yyyy RAM address 0 0000 yyyy PROGRAM EXAMPLE: Write immediate "0Fh" to RAM address "005h". STD #0Fh, 05h ; RAM[05h]← 0Fh * This specification are subject to be changed without notice. 6.14.2001 7 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT PROGRAM COUNTER (16K ROM) Program counter ( PC ) is composed by a 13-bit counter, which indicates the next executed address for the program ROM instruction. For BRANCH and CALL instructions, PC is changed by instruction indicating. PC only can indicate the address from 0000h-1FFFh. The bank number is decided by P3. (1) Branch instruction: SBR a Object code: 00aa aaaa Condition: SF=1; PC ← PC 12-6.a ( branch condition satisified ) PC Hold original PC value+1 a a a a a a SF=0; PC← PC +1( branch condition not satisified) PC Original PC value + 1 LBR a Object code: 1100 aaaa aaaa aaaa Condition: SF=1; PC ← PC 12.a ( branch condition satisified ) PC Hold +2 a a a a a a a a a a a a SF=0; PC← PC +2( branch condition not satisified) PC Original PC value + 2 SLBR a Object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1FFFh) 0101 0111 1100 aaaa aaaa aaaa (a:0000h~0FFFh) Condition: SF=1; PC ← a ( branch condition satisified) PC a a a a a a a a a a a a a SF=0 ; PC ← PC + 3 ( branch condition not satisified ) PC Original PC value + 3 (2) Subroutine instruction: SCALL a Object code: 1110 nnnn Condition : PC ← a ; a=8n+6 ; n=1..Fh ; a=86h, n=0 PC 0 0 0 0 0 a a a a a LCALL a Object code: 0100 0aaa aaaa aaaa Condition: PC ← a * This specification are subject to be changed without notice. a a a 6.14.2001 8 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT PC 0 0 a a a a a a a a a a a RET Object code: 0100 1111 Condition: PC ← STACK[SP]; SP + 1 PC The return address stored in stack RT I Object code: 0100 1101 Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1 PC The return address stored in stack (3) Interrupt acceptance operation: When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into PC,The interrupt vectors are as follows : INT0 (External interrupt from P8.2) PC 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 TRGA (Timer A overflow interrupt) PC 0 0 0 0 0 TRGB (Time B overflow interrupt) PC 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 TBI (Time base interrupt) PC 0 0 0 INT1 (External interrupt from P8.0) PC 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 (4) Reset operation: PC 0 0 (5) Other operations: For 1-byte instruction execution: PC + 1 For 2-byte instruction execution: PC + 2 For 3-byte instruction execution: PC + 3 * This specification are subject to be changed without notice. 6.14.2001 9 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ACCUMULATOR Accumulator is a 4-bit data register for temporary data storage. For the arithematic, logic and comparative opertion .., ACC plays a role which holds the source data and result. FLAGS There are three kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), and SF ( Status flag ), these three 1-bit flags are included by the arithematic, logic and comparative .... operation. All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after RTI instruction is executed. (1) Carry Flag ( CF ) The carry flag is affected by the following operations : a. Addition : CF as a carry out indicator, under addition operation, when a carry-out occures, the CF is "1", likewise, if the operation has no carry-out, the CF is "0". b. Subtraction : CF as a borrow-in indicator, under subtraction operation, when a borrow occures, the CF is "0", likewise, if there is no borrow-in, the CF is "1". c. Comparision: CF as a borrow-in indicator for Comparision operation as the same as subtraction operation. d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation. e. CF test instruction : Under TFCFC instruction, the CF content is sent into SF then clear itself as "0". Under TTSFC instruction, the CF content is sent into SF then set itself as "1". (2) Zero Flag ( ZF ) ZF is affected by the result of ALU, if the ALU operation generates a "0" result, the ZF is "1", likewise, the ZF is "0". (3) Status Flag ( SF ) The SF is affected by instruction operation and system status. a. SF is initiated to "1" for reset condition. b. Branch instruction is decided by SF, when SF=1, branch condition is satisified, likewise, when SF=0, branch condition is unsatisified. PROGRAM EXAMPLE: Check following arithematic operation for CF, ZF, SF LDIA #00h; LDIA #03h; ADDA #05h; ADDA #0Dh; ADDA #0Eh; CF - ZF 1 0 0 0 0 * This specification are subject to be changed without notice. SF 1 1 1 0 0 6.14.2001 10 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ALU The arithematic operation of 4 - bit data is performed in ALU unit . There are 2 flags that can be affected by the result of ALU operation, ZF and SF. The operation of ALU is affected by CF only. ALU STRUCTURE ALU supported user arithematic operation functions, including Addition, Subtraction and Rotaion. DATA BUS ALU ZF CF SF ALU FUNCTION (1) Addition: ALU supports addition function with instructions ADDAM, ADCAM, ADDM #k, ADD #k,y .... . The addition operation affects CF and ZF. Under addition operation, if the result is "0", ZF will be "1", otherwise, ZF will be "0", When the addition operation has a carry-out, CF will be "1", otherwise, CF will be "0". EXAMPLE: Operation 3+4=7 7+F=6 0+0=0 8+8=0 Carry 0 1 0 1 Zero 0 0 1 1 (2) Subtraction: ALU supports subtration function with instructions SUBM #k, SUBA #k, SBCAM, DECM.... The subtraction operation affects CF and ZF, Under subtraction operation, if the result is negative, CF will be "0", and a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of subtraction operation is "0", the ZF is "1", otherwise, ZF is "1". EXAMPLE: Operation 8-4=4 7-F= -8(1000) 9-9=0 Carry 1 0 1 Zero 0 0 1 * This specification are subject to be changed without notice. 6.14.2001 11 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT (3) Rotation: There are two kinds of rotation operation, one is rotation left, the other is rotation right. RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data will be hold in CF. MSB LSB ACC CF RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and the shift out data will be hold in CF. MSB LSB ACC CF PROGRAM EXAMPLE: To rotate Acc clockwise(right) and shift a "1" into the MSB bit of Acc. TTCFS; CF ← 1 RRCA; rotate Acc right and shift CF=1 into MSB. HL REGISTER HL register are two 4-bit registers, they are used as a pair of pointer for the of RAM memory address. They are used as also 2 independent temporary 4-bit data registers. For certain instructions, L register can be a pointer to indicate the pin number (Port4 only). HL REGISTER STRUCTURE 3 2 1 0 3 2 1 0 H REGISTER L REGISTER HL REGISTER FUNCTION (1) HL register is used as a temporary register for instructions : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH. PROGRAM EXAMPLE: Load immediate data "5h" into L register, "0Dh" into H register. LDL #05h; LDH #0Dh; (2) HL register is used as a poiner for the address of RAM memory for instructions : LDAM, STAM, STAMI... . PROGRAM EXAMPLE: Store immediate data "#0Ah" into RAM of address 35h. LDL #5h; LDH #3h; STDMI #0Ah; RAM[35] ← Ah * This specification are subject to be changed without notice. 6.14.2001 12 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT (3) L register is used as a pointer to indicate the bit of I/O port for instructions : SELP, CLPL, TFPL. (When LR = 0 indicate P4.0) PROGRAM EXAMPLE: To set bit 0 of Port4 to "1" LDL #00h; SEPL ; P4.0 ← 1 STACK POINTER (SP) Stack pointer is a 4-bit register which stores the present stack level number. Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition. When a new subroutine is received, the SP is decreased by one automatically, likewise, if returning from a subroutine, the SP is increased one. The data transfer between ACC and SP is done with instructions "LDASP" and "STASP". DATA POINTER (DP) Data pointer is a 12-bit register that stores the ROM address can indicating the ROM code data specified by user (refer to data ROM). CLOCK AND TIMING GENERATOR The clock generator is supported by a dual clock system. The high-frequency oscillator is source from RC oscillator, the working frequency range is 480 KHz to 4 MHz defined by the mask option. The lowfrequency oscillator may be sourced from crystal or RC oscillator as defined by mask option, the working frequency is 32 KHz. CLOCK GENERATOR STRUCTURE There are two clock generator for system clock control unit, P14 is the status register that hold the CPU status. P16, P19 and P22 are the command register for system clock mode control CLK High-frequency generator fc LXIN LXOUT Low-frequency generator P14 fs Mask option for choose Crystal or RC oscillator System clock mode control System control LXIN LXOUT LXOUT * This specification are subject to be changed without notice. P19 P22 LXIN Crystal connection P16 RC connection 6.14.2001 13 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT SYSTEM CLOCK MODE CONTROL The system clock mode controller can start or stop the high-frequency and low-frequency clock oscillator and switch between the basic clocks. EM73963A has four operation modes (DUAL, SLOW,IDLE and STOP operation modes). STOP operation mode I/O wakeup High osc : stopped Low osc : stopped Command (P16) Reset Reset Command (P16) Command (P22) Command (P22) Reset release RESET operation High osc : oscillating Low osc : oscillating DUAL operation mode Reset SLOW operation mode High osc : stopped Low osc : oscillating Command (P19) Reset I/O or internal timer wakeup IDLE (CPU stops) High osc : stopped Low osc : oscillating Operation Mode DUAL SLOW IDLE STOP Oscillator High, Low frequency Low frequency Low frequency None System Clock High frequency clock Low frequency clock CPU stops CPU stops Available function One instruction cycle LCD, sound generator 8 / fc LCD 8 / fs LCD All disable - DUAL OPERATION MODE The 4-bit µc is in the DUAL operation mode when the CPU is reseted. This mode is dual clock system (high-frequency and low-frequency clocks oscillating). It can be changed to SLOW or STOP operation mode with the command register (P22 or P16). LCD display and sound generator are available for the DUAL operation mode. SLOW OPERATION MODE The SLOW operation mode is single clock system (low-frequency clock oscillating). It can be changed to the DUAL operation mode with the command register (P22), STOP operation mode with P16 and IDLE operation mode with P19. LCD display is available for the SLOW operation mode. * This specification are subject to be changed without notice. 6.14.2001 14 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT P22 3 * 2 1 SOM SOM 0 0 0 1 ** P14 0 Initial value : 0000 Select operation mode DUAL operation mode SLOW operation mode 3 * 2 WKS 1 0 LFS CPUS Initial value : *000 LFS 0 1 Low-frequency status LXIN source is not stable LXIN source is stable WKS 0 1 Wakeup status Wakeup not by internal timer Wakeup by internal timer CPUS 0 1 CPU status DUAL operation mode SLOW operation mode Port14 is the status register for CPU. P14.0 (CPU status) and P14.1 (Low-frequency status) are read-only bits. P14.2 (wakeup status) will be set as '1' when CPU is waked by internal timer. P14.2 will be cleared as '0' when user out data to P14. IDLE OPERATION MODE The IDLE operation mode suspends all CPU functions except the low-frequency clock oscillation and the LCD driver. It keeps the internal status with low power consumption without stopping the slow clock oscillation and LCD display. LCD display is available for the IDLE operation mode. Sound generator is disabled in this mode. The IDLE operation mode will be wakeup and return to the SLOW operation mode by the internal timing generator or I/O pins (P0(0..3)/WAKEUP 0..3 or P8(0..3)/WAKEUPA..D). P19 3 * 2 IDME IDME 1 0 1 0 SIDR Enable IDLE mode Enable IDLE mode no function Initial value : 0000 SIDR 0 0 0 1 1 0 1 1 Select IDLE releasing condition P0(0..3), P8(0..3) pin input P0(0..3), P8(0..3) pin input and 1 sec signal P0(0..3), P8(0..3) pin input and 0.5 sec signal P0(0..3), P8(0..3) pin input and 15.625 ms signal STOP OPERATION MODE The STOP operation mode suspends system operation and holds the internal status immediately before the suspension with low power consumption. This mode will be released by reset or I/O pins (P0(0..3)/ WAKEUP 0..3 or P8(0..3)/WAKEUP A..D). LCD display and sound generator are disabled in the STOP operation mode. * This specification are subject to be changed without notice. 6.14.2001 15 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT P16 3 * 2 SPME SPME 1 0 1 0 SWWT Initial value : 0000 Enable STOP mode Enable STOP mode no function SWWT 0 0 0 1 1 0 1 1 Set wake-up warm-up time 218/CLK 214/CLK 216/CLK no function TIME BASE INTERRUPT (TBI ) The time base can be used to generate a single fixed frequency interrupt. Eight types of frequencies can be selected with the "P25" setting. P25 3 2 1 0 initial value : 0000 0 0 0 0 0 1 1 1 1 1 P25 0 x 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 x x 0 1 0 1 0 1 0 1 x DUAL operation mode Interrupt disable Interrupt frequency LXIN / 23 Hz Interrupt frequency LXIN / 24 Hz Interrupt frequency LXIN / 25 Hz Interrupt frequency LXIN / 214 Hz Interrupt frequency LXIN / 21 Hz Interrupt frequency LXIN / 26 Hz Interrupt frequency LXIN / 28 Hz Interrupt frequency LXIN / 210 Hz Reserved SLOW operation mode Interrupt disable Reserved Reserved Reserved Interrupt frequency LXIN / 214 Hz Reserved Interrupt frequency LXIN / 26 Hz Interrupt frequency LXIN / 28 Hz Interrupt frequency LXIN / 210 Hz Reserved TIMER / COUNTER ( TIMERA, TIMERB) Timer/counters support three special functions: 1. Even counter 2. Timer. 3. Pulse-width measurement. These three functions can be executed by 2 timer/counter independently. With timerA, the counter data is saved in timer register TAH, TAM, TAL. User can set counter initial value and read the counter value by instruction "LDATAH(M,L)" and "STATAH(M,L)". With timer B register is TBH, TBM, TBL and the W/R instruction "LDATBH (M,L)" and "STATBH (M,L)". The basic structure of timer/counter is composed by two identical counter module, these two modules can be set initial timer or counter value to the timer registers, P28 and P29 are the command registers for timer A and timer B, user can choose different operation modes and internal clock rates by setting these two registers. When timer/counter overflows, it will generate a TRGA(B) interrupt request to interrupt control unit. * This specification are subject to be changed without notice. 6.14.2001 16 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT INTERRUPT CONTROL TRGB request TRGA request DATA BUS P8.3/ TRGA 12 BIT COUNTER 12 BIT COUNTER EVENT COUNTER CONTROL EVENT COUNTER CONTROL TIMER CONTROL TIMER CONTROL PULSE-WIDTH MEASUREMENT CONTROL PULSE-WIDTH MEASUREMENT CONTROL internal clock P28 TMSA IPSA P29 TMSB P8.1/ TRGB internal clock IPSB TIMER/COUNTER CONTROL P8.1/TRGB, P8.3/TRGA are the external timer inputs for timerB and timerA, they are used in event counter and pulse-width measurement mode. Timer/counter command port: P28 is the command port for timer/counterA and P29 is for the timer/ counterB. Port 28 3 2 1 TMSA 0 IPSA Initial state: 0000 Port 29 3 2 TMSB 1 0 IPSB TIMER/COUNTER MODE SELECTION TMSA (B) Function description 00 Stop 0 1 Event counter mode 1 0 Timer mode 11 Pulse width measurement mode Initial state: 0000 INTERNAL PULSE-RATE SELECTION IPSA(B) DUAL mode SLOW mode 0 0 LXIN/23 Hz Reserved 0 1 LXIN/2 7 Hz LXIN/2 Hz 1 0 LXIN/2 11Hz LXIN/2 Hz 1 1 LXIN/2 15 Hz LXIN/215Hz * This specification are subject to be changed without notice. 7 11 6.14.2001 17 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT TIMER/COUNTER FUNCTION Timer/counterA, B are can be programmable for timer, event counter and pulse width measurement mode. Each timer/counter can execute any of these functions independently. EVENT COUNTER MODE Under event counter mode, the timer/counter is increased by one at any rising edge of P8.1/TRGB for timerB (P8.3/TRGA for timer A). When timerB (timerA) counts overflow, it will provide an interrupt request TRGB (TRGA) to interrupt control unit. P8.1/TRGB (P8.3/TRGA) TimerB (TimerA) value n n+1 n+2 n+3 n+4 n+5 n+6 PROGRAM EXAMPLE: Enable timerA with P28 LDIA #0100b; OUTA P28; Enable timerA with event counter mode TIMER MODE Under timer mode, the timer/counter is increased by one at any rising edge of internal pulse. User can choose up to 4 types of internal pulse rate by setting IPSB for timerB (IPSA for timerA). When timer/counter counts overflow, an interrupt request will be sent to interrupt control unit. Internal pulse TimerB (TimerA )value n n+1 n+2 n+3 n+4 n+5 n+6 n+7 PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock LXlN=32KHz LDIA #0100B; EXAE; enable mask 2 EICIL 110111b; interrupt latch ←0, enable EI LDIA #0Ah; STATAL; LDIA #00h; STATAM; LDIA #0Fh; STATAH; LDIA #1000B; OUTA P28; enable timerA with internal pulse rate: LXIN/23 Hz NOTE: The preset value of timer/counter register is calculated as following procedure. Internal pulse rate: LXIN/23 ; LXIN = 32KHz The time of timer counter count one = 23 /LXIN = 8/32768=0.244ms The number of internal pulse to get timer overflow = 60 ms/ 0.244ms = 245.901= 0F6h The preset value of timer/counter register = 1000h - 0F6h = F0Ah PULSE WIDTH MEASUREMENT MODE * This specification are subject to be changed without notice. 6.14.2001 18 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT Under the pulse width measurement mode, the counter is incresed at the rising edge of internal pulse during external timer/counter input (P8.1/TRGB, P8.3/TRGA ) in high level, interrupt request is generated as soon as timer/counter count overflow. P8.1/TRGB(P8.3/TRGA) Internal pulse TimerB(TimerA) value n n+1 n+2 n+3 n+4 n+5 PROGRAM EXAMPLE: Enable timerA by pulse width measurement mode. LDIA #1100b; OUTA P28; Enable timerA with pulse width measurement mode. INTERRUPT FUNCTION Five interrupt sources are available, 2 from external interrupt sources and 3 from internal interrupt sources. Multiple interrupts are admitted according to their priority. Type External Internal Internal Internal Internal External Interrupt source External interrupt(INT0) Reserved TimerA overflow interrupt (TRGA) TimerB overflow interrupt (TRGB) Time base interrupt(TBI) External interrupt(INT1) Priority Interrupt Latch Interrupt Enable condition Program ROM entry address 1 2 3 4 5 6 IL5 IL4 IL3 IL2 IL1 IL0 EI=1 EI=1, MASK3=1 EI=1, MASK2=1 EI=1, MASK1=1 002h 004h 006h 008h 00Ah 00Ch EI=1,MASK0=1 INTERRUPT STRUCTURE MASK0 MASK1 MASK1 MASK2 MASK3 Reset by system reset and program instruction INT1 r0 TBI r1 IL0 IL1 TRGB r2 IL2 TRGA Reserved r4 r3 IL3 IL4 INT0 r5 IL5 Priority checker Reset by system reset and program instruction Set by program instruction EI Interrupt request Entry address generator Interrupt entry address Interrupt controller: IL0-IL5 : Interrupt latch. Hold all interrupt requests from all interrupt sources. IL's can not be set by program, but can be reset by program or system reset, so IL can only decide which interrupt source can be accepted. MASK0-MASK3 : Except INT0 ,MASK register may promit or inhibit all interrupt sources. * This specification are subject to be changed without notice. 6.14.2001 19 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT EI : Enable interrupt Flip-Flop can promit or inhibit all interrupt sources, when interrupt occurs, EI is auto cleared to "0" , after RTI instruction is executed, EI is auto set to "1" again . Priority checker: Check interrupt priority when multiple interrupts occur. INTERRUPT FUNCTION The procedure of interrupt operation: 1. Push PC and all flags to stack. 2. Set interrupt entry address into PC. 3. Set SF= 1. 4. Clear EI to inhibit other interrupts occur. 5. Clear the IL with which interrupt source has already been accepted. 6. Excute interrupt subroutine from the interrupt entry address. 7. CPU accept RTI, restore PC and flags from stack . Set EI to accept other interrupt requests. PROGRAM EXAMPLE: To enable interrupt of "INT0, TRGA" LDIA #1100B; EXAE; set mask register "1100B" EICIL 010111B ; enable interrupt F.F and clear IL3 and IL5. LCD DRIVER It can directly drive the liquid crystal display ( LCD ) and has 40 segments , 8 commons output pins. There are total 40x8 dots can be display. The V1~V4 are the LCD bias voltage input pins. (1) LCD driver control command register: Port27 3 2 1 0 Initial value: 0000 LDC * * LCD DISPLAY CONTROL LDC Function description 0 0 LCD display disable 0 1 Blanking 1 0 no function 1 1 LCD display enable * : Don't care . P27 is the LDC driver control command register . The initial value is 0000 . When LDC ( bit2 and bit3 of P27 ) is set to "00", the LCD display is disabled . When LDC is set to "01", the LCD is blanking, the COM pins are inactive and the SEG pins output the display data continuously . When LDC is set to "11", the LCD display is enabled. (2) LCD display data area: The LCD display data is stored in the display data area of the data memory ( RAM) . The LCD display data area is as illustrated below: * This specification are subject to be changed without notice. 6.14.2001 20 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT The display data from the display data area are automatically read out and send to the LCD driver directly by the hardware. Therefore, the display patterns can be changed only by overwritting the contents of the display data area through software. The display memory area that is not used to store the LCD display data could be used as the ordinary data memory. LCD display data area : Bank1 P9.3=1 0 1 2 3 100-10Fh 110-11Fh 120-12Fh 130-13Fh 140-14Fh 150-15Fh 160-16Fh 170-17Fh 4 5 6 7 8 9 A B C D E F SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 P26 is the start address register of LCD common pin. Port26 3 2 1 0 Initial value: *000 * CSA Common start address register RAM CSA X000 X001 X010 X011 X100 X101 X110 X111 100109h 110119h 120129h 130139h COM0 COM1 COM2 COM3 COM7 COM0 COM1 COM2 COM6 COM7 COM0 COM5 COM6 COM4 150159h 160169h 170179h COM4 COM5 COM6 COM7 COM3 COM4 COM5 COM6 COM1 COM2 COM3 COM4 COM5 COM7 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM0 COM1 COM2 COM3 COM3 COM4 COM5 COM6 COM7 COM0 COM1 COM2 COM2 COM3 COM4 COM5 COM6 COM7 COM0 COM1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM0 * This specification are subject to be changed without notice. 140149h 6.14.2001 21 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT PROGRAM EXAMPLE: LDIA OUTA LDIA OUTA LDIA SEP STA #0000B P26 #1100B ; LCD display enable P27 #1010B ; store 1010B to RAM[101h] P9,3 01H (3) LCD waveform : (1/5 bias) Although there are two LCD waveform types, but for the reason of the number of voltage transition point in type A is greater than type B, so type B gets a better display performance. S E G 0 COM0 * TYPE A : : ON : OFF * TYPE B : COM0 COM0 VDD VDD V4 V3 V2 V1 Vss V4 V3 V2 V1 Vss COM1 COM1 SEG0 SEG0 SEG0-COM0 SEG0-COM0 ON ON SEG0-COM1 SEG0-COM1 OFF OFF COM7 Frame freq.=64Hz Frame freq. =64Hz (4) LCD bias resistor : There are high and low resistance choices for LCD bias resistor. To choose low bias resistor will take more power but get a better display performance. (5) LCD bias supply : The LCD bias voltage can be supplied by bias resistor. When user chooses a large bias resistor or uses a large LCD panel, to connect 4 capacitors to V1~V4 can get a better display performance. Otherwise, you can open V1~V4 and ignore these 4 capacitors. * This specification are subject to be changed without notice. 6.14.2001 22 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT 0.1µF VDD V1 V2 V3 VDD V1 0.1µF V2 V3 0.1µF or 0.1µF VSS V3 V4 0.1µF V4 V4 or VDD V1 V2 VSS VSS 0.1µF 0.1µF 0.1µF 0.1µF SOUND EFFECT EM73963A has a built-in sound effect generator. It includes the tone generator, random generator and volume control. The tone generator is a binary down counter and random generator is a 9-bit linear feedback shift register. The sound generator is available for the DUAL mode. When the CPU is reseted or in the IDLE or STOP operation mode, the sound generator is disable and the P4.0/SOUND is in high state and SOUND is in low state. P30 P23,P24 f2 240KHz Tone 3 kinds f1 generator of divider ÷2 ÷2 f2x2 High Random generator Output control SOUND SOUND PWM volume control * This specification are subject to be changed without notice. 6.14.2001 23 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT Sound generator command register Three basic frequencies for sound generator can be selected by P30. The output of sound effect generator can be tone, random tone or both combination. Port30 3 2 BFREQ BFREQ 0 0 0 1 1 0 1 1 Basic frequency (f1) select 240 KHz 120 KHz 60 KHz don't care 1 0 SMODE Initial value : 0000 SMODE 0 0 0 1 1 0 1 1 Sound generator mode Disable Tone output Random output Tone+random output Tone frequency register The 8-bit tone frequency register (TF) is P24 and P23. The tone frequency will be changed when user output the different data to P24 and P23. Port24 Port23 3 2 1 0 3 Higher nibble register 2 1 0 Initial value : 1111 1111 Lower nibble register ** f1=240K/2X, f2=f1/(TF+1)/2, TF=1~255, TF0 ** Example : BFREQ=10, TF=00110001B. ⇒ f1=60K Hz, f2=60K Hz/50/2=600 Hz Random generator f(x)=x9+x4+1 + 1 2 3 4 5 6 7 8 9 Volume control register The are 8 volume levels for sound generator. P17 is the volume control register. Port17 Initial value : * 111 3 2 1 0 * VCR VCR ts/tp 1 1 1 8/8 ts 1 1 0 7/8 1 0 1 6/8 1 0 0 5/8 0 1 1 4/8 tp 0 1 0 3/8 1 tp= 60KHz 0 0 1 2/8 0 0 0 1/8 * This specification are subject to be changed without notice. 6.14.2001 24 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT PROGRAM EXAMPLE: LDIA OUTA LDIA OUTA LDIA OUTA LDIA OUTA #1001B ; basic frequency : 60 KHz tone output P30 #0011B ; volume control P17 #0011B ; 600 Hz tone output P24 #0001B P23 RESETTING FUNCTION When CPU in normal working condition and RESET pin is held in low level for three instruction cycles at least, then CPU begins to initialize the whole internal states, when RESET pin changes to high level, CPU begins to work in normal condition. The CPU internal state during reset condition is as following table : Hardware condition in RESET state Program counter Status flag Interrupt enable flip-flop ( EI ) MASK0 ,1, 2, 3 Interrupt latch ( IL ) P3, 9, 14, 16, 17, 19, 22, 25, 26, 27, 28, 29, 30 P4, 8, 17, 23, 24 CLK, LXIN Initial value 0000h 01h 00h 00h 00h 00h 0Fh Start oscillation The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option. The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD. RESET * This specification are subject to be changed without notice. 6.14.2001 25 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT EM73963A I/O PORT DESCRIPTION : Port 0 E 1 2 3 4 E 5 6 7 8 E 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 I Input function Input port , wakeup function ---Input port ---Input port, wakeup function, external interrupt input -----CPU status register -- Output function I E E I I I I I I I I I I I I I Note --P3(0..2) : ROM bank selection Output port, P4.0/SOUND ---Output port P9.3 : RAM bank selection ------STOP mode control register Sound effect volume control register -IDLE mode control register --DUAL/SLOW mode control register Sound effect frequency register Sound effect frequency register Timebase control register LCD common start address register LCD control register Timer/counter A control register Timer/counter B control register Sound effect command register -- * This specification are subject to be changed without notice. low nibble high nibble 6.14.2001 26 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ABSOLUTE MAXIMUM RATINGS Items Sym. Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Ratings VDD VIN VO PD TOPR TSTG Conditions -0.5V to 6V -0.5V to VDD+0.5V -0.5V to VDD+0.5V 300mW 0oC to 50oC -55oC to 125oC TOPR=50oC RECOMMANDED OPERATING CONDITIONS Items Sym. Supply Voltage Input Voltage Operating Frequency Ratings VDD V IH V IL FC Fs Condition 2.4V to 5.5V 0.90xVDD to VDD 0V to 0.10xVDD 480K to 4MHz 32KHz CLK (RC osc) LXIN,LXOUT (crystal/RC osc) DC ELECTRICAL CHARACTERISTICS (VDD=3±0.3V, VSS=0V, TOPR=25oC) Parameters Supply current Hysteresis voltage Sym. Min. Typ. Max. Unit Conditions I DD - 0.9 2 mA - 12 25 µA - 10 1 2.4 4 0.1 -250 - ±1 ±1 -500 - µA µA V V µA µA µA V VDD=3.3V, no load, NORMAL mode, Fs=32KHz (R=750kΩ), Fc=4MHz (RC osc : R=5.6KΩ, C=20pF) VDD=3.3V, no load, SLOW mode, Fs=32KHz LCD on VDD=3.3V, IDLE mode, LCD off VDD=3.3V, STOP mode RESET, P0, P8 2.0 2.4 - V 80 200 - 0.15 150 400 15 20 0.3 1 230 600 - V µA KΩ KΩ % % Input current V HYS+ V HYSI IH Output voltage I IL V OH Leakage current Input resistor Frequency stability Frequency variation V OL I LO R IN 0.50VDD 0.20VDD 0.75VDD 0.40VDD * This specification are subject to be changed without notice. P0, RESET, VDD=3.3V, VIH=3.3/0V Open-drain, VDD=3.3V, VIH=3.3/0V Push-pull, VDD=3.3V, VIL=0.4V, except P4 Push-pull, P4(high current PMOS), SOUND, VDD=2.7V, IOH=-0.9mA Push-pull, P4(low current PMOS), P8, VDD=2.7V, IOH=-40µA VDD=2.7V, IOL=0.9mA Open-drain, VDD=3.3V, VO=3.3V P0 RESET Fc=4MHz, RC osc, [F(3V)-F(2.4V)]/F(3V) Fc=4MHz, VDD=3V,RC osc, [F(typical)-F(worse case)]/F(typical) 6.14.2001 27 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT (VDD=4.5±0.5V, VSS=0V, TOPR=25oC) Parameters Supply current Hysteresis voltage Sym. Min. Typ. Max. Unit Conditions I DD - 1.5 2 mA - 35 65 µA - 15 1 3.0 8 0.1 - ±1 ±1 -1 - µA µA V V µA µA mA V VDD=5.0V, no load, NORMAL mode, Fs=32KHz (R=820kΩ), Fc=4MHz (RC osc : R=5.6KΩ, C=20pF) VDD=5.0V, no load, SLOW mode, Fs=32KHz LCD on VDD=5.0V, IDLE mode, LCD off VDD=5.0V, STOP mode RESET, P0, P8 2.4 - - V 40 100 - 75 200 15 20 1 1 120 300 - V µA KΩ KΩ % % Input current V HYS+ V HYSI IH Output voltage I IL VOH Leakage current Input resistor Frequency stability Frequency variation V OL I LO R IN 0.50VDD 0.20VDD 0.75VDD 0.40VDD * This specification are subject to be changed without notice. P0, RESET, VDD=5.0V, VIH=5.0/0V Open-drain, VDD=5.0V, VIH=5.0/0V Push-pull, VDD=5.0V, VIL=0.4V, except P4 Push-pull, P4(high current PMOS), SOUND, VDD=4.0V, IOH=-4mA Push-pull, P4(low current PMOS), P8, VDD=4.0V, IOH=-200µA VDD=4.0V, IOL=4mA Open-drain, VDD=5.0V, VO=5.0V P0 RESET Fc=4MHz,RC osc,[F(4.5V)-F(3.6V)]/F(4.5V) Fc=4MHz, VDD=4.5V,RC osc, [F(typical)-F(worse case)]/F(typical) 6.14.2001 28 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT RESET PIN TYPE TYPE RESET-A RESET mask option OSCILLATION PIN TYPE TYPE OSC-B TYPE OSC-C LXIN Crystal Osc. CLK RC Osc. (comparator) LXOUT TYPE OSC-F LXIN RC Osc. (inverter) LXOUT INPUT PIN TYPE TYPE INPUT-A TYPE INPUT-B WAKEUP function mask option : mask option * This specification are subject to be changed without notice. P0/WAKEUP TYPE INPUT-A 6.14.2001 29 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT I/O PIN TYPE TYPE I/O TYPE I/O-L path B SEL path A Input data mask option TYPE I/O Special function control input Output data latch Output data WAKEUP function mask option TYPE I/O-O : mask option Path A : Path B : For set and clear bit of port instructions, data goes through path A from output data latch to CPU. For input and test instructions, data from output pin go through path B to CPU and the output data latch will be set to high. * This specification are subject to be changed without notice. 6.14.2001 30 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 V1 V2 V3 V4 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 PAD DIAGRAM 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 SEG24 1 49 SEG7 SEG25 2 48 SEG6 SEG26 3 47 SEG5 SEG27 4 46 SEG4 SEG28 5 45 SEG3 SEG29 6 44 SEG2 SEG30 7 43 SEG1 SEG31 42 SEG0 SEG32 8 9 41 COM7 SEG33 10 40 COM6 SEG34 39 COM5 SEG35 11 12 38 COM4 SEG36 13 37 COM3 SEG37 14 36 COM2 SEG38 15 35 COM1 SEG39 16 34 COM0 EM73963A (0,0) SOUND 32 33 P4.0 31 VDD TEST CLK RESET LXIN * This specification are subject to be changed without notice. 27 28 29 30 LXOUT VSS P0.0 P0.1 P8.0 P0.2 26 P0.3 25 P8.1 20 21 22 23 24 P8.2 17 18 19 P8.3 ELAN 6.14.2001 31 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 P8.3 P8.2 P8.1 P8.0 P0.3 P0.2 P0.1 P0.0 VSS LXIN LXOUT RESET CLK TEST VDD P4.0 SOUND COM0 COM1 COM2 COM3 COM4 COM5 COM6 X -1153.5 -1153.5 -1153.5 -1153.5 -1153.5 -1153.5 -1153.5 -1153.5 -1153.5 -1153.5 -1153.5 -1153.5 -1153.5 -1153.5 -1153.5 -1153.5 -1157.6 -1036.1 -914.4 -794.8 -671.8 -551.9 -428.9 -309.0 -161.3 -17.8 354.3 480.9 600.8 722.8 879.4 1035.0 1158.1 1151.3 1151.3 1151.3 1151.3 1151.3 1151.3 1151.3 * This specification are subject to be changed without notice. Y 903.0 783.1 663.2 543.3 423.4 303.5 183.6 63.7 -56.2 -176.1 -296.0 -415.9 -535.8 -655.7 -775.6 -895.5 -1077.5 -1077.5 -1077.5 -1077.5 -1077.5 -1077.5 -1077.5 -1077.5 -1077.5 -1077.5 -1077.5 -1077.5 -1077.5 -1077.5 -1077.5 -1077.5 -1077.5 -895.5 -775.6 -655.7 -535.8 -415.9 -296.0 -176.1 6.14.2001 32 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Symbol COM7 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 V1 V2 V3 V4 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 X 1151.3 1151.3 1151.3 1151.3 1151.3 1151.3 1151.3 1151.3 1151.3 1138.1 1018.2 898.3 778.4 658.5 538.6 418.7 298.8 178.9 59.0 -60.9 -180.8 -300.7 -420.6 -540.5 -660.4 -780.3 -900.2 -1020.1 -1140.0 Y -56.2 63.7 183.6 303.5 423.4 543.3 663.2 783.1 903.0 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 1077.8 Chip Size : 2620 x 2470 µm Unit : µm For PCB layout, IC substrate must be floated or connected to VSS. * This specification are subject to be changed without notice. 6.14.2001 33 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT INSTRUCTION TABLE (1) Data Transfer Mnemonic Object code ( binary ) Operation description Byte LDA x LDAM LDAX LDAXI LDH #k LDHL x LDIA #k LDL #k STA x STAM STAMD STAMI STD #k,y STDMI #k THA TLA 0110 1010 xxxx xxxx 0101 1010 0110 0101 0110 0111 1001 kkkk 0100 1110 xxxx xx00 1101 kkkk 1000 kkkk 0110 1001 xxxx xxxx 0101 1001 0111 1101 0111 1111 0100 1000 kkkk yyyy 1010 kkkk 0111 0110 0111 0100 Acc←RAM[x] Acc ←RAM[HL] Acc←ROM[DP]L Acc←ROM[DP]H,DP+1 HR←k LR←RAM[x],HR←RAM[x+1] Acc←k LR←k RAM[x]←Acc RAM[HL]←Acc RAM[HL]←Acc, LR-1 RAM[HL]←Acc, LR+1 RAM[y]←k RAM[HL]←k, LR+1 Acc←HR Acc←LR 2 1 1 1 1 2 1 1 2 1 1 1 2 1 1 1 Object code ( binary ) Operation description Byte Cycle 2 1 2 2 1 2 1 1 2 1 1 1 2 1 1 1 C - Flag Z Z Z Z Z Z Z Z Z Z Z C C C Flag Z Z Z S C' C' C C - Flag Z Z Z Z Z Z Z Z Z Z Z Z S C' C' C' C' C' C' C' C C C C' S 1 1 1 1 1 1 1 1 1 1 C C' 1 C' 1 1 (2) Rotate Mnemonic RLCA RRCA 0101 0000 0101 0001 ←CF←Acc← →CF→Acc→ 1 1 Cycle 1 1 (3) Arithmetic operation Mnemonic Object code ( binary ) Operation description Byte ADCAM ADD #k,y ADDA #k ADDAM ADDH #k ADDL #k ADDM #k DECA DECL DECM INCA 0111 0100 0110 0111 0110 0110 0110 0101 0111 0101 0101 Acc←Acc + RAM[HL] + CF RAM[y]←RAM[y] +k Acc←Acc+k Acc←Acc + RAM[HL] HR←HR+k LR←LR+k RAM[HL]←RAM[HL] +k Acc←Acc-1 LR←LR-1 RAM[HL]←RAM[HL] -1 Acc←Acc + 1 1 2 2 1 2 2 2 1 1 1 1 0000 1001 kkkk yyyy 1110 0101 kkkk 0001 1110 1001 kkkk 1110 0001 kkkk 1110 1101 kkkk 1100 1100 1101 1110 * This specification are subject to be changed without notice. Cycle 1 2 2 1 2 2 2 1 1 1 1 6.14.2001 34 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT INCL INCM SUBA #k SBCAM SUBM #k 0111 1110 0101 1111 0110 1110 0111 kkkk 0111 0010 0110 1110 1111 kkkk LR←LR + 1 RAM[HL]←RAM[HL]+1 Acc←k-Acc Acc←RAM[HLl - Acc - CF' RAM[HL]←k - RAM[HL] 1 1 2 1 2 1 1 2 1 2 C - Z Z Z Z Z C' C' C C C (4) Logical operation Object code ( binary ) Operation description Byte ANDA #k ANDAM ANDM #k ORA #k ORAM ORM #k XORAM 0110 0111 0110 0110 0111 0110 0111 Acc←Acc&k Acc←Acc & RAM[HL] RAM[HL]←RAM[HL]&k Acc←Acc k Acc ←Acc RAM[HL] RAM[HL]←RAM[HL] k Acc←Acc^RAM[HL] 2 1 2 2 1 2 1 -- 1110 0110 kkkk 1011 1110 1110 kkkk 1110 0100 kkkk 1000 1110 1100 kkkk 1001 ---- Mnemonic Cycle 2 1 2 2 1 2 1 C - Flag Z Z Z Z Z Z Z Z S Z' Z' Z' Z' Z' Z' Z' (5) Exchange Mnemonic Object code ( binary ) Operation description Byte Cycle EXA x EXAH EXAL EXAM EXHL x 0110 1000 xxxx xxxx 0110 0110 0110 0100 0101 1000 0100 1100 xxxx xx00 Acc↔RAM[x] Acc↔HR Acc↔LR Acc↔RAM[HL] LR↔RAM[x], HR↔RAM[x+1] 2 1 1 1 2 2 2 1 2 2 Mnemonic Object code ( binary ) Operation description Byte SBR a 00aa aaaa 1 1 LBR a SLBR a 1100 aaaa aaaa aaaa 0101 0101 1100 aaaa If SF=1 then PC←PC12-6.a5-0 else null If SF= 1 then PC←a else null If SF=1 then PC←a else null 2 3 2 3 Operation description Byte k-RAM[y] RAM[x]-Acc 2 2 Flag C Z S - Z Z Z Z 1 1 1 1 - - 1 Flag C Z - - S - - 1 1 (6) Branch aaaa aaaa (a:1000~1FFFh) Cycle 1 0101 0111 1100 aaaa aaaa aaaa (a:0000~0FFFh) (7) Compare Mnemonic Object code ( binary ) CMP #k,y 0100 1011 kkkk yyyy CMPA x 0110 1011 xxxx xxxx * This specification are subject to be changed without notice. Cycle 2 2 Flag C Z C C Z Z 6.14.2001 S Z' Z' 35 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT Mnemonic Object code ( binary ) CMPAM CMPH #k CMPIA #k CMPL #k 0111 0011 0110 1110 1011 kkkk 1011 kkkk 0110 1110 0011 kkkk Operation description Byte RAM[HL] - Acc k - HR k - Acc k-LR 1 2 1 2 Cycle 1 2 1 2 C Flag Z C - Flag Z - S 1 1 1 1 1 1 1 1 * * * * * * * Flag Z - S - C C - Z Z Z Z S Z' C Z' C (8) Bit manipulation Mnemonic Object code ( binary ) Operation description Byte CLM CLP CLPL CLR SEM SEP SEPL SET TF TFA TFM TFP TFPL TT TTP 1111 00bb 0110 1101 11bb pppp 0110 0000 0110 1100 11bb yyyy 1111 01bb 0110 1101 01bb pppp 0110 0010 0110 1100 01bb yyyy 0110 1100 00bb yyyy 1111 10bb 1111 11bb 0110 1101 00bb pppp 0110 0001 0110 1100 10bb yyyy 0110 1101 10bb pppp RAM[HL]b←0 PORT[p]b←0 PORT[LR3-2+4]LR1-0←0 RAM[y]b←0 RAM[HL]b←1 PORT[p]b←1 PORT[LR3-2+4]LRl-0←1 RAM[y]b←1 SF←RAM[y]b' SF←Accb' SF←RAM[HL]b' SF←PORT[p]b' SF←PORT[LR 3-2 +4]LR1-0' SF←RAM[y]b SF←PORT[p]b 1 2 1 2 1 2 1 2 2 1 1 2 1 2 2 Mnemonic Object code ( binary ) Operation description Byte LCALL a 0100 0aaa aaaa aaaa 2 2 SCALL a 1110 nnnn 1 2 - - - RET 0100 1111 STACK[SP]←PC, SP←SP -1, PC←a STACK[SP]←PC, SP←SP - 1, PC←a, a = 8n + 6 (n =1∼15),0086h (n = 0) SP←SP + 1, PC←STACK[SP] C - 1 2 - - - Mnemonic Object code ( binary ) Operation description Byte INA INM OUT OUTA OUTM 0110 1111 0100 pppp 0110 1111 1100 pppp 0100 1010 kkkk pppp 0110 1111 000p pppp 0110 1111 100p pppp Acc←PORT[p] RAM[HL]←PORT[p] PORT[p]←k PORT[p]←Acc PORT[p]←RAM[HL] 2 2 2 2 2 b p,b y,b b p,b y,b y,b b b p,b y,b p,b Cycle 1 2 2 2 1 2 2 2 2 1 1 2 2 2 2 (9) Subroutine Cycle (10) Input/output p p #k,p p p * This specification are subject to be changed without notice. Cycle 2 2 2 2 2 C - Flag Z Z - 6.14.2001 S Z' Z' 1 1 1 36 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT (11) Flag manipulation Mnemonic Object code ( binary ) Operation description Byte Cycle TFCFC TTCFS TZS 0101 0011 0101 0010 0101 1011 SF←CF', CF←0 SF←CF, CF←1 SF←ZF 1 1 1 1 1 1 Flag C 0 1 - Z - S * * * (12) Interrupt control Mnemonic Object code ( binary ) Operation description Byte CIL r DICIL r EICIL r EXAE RTI 0110 0011 11rr rrrr 0110 0011 10rr rrrr 0110 0011 01rr rrrr 0111 0101 0100 1101 IL←IL & r EIF←0,IL←IL&r EIF←1,IL←IL&r MASK↔Acc SP←SP+1,FLAG.PC ←STACK[SP],EIF ←1 2 2 2 1 1 Mnemonic Object code ( binary ) Operation description Byte NOP 0101 0110 no operation 1 Cycle 2 2 2 1 2 C * Flag Z * S 1 1 1 1 * C - Flag Z - S - C - Flag Z Z Z Z Z Z Z Z Z Z Z - S 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (13) CPU control Cycle 1 (14) Timer/Counter & Data pointer & Stack pointer control Mnemonic Object code ( binary ) Operation description Byte LDADPL LDADPM LDADPH LDASP LDATAL LDATAM LDATAH LDATBL LDATBM LDATBH STADPL STADPM STADPH STASP STATAL STATAM STATAH STATBL STATBM STATBH 0110 1010 1111 1100 0110 1010 1111 1101 0110 1010 1111 1110 0110 1010 1111 1111 0110 1010 1111 0100 0110 1010 1111 0101 0110 1010 1111 0110 0110 1010 1111 1000 0110 1010 1111 1001 0110 1010 1111 1010 0110 1001 1111 1100 0110 1001 1111 1101 0110 1001 1111 1110 0110 1001 1111 1111 0110 1001 1111 0100 0110 1001 1111 0101 0110 1001 1111 0110 0110 1001 1111 1000 0110 1001 1111 1001 0110 1001 1111 1010 Acc←[DP]L Acc←[DP]M Acc←[DP]H Acc←SP Acc←[TA]L Acc←[TA]M Acc←[TA]H Acc←[TB]L Acc←[TB]M Acc←[TB]H [DP]L←Acc [DP]M←Acc [DP]H←Acc SP←Acc [TA]L←Acc [TA]M←Acc [TA]H←Acc [ TB]L←Acc [TB]M←Acc [TB]H←Acc 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 * This specification are subject to be changed without notice. Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 6.14.2001 37 EM73963A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT **** SYMBOL DESCRIPTION Symbol HR PC SP ACC CF SF IL PORT[p] ΤΒ RAM[x] ROM[DP]H [DP]M [TA]L([TB]L) [TA]H([TB]H) LR3-2 PC12-6 ↔ -- #k y b Description Symbol H register Program counter Stack pointer Accumulator Carry flag Status flag Interrupt latch Port ( address : p ) Timer/counter B Data memory (address : x ) High 4-bit of program memory Middle 4-bit of data pointer register Low 4-bit of timer/counter A (timer/counter B) register High 4-bit of timer/counter A (timer/counter B) register Bit 3 to 2 of LR LR DP STACK[SP] FLAG ZF EI MASK ΤΑ RAM[HL] ROM[DP]L [DP]L [DP]H [TA]M([TB]M) Bit 12 to 6 of program counter Exchange Substraction Logic OR Inverse operation 4-bit immediate data 4-bit zero-page address Bit address ← + & ^ . x p r LR 1-0 a5-0 * This specification are subject to be changed without notice. Description L register Data pointer Stack specified by SP All flags Zero flag Enable interrupt register Interrupt mask Timer/counter A Data memory (address : HL ) Low 4-bit of program memory Low 4-bit of data pointer register High 4-bit of data pointer register Middle 4-bit of timer/counter A (timer/counter B) register Contents of bit assigned by bit 1 to 0 of LR Bit 5 to 0 of destination address for branch instruction Transfer Addition Logic AND Logic XOR Concatenation 8-bit RAM address 4-bit or 5-bit port address 6-bit interrupt latch 6.14.2001 38