EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr GENERAL DESCRIPTION EM73A89B is an advanced single chip CMOS 4-bit micro-controller. It contains 16K-byte ROM, 1012-nibble RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function, and one high speed conter. EM73A89B also equipped with 6 interrupt sources, 3~7 I/O ports (including 1 input port and 2~7 bidirection ports), LCD display (64x16 or 64x32), built-in watch-dog-timer and speech synthesizer. It's low power consumption and high speed feature are further strengten with DUAL, SLOW, IDLE and STOP operation mode for optimized power saving. FEATURES Operation voltage Clock source : 2.2V to 3.6V. : Dual clock system. Low-frequency oscillator is 32KHz. Crystal oscillator or RC oscillator by mask option and high-frequency oscillator is a built-in internal oscillator. Instruction set : 107 powerful instructions. Instruction cycle time : 0.85µs for 9.2M or 1.7µs for 4.6M Hz selected by mask option(high speed clock). 122µs for 32768 Hz (low speed clock, frequency double). ROM capacity : 16K x 8 bits. RAM capacity : 1012 x 4 bits. Input port : 1 port (P0.0-P0.3), IDLE/STOP releasing function is available by mask option. (each input pin has a pull-up and pull-down resistor available by mask option). Bidirection port : 2~7 ports (P1, P2, P4, P5, P6, P7, P8). IDLE/STOP release function for P8(0.. 3) is available by mask option. P1, P2, P5, P6, P7 are shared with LCD pins. Built-in watch-dog-timer counter : It is available by mask option. 12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse width measurement mode. Built-in time base counter : 22 stages. Subroutine nesting : Up to 13 levels. Interrupt : External interrupt . . . . . . 2 input interrupt sources. Internal interrupt . . . . . . 2 timer overflow interrupts, 1 time base interrupt. 1 speech/HTC interrupt. High speed counter : The high speed counter includes one 8-bit high speed counter and a resistor to frequency oscillator. It has resistor to frequrncy oscillation mode, melody mode and auto load timer mode. LCD driver : 64x32 or 64x16 dots, 1/32 or 1/16 duty, 1/5 bias by mask option. Speech synthesizer : 992K speech data ROM (use as 992K nibbles data ROM). PWM or current D/A : Output selection by mask option. Power saving function : SLOW, IDLE, STOP operation modes. Package type : Chip form 126 pins. * This specification are subject to be changed without notice. 8.16.2001 1 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim FUNCTION BLOCK DIAGRAM RESET CLK LXIN LXOUT Reset Control Clock Generator Timing Generator Clock Mode Control System Control Data pointer Speech synthesizer Instruction Decoder Instruction Register Interrupt Control HTC Time Base ROM Data Bus Timer/Counter (TA,TB) RAM Flag Z C S HR LR P0.0/WAKEUP0 P0.1/WAKEUP1 P0.2/WAKEUP2 P0.3/WAKEUP3 I/O Control P1/SESG60~63 P2,5,6,7/COM16~31 or SEG44~59 SEG0~43 LCD Driver COM0~15 VC1~VC4, VA,VB VR1~VR4 Stack ALU PC P4.0(RX) P4.1 P4.2(RY) P4.3(RZ) Stack pointer ACC P8.0(INT1)/WAKEUPA P8.1(TRGB)/WAKEUPB P8.2(INT0)/WAKEUPC P8.3(TRGA)/WAKEUPD BZ1/VO BZ2 PIN DESCRIPTIONS Symbol VDD,VDD2 VSS RESET CLK LXIN LXOUT P0(0..3)/WAKEUP0..3 P4.0(RX),P4.2(RY), P4.3(RZ) P4.1 Pin-type Function Power supply (+) Power supply (-) RESET-A System reset input signal, low active mask option : none pull-up OSC-G Capacitor connecting pin for internal high frequency oscillator. OSC-B/OSC-H Crystal/Resistor connecting pin for low speed clock source. OSC-B Crystal connecting pin for low speed clock source. INPUT-B 4-bit input port with IDLE/STOP releasing function mask option : wakeup enable, pull-up wakeup enable, none wakeup disable, pull-up wakeup disable, pull-down wakeup disable, none I/O-X1 3-bit bidirection I/O pins or RF oscillation input pins. mask option : open-drain (apply to RF oscillation) high current push-pull normal current push-pull low current push-pull I/O-Q1 1-bit bidirection I/O pin. mask option : open-drain high current push-pull normal current push-pull low current push-pull * This specification are subject to be changed without notice. 8.16.2001 2 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT Symbol Pin-type P8.0(INT1)/WAKEUPA I/O-X1 P8.2(INT0)/WAKEUPC P8.1(TRGB)/WAKEUPB I/O-X1 P8.3(TRGA)/WAKEUPD VCA, VCB, V1~V6 BZ1/VO BZ2 TEST *16 COMMONS : COM0~COM15 SEG0~SEG59 P1(0..3)/SEG63..60 P2(0..3),P5(0..3), P6(0..3),P7(0..3) *32 COMMONS : COM0~COM31 SEG0~SEG43 P1(0..3)/SEG63..60, P2(0..3)/SEG59..56, P5(0..3)/SEG55..52, P6(0..3)/SEG51..48, P7(0..3)/SEG47..44 I/O-P I/O-P I/O-P ary n i m i l e Pr Function 2-bit bidirection I/O port with external interrupt sources input and IDLE /STOP releasing function mask option : wakeup enable, normal current push-pull wakeup ensable, low current push-pull wakeup disable, high current push-pull wakeup disable, normal current push-pull wakeup disable, low current push-pull wakeup disable, open drain 2-bit bidirection I/O port with time/counter A,B external input and IDLE /STOP releasing function mask option : wakeup enable, normal current push-pull wakeup ensable, low current push-pull wakeup disable, high current push-pull wakeup disable, normal current push-pull wakeup disable, low current push-pull wakeup disable, open drain LCD bias voltage pins PWM or current D/A output pin for speech synthesizer by mask option PWM output pin for speech synthesizer Tie Vss as package type, no connecting as COB type. LCD common output pins LCD segment output pins 4-bit bidirection I/O pins with LCD segment pins mask option : LCD segment pin push-pull open-drain 16-bit bidirection I/O pins mask option : push-pull open-drain LCD common output pins LCD segment output pins 16-bit bidirection I/O pins with LCD segment pins mask option : LCD segment pin push-pull open-drain * This specification are subject to be changed without notice. 8.16.2001 3 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT FUNCTION DESCRIPTIONS inary Prelim PROGRAM ROM ( 16K X 8 bits ) 16 K x 8 bits program ROM contains user's program and some fixed data. The basic structure of the program ROM may be categorized into 5 partitions. 1. Address 0000h : Reset start address. 2. Address 0002h - 000Ch : 6 kinds of interrupt service routine entry addresses. 3. Address 000Eh - 0086h : SCALL subroutine entry address, only available at 000Eh, 0016h, 001Eh, 0026h, 002Eh, 0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh, 0086h. 4. Address 0000h - 07FFh : LCALL subroutine entry address. 5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program and data region. address Bank 0 : 0000h 0002h 0004h 0006h 0008h 000Ah 000Ch 000Eh 0086h Reset start address INT0 ; interrupt service routine entry address SPI or HTCI TRGA TRGB TBI INT1 Subroutine call entry address designated by [LCALL a] instruction SCALL, subroutine call entry address .. . 07FFh 0800h 0FFFh 1000h 1FFFh Bank 1 Bank 2 Data table for [LDAX],[LDAXI] instruction Bank 3 * This specification are subject to be changed without notice. 8.16.2001 4 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr User's program and fixed data are stored in the program ROM. User's program is executed using the PC value to fetch an instruction code. The 16Kx8 bits program ROM can be divided into 4 banks. There are 4Kx8 bits per bank. The program ROM bank is selected by P3(1..0). The program counter is a 13-bit binary counter. The PC and P3 are initialized to "0" during reset. When P3(1..0)=00B or 11B, the bank0 and bank1 of program ROM will be selected. P3(1..0)=01B, the bank0 and bank2 will be selected. P3(1..0)=10B, the bank0 and bank3 will be selected. P3=xx00B Address P3=xx11B P3=xx01B P3=xx10B 0000h : : Bank0 Bank0 Bank0 0FFFh 1000h : : Bank1 Bank2 Bank3 1FFFh PROGRAM EXAMPLE: BANK 0 : : : LDIA #00H ; set program ROM to bank1 OUTA P3 B XA1 : XA : : : LDIA #01H ; set program ROM to bank2 OUTA P3 B XB1 : XB : : : LDIA #02H ; set program ROM to bank3 OUTA P3 B XC1 : XC : : : B XD XD : : : : ;-------------------------------------------------------------------------------------BANK 1 XA1 : : : B XA : XA2 : : START: * This specification are subject to be changed without notice. 8.16.2001 5 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim B XA2 : ;--------------- -------------------- -------------------- -------------------- -BANK 2 XB1 : : : B XB : XB2 : : B XB2 : ;--------------- -------------------- -------------------- -------------------- -BANK 3 XC1 : : : B XC : XC2 : : B XC2 Fixed data can be read out by table-look-up instruction. Table-look-up instruction is requires the Data point (DP) to indicate the ROM address in obtaining the ROM code data (Except bank 0) : LDAX LDAXI Acc ← ROM[DP]L Acc ← ROM[DP]H,DP+1 DP is a 12-bit data register that stores the program ROM address as pointer for the ROM code data. User has to initially load ROM address into DP with instructions "STADPL", and "STADPM, STADPH", then to obtain the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI". PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction. LDIA STADPL STADPM STADPH : LDL LDH LDAX STAMI LDAXI STAM ; ORG DATA #07h; #00h; #03h; ; [DP]L ← 07h ; [DP]M ← 07h ; [DP]H ← 07h, Load DP=777h ; ACC ← 6h ; RAM[30] ← 6h ; ACC ← 5h ; RAM[31] ← 5h 1777h 56h; DATA RAM ( 1012-nibble ) A total 1012 - nibble data RAM is available from address 000 to 3FFh Data RAM includes the zero page region, stacks and data areas. * This specification are subject to be changed without notice. 8.16.2001 6 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr Bank 0 Address P9=xx00B 000-00Fh 010-01Fh 020-02Fh 030-03Fh 040-04Fh 050-05Fh 060-06Fh 070-07Fh 080-08Fh 090-09Fh 0A0-0AFh 0B0-0BFh 0C0-0CFh 0D0-0DFh 0E0-0EFh 0F0-0FFh Bank 1 0 1 2 3 4 5 6 7 Level Level Level Level 0 4 8 12 Level 1 Level 5 Level 8 9 A Level 2 Level 6 Level 10 P9=xx01B 100-10Fh 110-11Fh : : 1E0-1EFh 1F0-1FFh Bank 2 B C D E F Level 3 Level 7 Level 11 : : COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 P9=xx10B 200-20Fh 210-21Fh 220-22Fh 230-23Fh 240-24Fh 250-25Fh 260-26Fh 270-27Fh 280-28Fh 290-29Fh 2A0-2AFh 2B0-2BFh 2C0-2CFh 2D0-2DFh 2E0-2EFh 2F0-2FFh Bank 3 P9=xx11B 300-30Fh 310-31Fh 320-32Fh 330-33Fh 340-34Fh 350-35Fh 360-36Fh 370-37Fh 380-38Fh 390-39Fh 3A0-3AFh 3B0-3BFh 3C0-3CFh 3D0-3DFh 3E0-3EFh 3F0-3FFh 8 ZERO PAGE * This specification are subject to be changed without notice. 8.16.2001 7 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim ZERO- PAGE: From 000h to 00Fh is the zero-page location. It is used as the zero-page address mode pointer for the instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y". PROGRAM EXAMPLE: To write immediate data "07h" to RAM [03] and to clear bit 2 of RAM [0Eh]. STD #07h, 03h ; RAM[03] ← 07h CLR 0Eh,2 ; RAM[0Eh]2 ← 0 STACK: There are 13 - level (maximum) stack levels that user can use for subroutine (including interrupt and CALL). User can assign any level be the starting stack by providing the level number to stack pointer (SP). When an instruction (CALL or interrupt) is invoked, before enter the subroutine, the previous PC address is saved into the stack until returned from those subroutines, the PC value is restored by the data saved in stack. DATA AREA: Except the area used by user's application, the whole RAM can be used as data area for storing and loading general data. ADDRESSING MODE The 1012 nibble data memory consists of four banks (bank 0 ~ bank 3). There are 244x4 bits (address 000h~0F3h) in bank 0 and 768x4 bits (address 100h ~ 3FFh) in bank 1 ~ bank 3. The bank is selected by P9. P9 Initial value : * * 0 0 * * RBK RBK RAM bank 0 0 Bank0 0 1 Bank1 1 0 Bank2 1 1 Bank3 The Data Memory consists of three Address mode, namely (1) Indirect addressing mode: The address in the bank is specified by the HL registers. P9(1,0) HR LR RAM address * This specification are subject to be changed without notice. 8.16.2001 8 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "032h". OUT LDL LDH LDAM OUT LDL LDH STAM #0001B,P9 #3h #4h ; RAM bank1 ; LR← 3 ; HR← 4 ; Acc← RAM[134h] ; RAM bank0 ; LR← 2 ; HR← 3 ; RAM[023h]← Acc #0000B,P9 #2h #3h (2) Direct addressing mode: The address in the bank is directly specified by 8 bits code of the second byte in the instruction field. instruction field xxxxxxxx P9(1,0) xxxxxxxx RAM address PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h". OUT LDA OUT STA #0001B,P9 43h #0000B,P9 23h ; Acc← RAM[143h] ; RAM[023h]← Acc (3) Zero-page addressing mode: The zero-page is in the bank 0 (address 000h~00Fh). The address is the lower 4 bits code of the second byte in the instruction field. instruction field yyyy RAM address 00 0000 yyyy PROGRAM EXAMPLE: Write immediate "0Fh" to RAM address "005h". STD #0Fh, 05h ; RAM[05h]← 0Fh * This specification are subject to be changed without notice. 8.16.2001 9 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT y iminar l e r P PROGRAM COUNTER (16K ROM) Program counter ( PC ) is composed by a 13-bit counter, which indicates the next executed address for the instruction of program ROM instruction. For BRANCH and CALL instructions, PC is changed by instruction indicating. PC only can indicate the address from 0000h-1FFFh. The bank number is decided by P3. (1) Branch instruction: SBR a Object code: 00aa aaaa Condition: SF=1; PC ← PC 12-6.a ( branch condition satisified ) PC Hold original PC value+1 a a a a a a SF=0; PC← PC +1( branch condition not satisified ) PC Original PC value + 1 LBR a Object code: 1100 aaaa aaaa aaaa Condition: SF=1; PC ← PC 12.a ( branch condition satisified ) PC Hold +2 a a a a a a a a a a a a SF=0; PC← PC +2( branch condition not satisified ) PC Original PC value + 2 SLBR a Object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1FFFh) 0101 0111 1100 aaaa aaaa aaaa (a:0000h~0FFFh) Condition: SF=1; PC ← a ( branch condition satisified ) PC a a a a a a a a a a a a a SF=0 ; PC ← PC + 3 ( branch condition not satisified ) PC Original PC value + 3 (2) Subroutine instruction: SCALL a Object code: 1110 nnnn Condition : PC ← a ; a=8n+6 ; n=1..Fh ; a=86h, n=0 PC 0 0 0 0 0 a a a a a LCALL a Object code: 0100 0aaa aaaa aaaa Condition: PC ← a * This specification are subject to be changed without notice. a a a 8.16.2001 10 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT PC 0 0 a a ary n i m i l e Pr a a a a a a a a a RET Object code: 0100 1111 Condition: PC ← STACK[SP]; SP + 1 PC The return address stored in stack RT I Object code: 0100 1101 Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1 PC The return address stored in stack (3) Interrupt acceptance operation: When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into PC. The interrupt vectors are as follows : INT0 (External interrupt from P8.2) PC 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 SPI (speech end interrupt) PC 0 0 0 TRGA (Timer A overflow interrupt) PC 0 0 0 0 0 TRGB (Time B overflow interrupt) PC 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 TBI (Time base interrupt) PC 0 0 0 INT1 (External interrupt from P8.0) PC 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 (4) Reset operation: PC 0 0 * This specification are subject to be changed without notice. 8.16.2001 11 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT (5) Other operations: inary Prelim For 1-byte instruction execution: PC + 1 For 2-byte instruction execution: PC + 2 For 3-byte instruction execution: PC + 3 ACCUMULATOR Accumulator(ACC) is a 4-bit data register for temporary data storage. For the arithematic, logic and comparative opertion.., ACC plays a role which holds the source data and result. FLAGS There are three kinds of flag, CF ( Carry flag ), ZF ( Zero flag ) and SF ( Status flag ), these three 1-bit flags are included by the arithematic, logic and comparative .... operation. All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after RTI instruction is executed. (1) Carry Flag ( CF ) The carry flag is affected by the following operations: a. Addition : CF as a carry out indicator, under addition operation, when a carry-out occures, the CF is "1", likewise, if the operation has no carry-out, CF is "0". b. Subtraction : CF as a borrow-in indicator, under subtraction operation, when a borrow occures, the CF is "0", likewise, if there is no borrow-in, the CF is "1". c. Comparision : CF as a borrow-in indicator for Comparision operation as in the subtraction operation. d. Rotation : CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation. e. CF test instruction : Under TFCFC instruction, the CF content is sent into SF then clear itself as "0". Under TTSFC instruction, the CF content is sent into SF then set itself as "1". (2) Zero Flag ( ZF ) ZF is affected by the result of ALU, if the ALU operation generates a "0" result, the ZF is "1", likewise, the ZF is "0". (3) Status Flag ( SF ) The SF is affected by instruction operation and system status. a. SF is initiated to "1" for reset condition. b. Branch instruction is decided by SF, when SF=1, branch condition is satisified, likewise, when SF = 0, branch condition is unsatisified. * This specification are subject to be changed without notice. 8.16.2001 12 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr PROGRAM EXAMPLE: Check following arithematic operation for CF, ZF, SF CF - LDIA #00h; LDIA #03h; ADDA #05h; ADDA #0Dh; ADDA #0Eh; ZF 1 0 0 0 0 SF 1 1 1 0 0 ALU The arithematic operation of 4-bit data is performed in ALU unit. There are 2 flags that can be affected by the result of ALU operation, ZF and SF. The operation of ALU is affected by CF only. ALU STRUCTURE ALU supported user arithematic operation functions, including Addition, Subtraction and Rotaion. DATA BUS ALU ZF CF SF ALU FUNCTION (1) Addition: ALU supports addition function with instructions ADDAM, ADCAM, ADDM #k, ADD #k,y .... . The addition operation affects CF and ZF. Under addition operation, if the result is "0", ZF will be "1", otherwise, ZF will be "0". When the addition operation has a carry-out, CF will be "1", otherwise, CF will be "0". EXAMPLE: Operation 3+4=7 7+F=6 0+0=0 8+8=0 Carry 0 1 0 1 Zero 0 0 1 1 (2) Subtraction: ALU supports subtraction function with instructions SUBM #k, SUBA #k, SBCAM, DECM... . The subtraction operation affects CF and ZF. Under subtraction operation, if the result is negative, CF will be "0", and a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of subtraction operation is "0", the ZF is "1", likewise, ZF is "1". * This specification are subject to be changed without notice. 8.16.2001 13 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT EXAMPLE: Operation 8-4=4 7-F= -8(1000) 9-9=0 inary Prelim Carry 1 0 1 Zero 0 0 1 (3) Rotation: Two types of rotation operation are available, one is rotation left, the other is rotation right. RLCA instruction rotates Acc value counter-clockwise, shift the CF value into the LSB bit of Acc and hold the shift out data in CF. MSB LSB ACC CF RRCA instruction operation rotates Acc value clockwise, shift the CF value into the MSB bit of Acc and hold the shift out data in CF. MSB LSB ACC CF PROGRAM EXAMPLE: To rotate Acc clockwise (right) and shift a "1" into the MSB bit of Acc. TTCFS; CF ← 1 RRCA; rotate Acc right and shift CF=1 into MSB. HL REGISTER HL register are two 4-bit registers, they are used as a pair of pointer for the RAM memoryaddress. They are used as also 2 independent temporary 4-bit data registers. For certain instructions, L register can be a pointer to indicate the pin number (Port4 only). HL REGISTER STRUCTURE 3 2 1 0 3 2 1 0 H REGISTER L REGISTER HL REGISTER FUNCTION (1) HL register is used as a temporary register for instructions : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH. PROGRAM EXAMPLE: Load immediate data "5h" into L register, "0Dh" into H register. LDL #05h; LDH #0Dh; (2) HL register is used as a pointer for the address of RAM memory for instructions : LDAM, STAM, STAMI .. PROGRAM EXAMPLE: Store immediate data "#0Ah" into RAM of address 35h. * This specification are subject to be changed without notice. 8.16.2001 14 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT LDL #5h; LDH #3h; STDMI #0Ah; RAM[35] ← Ah ary n i m i l e Pr (3) L register is used as a pointer to indicate the bit of I/O port for instructions : SELP, CLPL, TFPL, (When LR = 0 indicate P4.0) PROGRAM EXAMPLE: To set bit 0 of Port4 to "1" LDL #00h; SEPL ; P4.0 ← 1 STACK POINTER (SP) Stack pointer is a 4-bit register that stores the present stack level number. Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition. When a new subroutine is received, the SP is decreased by one automatically, likewise, if returning from a subroutine, the SP is increased by one. The data transfer between ACC and SP is done with instructions "LDASP" and "STASP". DATA POINTER (DP) Data pointer is a 12-bit register that stores the ROM address can indicating the ROM code data specified by user (refer to data ROM). CLOCK AND TIMING GENERATOR The clock generator is supported by a dual clock system. The high-frequency oscillator is internal oscillator. The low-frequency oscillator may be sourced from crystal, the working frequency is 32 KHz. CLOCK GENERATOR STRUCTURE There are two clock generator for system clock control unit, P14 is the status register that hold the CPU status. P16, P19 and P22 are the command register for system clock mode control. CLK High-frequency generator fc LXIN LXOUT Low-frequency generator P14 System clock mode control fs P16 P19 P22 System control LXIN R VDD LXIN LXOUT Crystal connection open LXOUT RC oscillator connection R=2.2MΩ * This specification are subject to be changed without notice. 8.16.2001 15 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim SYSTEM CLOCK MODE CONTROL The system clock mode controller can start or stop the high-frequency and low-frequency clock oscillator and switch between the basic clocks. EM73A89B has four operation modes (DUAL, SLOW, IDLE and STOP operation modes). STOP operation mode I/O wakeup High osc : stopped Low osc : stopped Command (P16) Reset Reset Command (P16) Command (P22) Command (P22) Reset release RESET operation High osc : oscillating Low osc : oscillating NORMAL operation mode Reset SLOW operation mode High osc : stopped Low osc : oscillating Command (P19) Reset I/O or internal timer wakeup IDLE (CPU stops) High osc : stopped Low osc : oscillating Operation Mode NORMAL SLOW IDLE STOP Oscillator System Clock High, Low frequency High frequency clock Low frequency Low frequency clock Low frequency CPU stops None CPU stops Available function LCD, speech, HTC. LCD, HTC LCD All disable One instruction cycle 8 / fc 4 / fs - DUAL OPERATION MODE The 4-bit µc is in the DUAL operation mode when the CPU is reseted. This mode is dual clock system (high-frequency and low-frequency clocks oscillating). It can be changed to SLOW or STOP operation mode with the command register (P22 or P16). LCD display, speech synthesizer and sound generator are available for the DUAL operation mode. SLOW OPERATION MODE The SLOW operation mode is single clock system (low-frequency clock oscillating). It can be changed to the DUAL operation mode with the command register (P22), STOP operation mode with P16 and IDEL operation mode with P19. LCD display is available for the SLOW operation mode. Speech synthesizer and sound generator are disabled in this mode. * This specification are subject to be changed without notice. 8.16.2001 16 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT P22 3 * 2 * 1 * SOM 0 1 P14 3 ACT 0 SOM ary n i m i l e Pr Initial value : ***0 Select operation mode DUAL operation mode SLOW operation mode 2 WKS CPUS 0 1 1 0 SINT CPUS Initial value : 0000 CPU status DUAL operation mode SLOW operation mode WKS 0 1 Wakeup status Wakeup not by internal timer Wakeup by internal timer Port14 is the status register for CPU. P14.0 (CPU status) is a read-only bit. P14.2 (wakeup status) will be set as "1" when CPU is waked by internal timer. P14.2 will be cleared as "0" when user out data to P14. P14.1 is the interrupt source selector (refer to interrupt). P14.3 is the speech acknowledge signal (refer to speech synthesizer control). IDLE OPERATION MODE The IDLE operation mode suspends all CPU functions except the low-frequency clock oscillation and the LCD driver. It keeps the internal status with low power consumption without stopping the slow clock oscillator and LCD display. LCD display is available for the IDLE operation mode. The high speed counter and speech synthesizer are disabled in this mode. The IDLE operation mode will be wakeup and return to the SLOW operation mode by the internal timing generator or I/O pins (P0(0..3)/WAKEUP 0..3 and P8(0..3)/WAKEUPA..D). P19 3 2 IDME IDME 0 1 * * 1 0 SIDR Enable IDLE mode Enable IDLE mode no function Initial value : 0000 SIDR 0 0 0 1 1 0 1 1 Select IDLE releasing condition P0(0..3), P8(0..3) pin input P0(0..3), P8(0..3) pin input and 1 sec signal P0(0..3), P8(0..3) pin input and 0.5 sec signal P0(0..3), P8(0..3) pin input and 15.625 ms signal STOP OPERATION MODE The STOP operation mode suspends system operation and holds the internal status immediately before the suspension with low power consumption. This mode will be released by reset or I/O pins (P0(0..3)/ WAKEUP 0..3 or P8(0..3)/WAKEUP A..D). LCD display, high speed counter and speech synthesizer are disabled in this mode. * This specification are subject to be changed without notice. 8.16.2001 17 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT P16 3 * 2 SWWT 1 0 1 * * * 1 SWWT 0 inary Prelim Initial value : *000 Enable STOP mode Enable STOP mode no function GENERAL PURPOSE REGISTER (P10) P10 is a 4-bit general purpose register which can be read, written and rested by all I/O instructions. (including : INA, INM, OUT, OUTA, OUTM, SEP, CLP, TTP, TFP) PROGRAM EXAMPLE: CHIP ROM16K ;--------RAM define area----------------- DSEG ORG 10H HLBUF: RES 2 ; HL buffer for interrupt P9BUF: RES 1 ; P9 (RAM bank) buffer for interrupt : ;----------Interrupt subroutine-------------------CSEG ORG 004H LBR SPI : SPI: OUTA P10 ; save Acc to general purpose register P10 INA P9 OUT #0000B,P9 STA P9BUF ; save RAM bank to P9BUF EXHL HLBUF ; save HL to HLBUF : : EXHL HLBUF ; restore HLBUF to HL LDA P9BUF ; resotre P9BUF to RAM bank OUTA P9 INA P10 ; restore register P10 to Acc RTI * This specification are subject to be changed without notice. 10 instruction bytes 10 instruction bytes 8.16.2001 18 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr TIME BASE INTERRUPT (TBI) The time base can be used to generate a single fixed frequency interrupt. Eight types of frequencies can be selected with the "P25" setting. P25 3 2 1 0 initial value : 0000 0 0 0 0 0 1 1 1 1 1 P25 0 x 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 x x 0 1 0 1 0 1 0 1 x NORMAL operation mode Interrupt disable Interrupt frequency LXIN / 23 Hz Interrupt frequency LXIN / 215 Hz Interrupt frequency LXIN / 25 Hz Interrupt frequency LXIN / 214 Hz Interrupt frequency LXIN / 21 Hz Interrupt frequency LXIN / 26 Hz Interrupt frequency LXIN / 28 Hz Interrupt frequency LXIN / 210 Hz Reserved SLOW operation mode Interrupt disable Reserved Interrupt frequency LXIN / 215 Hz Reserved Interrupt frequency LXIN / 214 Hz Reserved Interrupt frequency LXIN / 26 Hz Interrupt frequency LXIN / 28 Hz Interrupt frequency LXIN / 210 Hz Reserved TIMER / COUNTER (TIMERA, TIMERB) Timer/counters support three special functions: 1. Even counter 2. Timer. 3. Pulse-width measurement. These three functions can be executed by 2 timer/counter independently. With timerA, the counter data is saved in timer register TAH, TAM, TAL. User can set counter initial value and read the counter value by instruction "LDATAH(M,L)" and "STATAH(M,L)". With timer B register is TBH, TBM, TBL and the W/R instruction are "LDATBH (M,L)" and "STATBH (M,L)". The basic structure of timer/counter is composed by two identical counter module, these two modules can be set initial timer or counter value to the timer registers, P28 and P29 are the command registers for timerA and timer B, user can choose different operation modes and internal clock rates by setting these two registers. When timer/counter overflows, it will generate a TRGA(B) interrupt request to interrupt control unit. INTERRUPT CONTROL TRGA request DATA BUS P8.3/ TRGA internal clock 12 BIT COUNTER 12 BIT COUNTER EVENT COUNTER CONTROL EVENT COUNTER CONTROL TIMER CONTROL TIMER CONTROL PULSE-WIDTH MEASUREMENT CONTROL P28 TRGB request TMSA IPSA PULSE-WIDTH MEASUREMENT CONTROL P29 * This specification are subject to be changed without notice. TMSB P8.1/ TRGB internal clock IPSB 8.16.2001 19 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim TIMER/COUNTER CONTROL P8.1/TRGB, P8.3/TRGA are the external timer inputs for timerB and timerA, they are used in event counter and pulse-width measurement mode. Timer/counter command port: P28 is the command port for timer/counterA and P29 is for the timer/ counterB. P28, P29 3 2 1 0 Initial value : 0000 TMSA(B) IPSA(B) TMSA(B) 00 01 10 11 Mode selection Stop Event counter mode Timer mode Pulse width measurement mode IPSA Clock rate selection NORMAL mode SLOW mode Reserved LXIN/23 HZ LXIN/27 HZ LXIN/27 HZ LXIN/211 HZ LXIN/211 HZ 15 LXIN/2 HZ LXIN/215 HZ 00 01 10 11 IPSB 00 01 10 11 Clock rate selection NORMAL mode SLOW mode Depend on high speed timer/counter LXIN/25 HZ LXIN/25 HZ LXIN/29 HZ LXIN/29 HZ 13 LXIN/2 HZ LXIN/213 HZ TIMER/COUNTER FUNCTION Timer/counterA,B are programmable for timer, event counter and pulse width measurement mode. Each timer/counter can execute any of these functions independently. EVENT COUNTER MODE Under event counter mode, the timer/counter is increased by one at any rising edge of P8.1/TRGB for timerB (P8.3/TRGA for timer A). When timerB (timerA) counts overflow, it will provide an interrupt request TRGB (TRGA) to interrupt control unit. P8.1/TRGB (P8.3/TRGA) TimerB (TimerA) value n n+1 n+2 n+3 n+4 n+5 n+6 PROGRAM EXAMPLE: Enable timerA with P28 LDIA OUTA #0100b; P28 ; Enable timerA with event counter mode * This specification are subject to be changed without notice. 8.16.2001 20 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr TIMER MODE Under timer mode, the timer/counter is increased by one at any rising edge of internal pulse. User can choose up to 4 types of internal pulse rate by setting IPSB for timerB (IPSA for timerA). When timer/counter counts overflow, an interrupt request will be sent to interrupt control unit. Internal pulse TimerB (TimerA )value n n+1 n+2 n+3 n+4 n+5 n+6 n+7 PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock LXlN=32KHz LDIA #0100B EXAE EICIL 110111b LDIA #0Ah; STATAL; LDIA #00h; STATAM; LDIA #0Fh; STATAH; LDIA #1000B; OUTA P28 NOTE: ; ; enable mask 2 ; interrupt latch ←0, enable EI ; enable timerA with internal pulse rate: LXIN/23 Hz The preset value of timer/counter register is calculated as following procedure. Internal pulse rate: LXIN/23 ; LXIN = 32KHz The time of timer counter count one = 23 /LXIN = 8/32768=0.244ms The number of internal pulse to get timer overflow = 60 ms/0.244ms = 245.901= 0F6h The preset value of timer/counter register = 1000h - 0F6h = F0Ah PULSE WIDTH MEASUREMENT MODE Under the pulse width measurement mode, the counter is incresed at the rising edge of internal pulse during external timer/counter input (P8.1/TRGB, P8.3/TRGA) in high level, interrupt request is generated as soon as timer/counter count overflow. P8.1/TRGB(P8.3/TRGA) Internal pulse TimerB(TimerA) value n n+1 n+2 n+3 n+4 n+5 PROGRAM EXAMPLE: Enable timerA by pulse width measurement mode. LDIA OUTA #1100b ; P28 ; Enable timerA with pulse width measurement mode. * This specification are subject to be changed without notice. 8.16.2001 21 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim INTERRUPT FUNCTION Six interrupt sources are available, 2 from external interrupt sources and 4 from internal interrupt sources. Multiple interrupts are admitted according to their priority. Type Interrupt source Priority Interrupt Interrupt Latch Enablecondition ProgramROM entry address External Internal Internal Internal Internal External External interrupt (INT0) Speech or HTC interrupt (SPI or HTCI) TimerA overflow interrupt (TRGA) TimerB overflow interrupt (TRGB) Time base interrupt(TBI) Externalinterrupt(INT1) 1 2 3 4 5 6 002h 004h 006h 008h 00Ah 00Ch IL5 IL4 IL3 IL2 IL1 IL0 EI=1 EI=1,MASK3=1 EI=1,MASK2=1 EI=1,MASK1=1 EI=1, MASK0=1 INTERRUPT STRUCTURE MASK0 MASK1 MASK1 MASK2 MASK3 INT1 r0 Reset by system reset and program instruction IL0 TBI r1 TRGB r2 TRGA r3 IL1 IL2 IL3 SPI or HTCI r4 IL4 INT0 r5 IL5 Priority checker Reset by system reset and program instruction Set by program instruction EI Interrupt request Entry address generator Interrupt entry address Interrupt controller: IL0-IL5 : Interrupt latch. Hold all interrupt requests from all interrupt sources. IL's can not be set by program, but can be reset by program or system reset, so IL can only decide which interrupt source can be accepted. MASK0-MASK3 : Except INT0, MASK register may permit or inhibit all interrupt sources. EI : Enable interrupt Flip-Flop may promit or inhibit all interrupt sources, when interrupt occurs, EI is auto cleared to "0", after RTI instruction is executed, EI is auto set to "1" again. Priority checker : Check interrupt priority when multiple interrupts occur. * This specification are subject to be changed without notice. 8.16.2001 22 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT INTERRUPT OPERATION ary n i m i l e Pr The procedure of interrupt operation: 1. Push PC and all flags to stack. 2. Set interrupt entry address into PC. 3. Set SF = 1. 4. Clear EI to inhibit other interrupts occur. 5. Clear the IL with which interrupt source has already been accepted. 6. Excute interrupt subroutine from the interrupt entry address. 7. CPU accept RTI, restore PC and flags from stack. Set EI to accept other interrupt requests. PROGRAM EXAMPLE: To enable interrupt of "INT0, TRGA" LDIA EXAE EICIL #0100B ; ; set mask register "0100b" 010111B ; enable interrupt F.F. and clear IL3 and IL5 INTERRUPT SOURCE SELECTION REGISTER P14 3 2 1 0 Initial value : 0000 ACT WKS SINT CPUS P14.1 is the interrupt source selection register for speech ending interrupt (SPI) and high speed counter overflow interrupt (HTCI) selection. When SINT=0, the program address "0004H" is the interrupt entry address of SPI. When SINT=1, the program address "0004H" is the interrupt entry address of HTCI. P14.0 and P14.2 are the CPU flages (refer to system operation mode). P14.3 is the speech acknowledge signal (refer to speech synthesizer control). HIGH SPEED COUNTER EM73A89B has one high speed counter for resistor to frequency oscillation mode, melody mode and auto load timer mode. This function is available for the DUAL and SLOW operation mode. The resistor to frequency oscillation (RFO) circuit as show below : P18(1..0) P18(3..2) P13 P12 P4.0(RX) P4.2(RY) P4.3(RZ) MUX Resistor FRF/2X FRF to Counter 8-bit Counter frequency oscillator P20(1..0) P20(3..2) P17 Mode Rate VCR HTCI interrupt TCB PWM ckt or D/A clock gating rate rate * This specification are subject to be changed without notice. 8.16.2001 23 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim CONTROL OF HIGH SPEED COUNTER The high speed counter is controlled by the command registers (P20, P18) : P20 3 1 0 Initial value : 0000 MODE RATE MODE 0 0 0 1 1 0 1 1 Selection of HTC mode Disable HTC Auto load timer mode Melody mode Resistor to frequency oscillation mode RATE ( Hz ) Internal pulse rate / Counter start request frequency Resistor to frequency Auto load timer mode / oscillation mode Melody mode internal pulse rate CLK / 2" LXIN / 2$ LXIN / 2 CLK / 2# " LXIN / 2 CLK / 2$ LXIN / 2# CLK / 2% 0 0 1 1 P18 2 3 0 1 0 1 2 1 0 Initial value : 0000 RFIP RFIN RFIP 0 0 0 1 1 0 1 1 Input frequency of RFO F4. F4. / 4 F4. / 16 F4. / 64 RFIN 0 0 0 1 1 0 1 1 Selection of RFO Pin Normal I/O P4.0 (RX) for RFO P4.2 (RY) for RFO P4.3 (RZ) for RFO P12 and P13 are the 8-bit binary counter registers of the HTC. P12 is lower nibble register and P13 is higher nibble register. P13 3 2 1 0 Higher nibble register P12 3 2 1 0 Lower nibble register Initial value : 0000 0000 The HTC can be set initial value and send counter value to counter registers (P13 and P12), P20 and P18 are the command ports for HTC, user can choose different operation mode and different internal clockrate by setting the port. The timer/counter increase one at the rising edge of internal pulse. The HTC can generate an overflow interrupt (HTCI) when it overflows. The HTCI can't be generated when the HTC is in the melody mode or disabled. * This specification are subject to be changed without notice. 8.16.2001 24 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr 8-BIT BINARY COUNTER Write the preset value to the registers The value of 8-bit binary counter can be presetted by P13 and P12. The value of registers can be loaded into the 8-bit binary counter when the counter starts counting or occurs overflow. When the 8-bit binary counter overflows, the HTCI interrupt will be generated. If you write values to the registers before the next overflow occurs, the preset value can be changed. Read the count value from the registers The count value of 8-bit binary counter can be read out from P13 and P12. The value is unstable when you read out the value during counting. Thus, you must disable the counter before reading out the value. 20-BIT COUNTER FUNCTION The 8-bit binary counter is connected to TCB which is one 12-bit general counter and becomes to the 20bit counter. The TCB increases one when the 8-bit binary counter overflows and generats an overflow interrupt (TRGB) when the TCB overflows. The TRGB cannot be generated when the HTC is in the melody or disable. FUNCTION OF HIGH SPEED COUNTER The HTC has three modes which are RFO mode, melody mode and auto load timer mode. The HTC is disabled when the CPU is reseted or in the STOP/IDLE operation mode. Users must enable it by yourself when the CPU is waked up. Resistor to frequency oscillation mode In this mode, the HTC is counted by the rising edges of input pulses from P4.1 (CS) and the value of window gate width is specified by P20. In this case, the window gate width interval is from the time base output fall to rise and the value of window gate width setting is the same as the time base interrupt frequency. The time base can be generated a fixed frequency interrupt when the time base interrupt (TBI) is enabled. The content of the HTC can be read and initialized by the TBI interrupt service routine. HTC input pulse Time base 8-bit binary counter n n+1 00 01 FF 00 01 8-bit binary counter overflow 00 TCB counter Program Disable HTC and read data. Enable HTC and write data. 001 Window gate width TBI interrupt service routine ex. TBI interrupt frequency is LXIN/215 Hz (P25=0101B). The pulse rate of RFO is LXIN/215 Hz (P20=1111B). The window gate width of RFO is 214/LXIN sec. (LXIN=32KHz) * This specification are subject to be changed without notice. 8.16.2001 25 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim PROGRAM EXAMPLE DSEG ORG 00H HLBUF: RES 2 P9BUF: RES 1 RFCON: RES 1 : CSEG ORG LBR ORG LBR : TBI: OUTA INA OUT STA EXHL CMP B STD LDIA OUTA OUTA STATBL STATBM STATBH B 00H MAIN 0AH TBI P10 P9 #0,P9 P9BUF HLBUF #00H,RFCON TBI1 #01H,RFCON #00H P13 P12 ; initial jump ; timebase interrupt vector address ; timebase interrupt service routine ; initial TCB & HTC register TBIEND * This specification are subject to be changed without notice. 8.16.2001 26 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr TBI1: OUTA INA OUT STA EXHL LDIA OUTA INA STA INA STA LDATBL STA LDATBM STA LDATBH STA P10 P9 #0,P9 P9BUF HLBUF #00H P20 P12 00H P13 01H ; store the counter value to RAM[00] - RAM[04] 02H 03H 04H TBIEND: EXHL LDA OUTA INA RTI HLBUF P9BUF P9 P10 MAIN: #00H,RFCON #0001B P18 #0010B STD LDIA OUTA LDIA EXAE EICIL LDIA OUTA LDIA OUTA : ; disable RFO before reading the counter value 0 #1111B P20 #0101B P25 ; main program ; P4.0 (RX) output ; enable timebase interrupt 15 ; the pulse rate of RFO=2 /LXIN sec. ; enable timebase, interrupt frequency : LXIN / 215 Hz * This specification are subject to be changed without notice. 8.16.2001 27 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim Auto load timer mode In this mode, there are four different internal pulse rates can be selected by P20. The HTC loads the initial values by the counter registers (P12, P13) and increases at the rising edges of internal pulse generated by the time base. The value of TCB increases one when the high speed counter overflows and generates an overflow interrupt (TRGB) when the TCB overflows. This mode is only available for DUAL operation mode. PROGRAM EXAMPLE : LDIA #00H STATBL STATBM STATBH OUTA P13 OUTA P12 OUTA P18 LDIA #0111B OUTA P20 : LDIA #00H OUTA P20 INA P12 STA 00H INA P13 STA 01H LDATBL STA 02H LDATBM STA 03H LDATBH STA 04H ; initial TCB & HTC register ; enable timer mode, internal pulse rate : CLK/27 ; disable timer mode ; store the counter value to RAM[00] - RAM[04] Melody mode In the melody mode, HTC will output the square wave to the PWM circuit or D/A converter. The 8-bit tone frequency register is P13 and P12. The tone frequency will be changed when users output the different data to P12. Thus, the data must be output to P13 before P12 when users want to change the 8-bit tone frequency (TF). This mode is only available for DUAL operation mode. P13 3 2 1 0 Higher nibble register P12 3 2 1 0 Initial value : 0000 0000 ( TF ) Lower nibble register ** FTONE = [ (CLK / 2:) / (100H - TF) ] / 2, TF = 0 ~ 255 ** Example : CLK = 4.6MHz, RATE = 10, TF = 11001110 B= 0CEH. FTONE = [ (4.6MHz / 25) / (100H - 0CEH) ] / 2 = 1430 Hz. * This specification are subject to be changed without notice. 8.16.2001 28 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr Volume control register (P17) The are 16 levels of volume for sound generator. P17 is the volume control register. Port17 Initial value : 0000 3 2 1 0 VCR VCR ts/tp 1 1 1 1 15/16 ts 1 1 1 0 14/16 1 tp= CLK/64 (CLK=4.6MHz) : : 0 0 0 1 1/16 tp 0 0 0 0 0/16 PROGRAM EXAMPLE: LDIA OUTA LDIA OUTA LDIA OUTA LDIA OUTA #0CH P13 #0EH P12 #0111B P17 #1010B P20 ; volume control ; 1430 Hz tone output LCD DRIVER It can directly drive the liquid crystal display (LCD) and has 64 segment pins, 16 or 32 common pins by mask option. There are total 64x16 or 64x32 dots can be display. The V1~V5, VA and VB pins have to connect the capacitors for LCD voltage multiplier. Display dots Bias Duty LCD display RAM I/O or LCD pin by mask option 16 common pins 16x64 dots 1/5 bias 1/16 duty Bank2 (P9=xx10B) COM0..15, SEG0..59, P1[0..3]/SEG63..60 * This specification are subject to be changed without notice. 32 common pins 32x64 dots 1/5 bias 1/32 duty Bank2(P9=xx10B), Bank3(P9=xx11B) COM0..31, SEG0..43, P7[0..3]/SEG47..44, P6[0..3]/SEG51..48, P5[0..3]/SEG55..52, P2[0..3]/SEG59..56, P1[0..3]/SEG63..60 8.16.2001 29 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary relimin P LCD driver control command register (P27) : Port27 3 2 1 0 LDC VREF Initial value : 0000 LDC LCD display control 0 LCD display disable 1 LCD display enable * : Don't care. *1 : V5 is LCD working voltage (suggestion only). VREF 000 001 010 011 100 101 11* Reference voltage 0.85V 0.90V 0.95V 1.00V 1.05V Reserved Reserved V5(1/5bias)*1 4.25V 4.50V 4.75V 5.00V 5.25V Reserved Reserved Example : LDIA OUTA : LDIA OUTA #1001B P27 ; enable LCD. #0000B P27 ; disable LCD. LCD display data area: The LCD display data is stored in the display data area of the data memory (RAM). Bank 2 Address 0 1 2 3 4 5 6 7 8 9 A B C D E F COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 P9=xx10B 200-20Fh 210-21Fh 220-22Fh 230-23Fh 240-24Fh 250-25Fh 260-26Fh 270-27Fh 280-28Fh 290-29Fh 2A0-2AFh 2B0-2BFh 2C0-2CFh 2D0-2DFh 2E0-2EFh 2F0-2FFh Bank 3 P9=xx11B300-30Fh 310-31Fh 320-32Fh 330-33Fh 340-34Fh 350-35Fh 360-36Fh 370-37Fh 380-38Fh 390-39Fh 3A0-3AFh 3B0-3BFh 3C0-3CFh 3D0-3DFh 3E0-3EFh 3F0-3FFh * This specification are subject to be changed without notice. 8.16.2001 30 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr LCD waveform : (1)1/32 duty, 1/5 bias SEG1 SEG0 COM0 V5 V4 V3 V2 V1 VSS COM0 COM1 : : : : COM31 COM1 V5 V4 V3 V2 V1 VSS COM31 : ON : OFF V5 V4 V3 V2 V1 VSS SEG0 V5 V4 V3 V2 V1 VSS SEG0 - COM0 ON V5 V4 V3 V2 V1 VSS -V1 -V2 -V3 -V4 -V5 SEG0 - COM1 OFF V5 V4 V3 V2 V1 VSS -V1 -V2 -V3 -V4 -V5 Frame freq.=64Hz * This specification are subject to be changed without notice. 8.16.2001 31 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim (2)1/16 duty, 1/5 bias SEG1 SEG0 COM0 V5 V4 V3 V2 V1 VSS COM0 COM1 : : : : COM15 COM1 V5 V4 V3 V2 V1 VSS COM15 : ON V5 V4 V3 V2 V1 VSS : OFF SEG0 V5 V4 V3 V2 V1 VSS SEG0 - COM0 ON V5 V4 V3 V2 V1 VSS -V1 -V2 -V3 -V4 -V5 SEG0 - COM1 OFF V5 V4 V3 V2 V1 VSS -V1 -V2 -V3 -V4 -V5 Frame freq.= 64Hz * This specification are subject to be changed without notice. 8.16.2001 32 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr SPEECH SYNTHESIZER Set tone freq. Set melody mode P12,13 Write Set tone amplitude P20 Write BZ1/VO P17 Write D/A PWM Sound effect generator speech ROM P11 Write P11 Read speech decoder BZ2 SPI interrupt P14.3 read P24 Write P23 Write Set data address (write 5 times) Read data Set speech address (write 4 times) Speech active Set sample rate Block diagram of speech and sound effect EM73A89B speech synthesizer operates as following : 1. Send the speech start address to the address latch by writing P24 four times. 2. Choose the sampling rate, enable the speech synthesizer by writing P23. 3. The ROM address counters send the ROM address A6 .. A19 to the speech ROM. 4. ACT is the speech acknowledge signal. When the speech synthesizer has voice output. ACT is high. When ACT is changed from high to low, the speech synthesizer can generate the speech ending interrupt SPI. The ACT signal can be read from P14.3. SPEECH SYNTHESIZER CONTROL Speech sample rate control register (P23 write) : P23 3 2 1 0 Initial value : 1111 SR SR 0000 0001 0010 0011 0100 0101 0110 0111 1*** Sample rate selection CLK/64/2/3 CLK/64/2/4 CLK/64/3/3 CLK/64/3/4 CLK/64/2/7 CLK/64/4/4 CLK/64/6/3 CLK/64/6/4 Disable speech port 23 -- initialization is "1111". port 24 -- initialization is pointed to the lownibble of start address latch. The frequency of CLK is decided by mask option. * This specification are subject to be changed without notice. 8.16.2001 33 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim Speech active flag (P14.3 read) : P14 3 2 1 0 Initial value : 0000 ACT WKS SINT CPUS ACT is the speech acknowledge signal. When the speech synthesizer has voice output, ACT is high. When ACT is high → low, the speech synthesizer can generate the speech ending interrupt SPI. P14(0,2) are CPU status flags (refer to CPU status). P14.1 is the interrupt source selector (refer to interrupt). P24 Speech start address register (P24 write) : 3 2 1 0 Initial value : 1111 Port 24 P24L1 A9 A8 A7 A6 P24L2 A13 A12 A11 A10 P24L3 A17 A16 A15 A14 P24L4 - A19 A18 Send the speech start address to the speech synthesizer by writing P24 four times. There is a pointer counter to point the address latch (P24L1, P24L2, P24L3, P24L4). It will increase one when write P24. So, the first time writing P24 to P24L1, the second time is P24L2, the third time is P24L3, the fourth time is P24L4 and the fifth time is P24L1 latch again, ... etc. The pointer counter point to P24L1 when CPU is reset or P23 is written. In the DUAL operation mode, the speech synthesizer is available. In the other operation modes, it is disable. PROGRAM EXAMPLE: CHIP ROM16K ;--------RAM define area----------------DSEG ORG 10H HLBUF: RES 2 P9BUF: RES 1 : ;----------Constant-------------------------ACT EQU 143 SPEECH EQU 43200H : ;----------Interrupt subroutine----------CSEG ORG 004H LBR SPI : SPI: OUTA P10 INA P9 OUT #0000B,P9 STA P9BUF EXHL HLBUF : : EXHL HLBUF LDA P9BUF OUTA P9 INA P10 RTI ; HL buffer for interrupt ; P9 (RAM bank) buffer for interrupt ; save Acc to general purpose register P10 ; save RAM bank to P9BUF ; save HL to HLBUF ; restore HLBUF to HL ; resotre P9BUF to RAM bank 10 instruction bytes 10 instruction bytes ; restore register P10 to Acc * This specification are subject to be changed without notice. 8.16.2001 34 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr ;----------Mainprogram------------------MAIN : WAIT : : LDIA OUTA LDIA OUTA LDIA OUTA LDIA OUTA LDIA OUTA LDIA OUTA : TTP B : #0000B P14 #SPEECH/40H P24 #SPEECH/400H P24 #SPEECH/4000H P24 #SPEECH/40000H P24 #0011B P23 ; select SPI interrupt ; set speech start address ; set sampling rate and start playing P14,3 WAIT ; wait speed end USING SPEECH ROM AS DATA ROM The speech ROM can be used for speech synthesizer and for data ROM simutaneously. First, write initial address to P11 five times, then you can read P11 to get data, and the address counter increases one automatically. The read operation should be all done before you leave normal mode and change to slow mode. Get speech ROM data (P11 read) : 3 2 1 0 Port 11 Set speech ROM address (P11 write) : 3 2 1 0 Port 11 P11L1 A3 A2 A1 A0 P11L2 A7 A6 A5 A4 PROGRAM EXAMPLE: DATA_ADR EQU : LDIA OUTA LDIA OUTA LDIA OUTA LDIA OUTA LDIA OUTA P11L3 P11L4 A11 A10 A9 A8 A15 A14 A13 A12 12345H P11L5 A19 A18 A17 A16 ; the start address of the speech ROM #DATA_ADR P11 #DATA_ADR/10H P11 #DATA_ADR/100H P11 #DATA_ADR/1000H P11 #DATA_ADR/10000H P11 * This specification are subject to be changed without notice. 8.16.2001 35 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim INA STA INA STA : P11 TEMP P11 TEMP+1 ; READ DATA ; read DATA_ADR WATCH-DOG-TIMER (WDT) Watch-dog-timer can help user to detect the malfunction (runaway) of CPU and give system a timeup signal every certain time. User can use the time up signal to give system a reset signal when system is fail. This function is available by mask option. If the mask option of WDT is enabled, it will stop counting when CPU is reseted or in the STOP operation mode. The basic structure of Watch-Dog-Timer control is composed by a 4-stage binary counter and a control unit. The WDT counter counts for a certain time to check the CPU status, if there is no malfunction happened, the counter will be cleared and continue counting. Otherwise, if there is a malfunction happened, the WDT control will send a WDT signal (low active) to reset CPU. The WDT checking period is assign by P21 (WDT command port). WDT counter LXIN/213 0 1 2 3 RESET pin counter clear request mask option WDT control P21 WDT command port P21 is the control port of watch-dog-timer, and the WDT time up signal is connected to RESET. Port 21 CWC 3 * 2 * 1 0 WDT Initial value :0000 CWC 0 1 Clear watchdog timer counter Clear counter then return to 1 Nothing WDT 0 1 Set watch-dog-timer detect time 3 x 213/LXIN = 3 x 213/32K Hz = 0.75 sec 7 x 213/LXIN = 7 x 213/32K Hz = 1.75 sec PROGRAM EXAMPLE To enable WDT with 7 x 213/LXIN detection time. LDIA #0001B OUTA P21 ; set WDT detection time and clear WDT counter : : * This specification are subject to be changed without notice. 8.16.2001 36 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT RESETTING FUNCTION ary n i m i l e Pr When CPU in normal working condition and RESET pin is held in low level for three instruction cycles at least, then CPU begins to initialize the whole internal states, when RESET pin changes to high level, CPU begins to work in normal condition. The CPU internal state during reset condition is as following table : Hardware condition in RESET state Program counter Status flag Interrupt enable flip-flop ( EI ) MASK0 ,1, 2, 3 Interrupt latch ( IL ) P3, 9, 10, 11, 12, 13, 14, 16, 18, 19, 20, 21, 22, 25, 27, 28, 29 P0, 1, 2, 4, 5, 6, 7, 8, 17, 23, 24 CLK, LXIN Initial value 0000h 01h 00h 00h 00h 00h 0Fh Start oscillation The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option. The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD. RESET * This specification are subject to be changed without notice. 8.16.2001 37 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim EM73A89B I/O PORT DESCRIPTION : Port 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 E E E I E E E E E I I I I Input function Input port , wakeup function Input port Input port ROM bank selection Input port Input port Input port Input port Input port, wakeup function, external interrupt input RAM bank selection General purpose register Read data register --CPU status, ACT flag -- Output function E E I E E E E E Output port / LCD segment pins Output port / LCD pins ROM bank selection Output port / RFO pins Output port / LCD pins Output port / LCD pins Output port / LCD pins Output port I I I I I I RAM bank selection General purpose register Data ROM address register High speed counter register High speed counter register CPU status, interrupt souce selector -STOP mode control register TONE volume control register HTC control register IDLE mode control register HTC control register WDT control register DUAL/SLOW mode control register Speech sampling rate register Speech start address register Timebase control register -LCD control register Timer/counter A control register Timer/counter B control register --- I I I I I I I I I I I I I * This specification are subject to be changed without notice. Note Low nibble High nibble 8.16.2001 38 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT APPLICATION CIRCUIT ary n i m i l e Pr 100 VBAT 0.1µF VBAT 0.1µF VDD 3V VDD2 P0.0 P0.1 SEG0~ SEG63 COM0~ COM31 LCD PANNEL VA P0.2 0.1µF VB BZ1 100Ω BZ2 RESET 0.1µF V5 V4 V3 V2 V1 LXOUT all 0.1µF 32.768KHz LXIN RESET 20P VSS CLK 0.022µF EM73A89B * This specification are subject to be changed without notice. 8.16.2001 39 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim RESET PIN TYPE TYPE RESET-A RESET mask option OSCILLATION PIN TYPE TYPE OSC-B TYPE OSC_G LXIN Crystal Osc. CLK Internal Osc. LXOUT TYPE OSC-H VDD LXIN RC Osc. INPUT PIN TYPE TYPE INPUT-A TYPE INPUT-B WAKEUP function mask option P0 /WAKEUP TYPE INPUT_A : mask option * This specification are subject to be changed without notice. 8.16.2001 40 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr I/O PIN TYPE TYPE I/O TYPE I/O-P path B Input data path A mask option Output Output TYPE I/O data data latch Special function output TYPE I/O-Q1 : mask option TYPE I/O-X1 path B Special function control input SEL path A TYPE I/O_Q1 I/O_N TYPE Input data Output Output data data : mask option Path A : Path B : latch For set and clear bit of port instructions, data goes through path A from output data latch to CPU. For input and test instructions, data from output pin go through path B to CPU and the output data latch will be set to high. * This specification are subject to be changed without notice. 8.16.2001 41 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim SEG57 116 115 SEG58 117 SEG59 SEG60/P1.3 SEG61/P1.2 SEG63/P1.0 SEG62/P1.1 122 121 120 119 118 V2 123 V1 124 V4 V5 126 125 V3 VB VA PAD DIAGRAM (16 COMMONS) 114 113 SEG31 1 112 SEG56 SEG30 2 111 SEG55 SEG29 3 110 SEG54 SEG28 4 109 SEG53 SEG27 5 108 SEG52 SEG26 6 107 SEG51 SEG25 7 106 SEG50 SEG24 8 105 SEG49 SEG23 9 104 SEG48 SEG22 10 103 SEG47 SEG21 11 102 SEG46 SEG20 12 101 SEG45 SEG19 13 100 SEG44 SEG18 14 99 SEG43 SEG17 15 98 SEG42 SEG16 16 97 SEG41 SEG15 17 96 SEG40 SEG14 18 95 SEG39 SEG13 19 94 SEG38 SEG12 20 93 SEG37 SEG11 21 92 SEG36 SEG10 22 91 SEG35 SEG9 23 90 SEG34 SEG8 24 89 SEG33 SEG7 25 88 SEG32 SEG6 26 87 P7.3 SEG5 27 86 P7.2 SEG4 28 85 P7.1 SEG3 29 84 P7.0 SEG2 30 83 P6.3 SEG1 31 82 P6.2 SEG0 32 81 P6.1 COM0 33 80 P6.0 COM1 34 79 P5.3 COM2 35 78 P5.2 COM3 36 77 P5.1 COM4 37 76 P5.0 COM5 38 75 P2.3 COM6 39 74 P2.2 COM7 40 73 P2.1 COM8 41 72 P2.0 COM9 42 71 LXOUT COM10 43 70 LXIN COM11 44 69 VDD COM12 45 68 CLK COM13 46 67 P4.0 COM14 47 66 P4.1 COM15 48 65 P4.2 VSS 49 64 P4.3 (0,0) 50 51 52 53 54 55 56 57 58 59 60 61 62 63 VDD2 BZ1/VO BZ2 VSS TEST RESET P8.3 P8.2 P8.1 P8.0 P0.3 P0.2 P0.1 P0.0 EM73A89B * This specification are subject to be changed without notice. 8.16.2001 42 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 X -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 * This specification are subject to be changed without notice. Y 2753.9 2623.9 2496.4 2371.4 2246.4 2121.4 1996.4 1873.9 1753.9 1633.9 1513.9 1393.9 1276.4 1161.4 1046.4 931.4 816.4 703.9 593.9 483.9 373.9 263.9 156.4 51.4 -53.6 -158.6 -263.6 -371.1 -481.1 -591.1 -701.1 -811.1 -923.6 -1038.6 -1153.6 -1268.6 -1383.6 -1501.1 -1621.1 -1741.1 8.16.2001 43 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 VSS VDD2 BZ1/VO BZ2 VSS TEST RESET P8.3 P8.2 P8.1 P8.0 P0.3 P0.2 P0.1 P0.0 P4.3 P4.2 P4.1 P4.0 CLK VDD LXIN LXOUT P2.0 P2.1 P2.2 P2.3 P5.0 P5.1 P5.2 P5.3 P6.0 X -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -763.3 -633.2 -483.2 -353.1 -237.9 -127.9 -17.9 92.1 202.1 312.1 422.1 532.1 642.1 759.6 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 * This specification are subject to be changed without notice. Y -1861.1 -1981.1 -2103.6 -2228.6 -2353.6 -2478.6 -2603.6 -2731.1 -2861.1 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -2861.1 -2731.1 -2603.6 -2478.6 -2353.6 -2228.6 -2103.6 -1981.1 -1861.1 -1741.1 -1621.1 -1501.1 -1383.6 -1268.6 -1153.6 -1041.1 -931.1 8.16.2001 44 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr Pad No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol P6.1 P6.2 P6.3 P7.0 P7.1 P7.2 P7.3 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60/P1.3 SEG61/P1.2 SEG62/P1.1 SEG63/P1.0 V2 X 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 715.0 605.0 495.0 385.0 275.0 165.0 55.0 -55.0 * This specification are subject to be changed without notice. Y -821.1 -711.1 -601.1 -491.1 -381.1 -271.1 -161.1 -53.6 51.4 156.4 263.9 373.9 483.9 593.9 703.9 816.4 931.4 1046.1 1161.4 1276.4 1393.9 1513.9 1633.9 1753.9 1873.9 1996.4 2121.4 2246.4 2371.4 2496.4 2623.9 2753.9 3120.0 3120.0 3120.0 3120.0 3120.0 3120.0 3120.0 3120.0 8.16.2001 45 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim Pad No. 121 122 123 124 125 126 Symbol V1 V4 V3 V5 VB VA X -165.0 -275.0 -385.0 -495.0 -605.0 -715.0 Y 3120.0 3120.0 3120.0 3120.0 3120.0 3120.0 Unit : um Chip size : 1810 x 6490um Note : For PCB layout, IC substrate must be floated or connected to Vss. * This specification are subject to be changed without notice. 8.16.2001 46 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT SEG57/P2.2 116 115 SEG58/P2.1 SEG59/P2.0 V2 SEG60/P1.3 SEG61/P1.2 117 SEG63/P1.0 122 121 120 119 118 V4 123 V1 124 SEG62/P1.1 126 125 V3 VB VA PAD DIAGRAM (32 COMMONS) V5 ary n i m i l e Pr 114 113 SEG31 1 112 SEG56/P2.3 SEG30 2 111 SEG55/P5.0 SEG29 3 110 SEG54/P5.1 SEG28 4 109 SEG53/P5.2 SEG27 5 108 SEG52/P5.3 SEG26 6 107 SEG51/P6.0 SEG25 7 106 SEG50/P6.1 SEG24 8 105 SEG49/P6.2 SEG23 9 104 SEG48/P6.3 SEG22 10 103 SEG47/P7.0 SEG21 11 102 SEG46/P7.1 SEG20 12 101 SEG45/P7.2 SEG19 13 100 SEG44/P7.3 SEG18 14 99 SEG43 SEG17 15 98 SEG42 SEG16 16 97 SEG41 SEG15 17 96 SEG40 SEG14 18 95 SEG39 SEG13 19 94 SEG38 SEG12 20 93 SEG37 SEG11 21 92 SEG36 SEG10 22 91 SEG35 SEG9 23 90 SEG34 SEG8 24 89 SEG33 SEG7 25 88 SEG32 SEG6 26 87 COM16 SEG5 27 86 COM17 SEG4 28 85 COM18 SEG3 29 84 COM19 SEG2 30 83 COM20 SEG1 31 82 COM21 SEG0 32 81 COM22 COM0 33 80 COM23 COM1 34 79 COM24 COM2 35 78 COM25 COM3 36 77 COM26 COM4 37 76 COM27 COM5 38 75 COM28 COM6 39 74 COM29 COM7 40 73 COM30 COM8 41 72 COM31 COM9 42 71 LXOUT COM10 43 70 LXIN COM11 44 69 VDD COM12 45 68 CLK COM13 46 67 P4.0 COM14 47 66 P4.1 COM15 48 65 P4.2 VSS 49 64 P4.3 (0,0) 53 54 55 56 57 58 59 60 61 62 63 TEST RESET P8.3 P8.2 P8.1 P8.0 P0.3 P0.2 P0.1 P0.0 VDD2 52 BZ2 51 VSS 50 BZ1/VO EM73A89B * This specification are subject to be changed without notice. 8.16.2001 47 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 X -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 * This specification are subject to be changed without notice. Y 2753.9 2623.9 2496.4 2371.4 2246.4 2121.4 1996.4 1873.9 1753.9 1633.9 1513.9 1393.9 1276.4 1161.4 1046.4 931.4 816.4 703.9 593.9 483.9 373.9 263.9 156.4 51.4 -53.6 -158.6 -263.6 -371.1 -481.1 -591.1 -701.1 -811.1 -923.6 -1038.6 -1153.6 -1268.6 -1383.6 -1501.1 -1621.1 -1741.1 8.16.2001 48 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 VSS VDD2 BZ1/VO BZ2 VSS TEST RESET P8.3 P8.2 P8.1 P8.0 P0.3 P0.2 P0.1 P0.0 P4.3 P4.2 P4.1 P4.0 CLK VDD LXIN LXOUT COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 X -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -780.0 -763.3 -633.2 -483.2 -353.1 -237.9 -127.9 -17.9 92.1 202.1 312.1 422.1 532.1 642.1 759.6 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 * This specification are subject to be changed without notice. Y -1861.1 -1981.1 -2103.6 -2228.6 -2353.6 -2478.6 -2603.6 -2731.1 -2861.1 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -3120.0 -2861.1 -2731.1 -2603.6 -2478.6 -2353.6 -2228.6 -2103.6 -1981.1 -1861.1 -1741.1 -1621.1 -1501.1 -1383.6 -1268.6 -1153.6 -1041.1 -931.1 8.16.2001 49 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim Pad No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol COM22 COM21 COM20 COM19 COM18 COM17 COM16 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44/P7.3 SEG45/P7.2 SEG46/P7.1 SEG47/P7.0 SEG48/P6.3 SEG49/P6.2 SEG50/P6.1 SEG51/P6.0 SEG52/P5.3 SEG53/P5.2 SEG54/P5.1 SEG55/P5.0 SEG56/P2.3 SEG57/P2.2 SEG58/P2.1 SEG59/P2.0 SEG60/P1.3 SEG61/P1.2 SEG62/P1.1 SEG63/P1.0 V2 X 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 780.0 715.0 605.0 495.0 385.0 275.0 165.0 55.0 -55.0 * This specification are subject to be changed without notice. Y -821.1 -711.1 -601.1 -491.1 -381.1 -271.1 -161.1 -53.6 51.4 156.4 263.9 373.9 483.9 593.9 703.9 816.4 931.4 1046.1 1161.4 1276.4 1393.9 1513.9 1633.9 1753.9 1873.9 1996.4 2121.4 2246.4 2371.4 2496.4 2623.9 2753.9 3120.0 3120.0 3120.0 3120.0 3120.0 3120.0 3120.0 3120.0 8.16.2001 50 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr Pad No. 121 122 123 124 125 126 Symbol V1 V4 V3 V5 VB VA X -165.0 -275.0 -385.0 -495.0 -605.0 -715.0 Y 3120.0 3120.0 3120.0 3120.0 3120.0 3120.0 Unit : um Chip size : 1810 x 6490um Note : For PCB layout, IC substrate must be floated or connected to Vss. * This specification are subject to be changed without notice. 8.16.2001 51 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim ABSOLUTE MAXIMUM RATINGS Items Sym. Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Ratings V DD V IN VO PD T OPR TSTG Conditions -0.5V to 3.6V -0.5V to VDD+0.5V -0.5V to VDD+0.5V 300mW -30oC to 70oC -55oC to 125oC TOPR=50 oC RECOMMANDED OPERATING CONDITIONS Items Sym. Supply Voltage Input Voltage Operating Frequency Ratings VDD V IH V IL FC Fs Conditions 2.2V to 3.6V 0.90xVDD to VDD 0V to 0.10xVDD 4.6MHz ~ 9.2MHz 32KHz CLK LXIN,LXOUT DC ELECTRICAL CHARACTERISTICS (VDD=3±0.3V, VSS=0V, TOPR=25oC) Parameters Sym. Min. Typ. Max. Unit Conditions Supply current Hysteresis voltage Input current I DD VHYS+ VHYSIIH I IL Output voltage Leakage current Input resistor VOH V OL ILO R IN - 0.5 1.2 mA - 45 40 12 1 - 35 30 7 0.1 -250 ±1 ±1 -500 µA µA µA µA V V µA µA µA - -20 -25 µA 2.4 - - V 2.0 2.4 - V 100 300 0.15 200 600 0.3 1 300 900 V µA KΩ KΩ 0.50VDD 0.20VDD 0.75VDD 0.40VDD * This specification are subject to be changed without notice. VDD=3.3V,DUAL mode,no load, Fc=4.6MHz ,Fs=32KHz VDD=3.3V,SLOW mode,Fs=32KHz, LCD on VDD=3.3V, IDLE mode, LCD on VDD=3.3V, IDLE mode, LCD off VDD=3.3V, STOP mode RESET, P0, P8 P0, RESET, VDD=3.3V,VIH=3.3/0V Open-drain, VDD=3.3V,VIH=3.3/0V Push-pull (normal current push-pull) VDD=3.3V, VIL=0.4V Push-pull (low current push-pull) VDD=3.3V, VIL=0.4V Push-pull, (high current push-pull) VDD=2.7V, IOH=-0.9mA Push-pull, (normal current push-pull) VDD=2.7V, IOH=-40µA VDD=2.7V, IOL=0.9mA Open-drain, VDD=3.3V, VO=3.3V P0, VDD=3.3V RESET, VDD=3.3V 8.16.2001 52 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr Output current of BZ1, BZ2 I OH I OL I OH I OL Output current of VO LCD reference V REF voltage 30 30 75 75 2 0.765 0.81 0.855 0.9 0.945 3 0.85 0.90 0.95 1.00 1.05 4 0.935 0.99 1.045 1.1 1.155 mA mA mA mA mA V V V V V * This specification are subject to be changed without notice. VDD=3.0V, VBZ=1.5V, mask option : small size VDD=3.0V, VBZ=1.5V, mask option : large size VDD=3.0V, vo=0.7V VDD=3.0V,no load,VREF=000 VDD=3.0V,no load,VREF=001 VDD=3.0V,no load,VREF=010 VDD=3.0V,no load,VREF=011 VDD=3.0V,no load,VREF=100 8.16.2001 53 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT INSTRUCTION TABLE inary Prelim (1) Data Transfer Mnemonic Object code ( binary ) Operation description LDA x 0110 1010 xxxx xxxx LDAM 0101 1010 LDAX 0110 0101 LDAXI 0110 0111 LDH #k 1001 kkkk LDHL x 0100 1110 xxxx xx00 LDIA #k 1101 kkkk LDL #k 1000 kkkk STA x 0110 1001 xxxx xxxx STAM 0101 1001 STAMD 0111 1101 STAMI 0111 1111 STD #k,y 0100 1000 kkkk yyyy STDMI #k 1010 kkkk THA 0111 0110 TLA 0111 0100 Acc←RAM[x] Acc ←RAM[HL] Acc←ROM[DP] L Acc←ROM[DP]H,DP+1 HR←k LR←RAM[x],HR←RAM[x+1] Acc←k LR←k RAM[x]←Acc RAM[HL]←Acc RAM[HL]←Acc, LR-1 RAM[HL]←Acc, LR+1 RAM[y]←k RAM[HL]←k, LR+1 Acc←HR Acc←LR Byte 2 1 1 1 1 2 1 1 2 1 1 1 2 1 1 1 Cycle 2 1 2 2 1 2 1 1 2 1 1 1 2 1 1 1 C - Flag Z Z Z Z Z Z Z Z Z Z Z C C C Flag Z Z Z S C' C' C C - Flag Z Z Z Z Z Z Z Z Z Z Z Z S C' C' C' C' C' C' C' C C C C' S 1 1 1 1 1 1 1 1 1 1 C C' 1 C' 1 1 (2) Rotate Mnemonic RLCA RRCA Object code ( binary ) Operation description 0101 0000 0101 0001 ←CF←Acc← →CF→Acc→ Byte 1 1 Cycle 1 1 (3) Arithmetic operation Mnemonic ADCAM ADD #k,y ADDA #k ADDAM ADDH #k ADDL #k ADDM #k DECA DECL DECM INCA Object code ( binary ) Operation description 0111 0100 0110 0111 0110 0110 0110 0101 0111 0101 0101 0000 1001 kkkk yyyy 1110 0101 kkkk 0001 1110 1001 kkkk 1110 0001 kkkk 1110 1101 kkkk 1100 1100 1101 1110 Acc←Acc + RAM[HL] + CF RAM[y]←RAM[y] + k Acc←Acc+k Acc←Acc + RAM[HL] HR←HR+k LR←LR+k RAM[HL]←RAM[HL] +k Acc←Acc-1 LR←LR-1 RAM[HL]←RAM[HL] -1 Acc←Acc + 1 * This specification are subject to be changed without notice. Byte 1 2 2 1 2 2 2 1 1 1 1 Cycle 1 2 2 1 2 2 2 1 1 1 1 8.16.2001 54 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT INCL INCM SUBA #k SBCAM SUBM #k 0111 1110 0101 1111 0110 1110 0111 kkkk 0111 0010 0110 1110 1111 kkkk ary n i m i l e Pr LR←LR + 1 RAM[HL]←RAM[HL]+1 Acc←k-Acc Acc←RAM[HLl - Acc - CF' RAM[HL]←k - RAM[HL] 1 1 2 1 2 1 1 2 1 2 Operation description Byte Acc←Acc&k Acc←Acc & RAM[HL] RAM[HL]←RAM[HL]&k Acc←Acc k Acc ←Acc RAM[HL] RAM[HL]←RAM[HL] k Acc←Acc^RAM[HL] 2 1 2 2 1 2 1 Operation description Byte Acc↔RAM[x] Acc↔HR Acc↔LR Acc↔RAM[HL] LR↔RAM[x], HR↔RAM[x+1] 2 1 1 1 2 2 2 1 2 2 Operation description Byte If SF=1 then PC←PC12-6.a5-0 elsenull If SF= 1 then PC←a else null If SF=1 then PC←a else null 1 1 2 3 2 3 Operation description Byte k-RAM[y] RAM[x]-Acc 2 2 C - Z Z Z Z Z C' C' C C C (4) Logical operation Mnemonic 1110 0110 kkkk 1011 1110 1110 kkkk 1110 0100 kkkk 1000 1110 1100 kkkk 1001 -- 0110 0111 0110 0110 0111 0110 0111 ---- ANDA #k ANDAM ANDM #k ORA #k ORAM ORM #k XORAM Object code (binary) Cycle 2 1 2 2 1 2 1 C - Flag Z Z Z Z Z Z Z Z S Z' Z' Z' Z' Z' Z' Z' (5) Exchange Mnemonic EXA x EXAH EXAL EXAM EXHL x Object code (binary) 0110 1000 xxxx xxxx 0110 0110 0110 0100 0101 1000 0100 1100 xxxx xx00 Cycle Flag C Z S - Z Z Z Z 1 1 1 1 - - 1 Flag C Z - - S - - 1 1 Flag C Z S 8.16.2001 55 (6) Branch Mnemonic Object code (binary) SBR a 00aa aaaa LBR a SLBR a 1100 aaaa aaaa aaaa 0101 0101 1100 aaaa aaaa aaaa (a:1000~1FFFh) Cycle 1 0101 0111 1100 aaaa aaaa aaaa (a:0000~0FFFh) (7) Compare Mnemonic Object code (binary) CMP #k,y 0100 1011 kkkk yyyy CMPA x 0110 1011 xxxx xxxx * This specification are subject to be changed without notice. Cycle 2 2 C C Z Z Z' Z' EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT Mnemonic Object code ( binary ) CMPAM CMPH #k CMPIA #k CMPL #k 0111 0011 0110 1110 1011 kkkk 1011 kkkk 0110 1110 0011 kkkk inary Prelim Operation description Byte RAM[HL] - Acc k - HR k - Acc k-LR 1 2 1 2 Cycle 1 2 1 2 C Flag Z C - Flag Z - S 1 1 1 1 1 1 1 1 * * * * * * * Flag Z - S - C C - Z Z Z Z S Z' C Z' C (8) Bit manipulation Mnemonic Object code ( binary ) Operation description Byte CLM CLP CLPL CLR SEM SEP SEPL SET TF TFA TFM TFP TFPL TT TTP 1111 00bb 0110 1101 11bb pppp 0110 0000 0110 1100 11bb yyyy 1111 01bb 0110 1101 01bb pppp 0110 0010 0110 1100 01bb yyyy 0110 1100 00bb yyyy 1111 10bb 1111 11bb 0110 1101 00bb pppp 0110 0001 0110 1100 10bb yyyy 0110 1101 10bb pppp RAM[HL]b←0 PORT[p]b←0 PORT[LR3-2+4]LR1-0←0 RAM[y]b←0 RAM[HL]b←1 PORT[p]b←1 PORT[LR3-2+4]LRl-0←1 RAM[y]b←1 SF←RAM[y]b' SF←Acc b' SF←RAM[HL]b' SF←PORT[p]b' SF←PORT[LR 3-2 +4]LR1-0' SF←RAM[y]b SF←PORT[p]b 1 2 1 2 1 2 1 2 2 1 1 2 1 2 2 Mnemonic Object code ( binary ) Operation description Byte LCALL a 0100 0aaa aaaa aaaa 2 2 SCALL a 1110 nnnn 1 2 - - - RET 0100 1111 STACK[SP]←PC, SP←SP -1, PC←a STACK[SP]←PC, SP←SP - 1, PC←a, a = 8n + 6 (n =1∼15),0086h (n = 0) SP←SP + 1, PC←STACK[SP] C - 1 2 - - - Mnemonic Object code ( binary ) Operation description Byte INA INM OUT OUTA OUTM 0110 1111 0100 pppp 0110 1111 1100 pppp 0100 1010 kkkk pppp 0110 1111 000p pppp 0110 1111 100p pppp Acc←PORT[p] RAM[HL]←PORT[p] PORT[p]←k PORT[p]←Acc PORT[p]←RAM[HL] 2 2 2 2 2 b p,b y,b b p,b y,b y,b b b p,b y,b p,b Cycle 1 2 2 2 1 2 2 2 2 1 1 2 2 2 2 (9) Subroutine Cycle (10) Input/output p p #k,p p p * This specification are subject to be changed without notice. Cycle 2 2 2 2 2 C - Flag Z Z - 8.16.2001 S Z' Z' 1 1 1 56 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT (11) Flag manipulation ary n i m i l e Pr Mnemonic Object code ( binary ) Operation description Byte Cycle TFCFC TTCFS TZS 0101 0011 0101 0010 0101 1011 SF←CF', CF←0 SF←CF, CF←1 SF←ZF 1 1 1 1 1 1 C 0 1 - Flag Z - S * * * C * Flag Z * S 1 1 1 1 * C - Flag Z - S - C - Flag Z Z Z Z Z Z Z Z Z Z Z - S 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (12) Interrupt control Mnemonic Object code ( binary ) Operation description Byte CIL r DICIL r EICIL r EXAE RTI 0110 0011 11rr rrrr 0110 0011 10rr rrrr 0110 0011 01rr rrrr 0111 0101 0100 1101 IL←IL & r EIF←0,IL←IL&r EIF←1,IL←IL&r MASK↔Acc SP←SP+1,FLAG.PC ←STACK[SP],EIF ←1 2 2 2 1 1 Mnemonic Object code ( binary ) Operation description Byte NOP 0101 0110 no operation 1 Cycle 2 2 2 1 2 (13) CPU control Cycle 1 (14) Timer/Counter & Data pointer & Stack pointer control Mnemonic Object code ( binary ) Operation description Byte LDADPL LDADPM LDADPH LDASP LDATAL LDATAM LDATAH LDATBL LDATBM LDATBH STADPL STADPM STADPH STASP STATAL STATAM STATAH STATBL STATBM STATBH 0110 1010 1111 1100 0110 1010 1111 1101 0110 1010 1111 1110 0110 1010 1111 1111 0110 1010 1111 0100 0110 1010 1111 0101 0110 1010 1111 0110 0110 1010 1111 1000 0110 1010 1111 1001 0110 1010 1111 1010 0110 1001 1111 1100 0110 1001 1111 1101 0110 1001 1111 1110 0110 1001 1111 1111 0110 1001 1111 0100 0110 1001 1111 0101 0110 1001 1111 0110 0110 1001 1111 1000 0110 1001 1111 1001 0110 1001 1111 1010 Acc←[DP] L Acc←[DP] M Acc←[DP] H Acc←SP Acc←[TA] L Acc←[TA]M Acc←[TA] H Acc←[TB] L Acc←[TB]M Acc←[TB]H [DP] L ←Acc [DP] M ←Acc [DP] H←Acc SP←Acc [TA] L←Acc [TA]M ←Acc [TA] H←Acc [ TB] L←Acc [TB] M←Acc [TB] H←Acc 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 * This specification are subject to be changed without notice. Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 8.16.2001 57 EM73A89B 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT **** SYMBOL DESCRIPTION Symbol HR PC SP ACC CF SF IL PORT[p] ΤΒ RAM[x] ROM[DP]H [DP]M [TA]L([TB]L) [TA]H([TB]H) LR3-2 PC12-6 ↔ -- #k y b inary Prelim Description Symbol H register Program counter Stack pointer Accumulator Carry flag Status flag Interrupt latch Port ( address : p ) Timer/counter B Data memory (address : x ) High 4-bit of program memory Middle 4-bit of data pointer register Low 4-bit of timer/counter A (timer/counter B) register High 4-bit of timer/counter A (timer/counter B) register Bit 3 to 2 of LR LR DP STACK[SP] FLAG ZF EI MASK ΤΑ RAM[HL] ROM[DP]L [DP]L [DP]H [TA]M([TB]M) Bit 12 to 6 of program counter Exchange Substraction Logic OR Inverse operation 4-bit immediate data 4-bit zero-page address Bit address ← + & ^ . x p r LR 1-0 a5-0 * This specification are subject to be changed without notice. Description L register Data pointer Stack specified by SP All flags Zero flag Enable interrupt register Interrupt mask Timer/counter A Data memory (address : HL ) Low 4-bit of program memory Low 4-bit of data pointer register High 4-bit of data pointer register Middle 4-bit of timer/counter A (timer/counter B) register Contents of bit assigned by bit 1 to 0 of LR Bit 5 to 0 of destination address for branch instruction Transfer Addition Logic AND Logic XOR Concatenation 8-bit RAM address 4-bit or 5-bit port address 6-bit interrupt latch 8.16.2001 58