SCES515E − DECEMBER 2003 − REVISED MAY 2004
D Available in the Texas Instruments
D
D
D
D
D
NanoStar and NanoFree Packages
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.65-V to
5.5-V Power-Supply Range
VCC Isolation Feature − If Either VCC Input
Is at GND, Both Ports Are in the
High-Impedance State
DIR Input Circuit Referenced to VCCA
Low Power Consumption, 4-µA Max ICC
±24-mA Output Drive at 3.3 V
1
6
2
5
3
4
D
D
D
Operation
Max Data Rates
− 420 Mbps (3.3-V to 5-V Translation)
− 210 Mbps (Translate to 3.3 V)
− 140 Mbps (Translate to 2.5 V)
− 75 Mbps (Translate to 1.8 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
YEP OR YZP PACKAGE
(BOTTOM VIEW)
DBV OR DCK PACKAGE
(TOP VIEW)
VCCA
GND
A
D Ioff Supports Partial-Power-Down Mode
A
GND
VCCA
VCCB
DIR
B
3 4
2 5
1 6
B
DIR
VCCB
description/ordering information
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track
VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional
translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
The SN74LVC1T45 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
−40 C to 85°C
−40°C
85 C
SOT (SOT-23) − DBV
SOT (SC-70) − DCK
TOP-SIDE
MARKING‡
SN74LVC1T45YEPR
Reel of 3000
_ _ _TA_
SN74LVC1T45YZPR
Reel of 3000
SN74LVC1T45DBVR
Reel of 250
SN74LVC1T45DBVT
Reel of 3000
SN74LVC1T45DCKR
Reel of 250
SN74LVC1T45DCKT
CT1_
TA_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright 2004, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCES515E − DECEMBER 2003 − REVISED MAY 2004
description/ordering information (continued)
The SN74LVC1T45 is designed so that the DIR input circuit is supplied by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
FUNCTION TABLE
INPUT
DIR
OPERATION
L
B data to A bus
H
A data to B bus
logic diagram (positive logic)
DIR
A
5
3
4
VCCA
2
POST OFFICE BOX 655303
VCCB
• DALLAS, TEXAS 75265
B
SCES515E − DECEMBER 2003 − REVISED MAY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCCA and VCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCA + 0.5V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCB + 0.5V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
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3
SCES515E − DECEMBER 2003 − REVISED MAY 2004
recommended operating conditions (see Notes 4 through 8)
VCCI
VCCA
VCCB
VCCO
Supply voltage
High-level input
voltage
Data inputs
(see Note 7)
MAX
1.65
5.5
1.65
5.5
2.3 V to 2.7 V
3 V to 3.6 V
VCCI × 0.7
VCCI × 0.35
0.7
1.65 V to 1.95 V
Low-level input
voltage
Data inputs
(see Note 7)
2.3 V to 2.7 V
3 V to 3.6 V
0.8
DIR
(Referenced to VCCA)
(see Note 8)
High-level input
voltage
VCCA × 0.65
1.7
2.3 V to 2.7 V
3 V to 3.6 V
VCCA × 0.7
VCCA × 0.35
0.7
1.65 V to 1.95 V
VIL
DIR
(Referenced to VCCA)
(see Note 8)
2.3 V to 2.7 V
3 V to 3.6 V
0.8
4.5 V to 5.5 V
VI
VO
Input voltage
0
Output voltage
0
1.65 V to 1.95 V
IOH
High-level output current
∆t/∆v
t/ v
Low-level output current
Input transition rise or
fall rate
Data input
Control input
VCCA × 0.3
5.5
VCCO
−4
2.3 V to 2.7 V
−8
3 V to 3.6 V
−24
4.5 V to 5.5 V
−32
1.65 V to 1.95 V
IOL
V
2
4.5 V to 5.5 V
Low-level input
voltage
V
VCCI × 0.3
4.5 V to 5.5 V
1.65 V to 1.95 V
VIH
V
V
2
4.5 V to 5.5 V
VIL
UNIT
VCCI × 0.65
1.7
1.65 V to 1.95 V
VIH
MIN
V
V
V
mA
4
2.3 V to 2.7 V
8
3 V to 3.6 V
24
4.5 V to 5.5 V
32
1.65 V to 1.95 V
20
2.3 V to 2.7 V
20
3 V to 3.6 V
10
4.5 V to 5.5 V
5
1.65 V to 5.5 V
5
mA
ns/V
TA
Operating free-air temperature
−40
85
°C
NOTES: 4. VCCI is the VCC associated with the data input port.
5. VCCO is the VCC associated with the output port.
6. All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7. For VCCI values not specified in the data sheet, VIH(min) = VCCI x 0.7 V, VIL(max) = VCCI x 0.3 V.
8. For VCCI values not specified in the data sheet, VIH(min) = VCCA x 0.7 V, VIL(max) = VCCA x 0.3 V.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES515E − DECEMBER 2003 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Notes 9 and 10)
PARAMETER
VOH
VOL
II
DIR
input
TEST CONDITIONS
VCCA
VCCB
MIN
TA = 25°C
TYP
MAX
−40°C to 85°C
MIN
IOH = −100 µA,
IOH = −4 mA,
VI = VIH
VI = VIH
1.65 V to 4.5 V
1.65 V to 4.5 V
1.65V
1.65 V
IOH = −8 mA,
IOH = −24 mA,
VI = VIH
VI = VIH
2.3 V
2.3 V
1.9
3V
3V
2.4
IOH = −32 mA,
IOL = 100 µA,
VI = VIH
VI = VIL
3.8
IOL = 4 mA,
IOL = 8 mA,
IOL = 24 mA,
IOL = 32 mA,
MAX
VCCO−0.1
1.2
V
4.5 V
4.5 V
1.65 V to 4.5 V
1.65 V to 4.5 V
0.1
VI = VIL
VI = VIL
1.65 V
1.65 V
0.45
2.3 V
2.3 V
0.3
VI = VIL
VI = VIL
3V
3V
0.55
4.5 V
4.5 V
0.55
1.65 V to 5.5 V
1.65 V to 5.5 V
±1
±2
VI = VCCA or GND
0V
0 to 5.5 V
Ioff
VI or VO = 0 to 5.5 V
±1
±2
B port
0 to 5.5 V
0V
±1
±2
IOZ
A or B
ports
VO = VCCO or GND
1.65 V to 5.5 V
1.65 V to 5.5 V
±1
±2
1.65 V to 5.5 V
1.65 V to 5.5 V
3
5.5 V
0V
2
A port
VI = VCCI or
GND
ICCA
ICCB
VI = VCCI or
GND
ICCA + ICCB
VI = VCCI or
GND
IO = 0
IO = 0
IO = 0
A port
A port at VCCA − 0.6 V,
DIR at VCCA, B port = OPEN
DIR
DIR at VCCA − 0.6 V,
B port = OPEN,
A port at VCCA or GND
∆ICCB
B port
B port at VCCB − 0.6 V,
DIR at GND, A port = OPEN
Ci
DIR
input
Cio
A or B
ports
∆ICCA
UNIT
0V
5.5 V
0
1.65 V to 5.5 V
1.65 V to 5.5 V
3
5.5 V
0V
0
0V
5.5 V
2
1.65 V to 5.5 V
1.65 V to 5.5 V
4
V
µA
µA
A
µA
µA
µA
µA
50
3 V to 5.5 V
µA
3 V to 5.5 V
50
50
µA
3 V to 5.5 V
3 V to 5.5 V
VI = VCCA or GND
3.3 V
3.3 V
2.5
pF
VO = VCCA/B or GND
3.3 V
3.3 V
6
pF
NOTES: 9. VCCO is the VCC associated with the output port.
10. VCCI is the VCC associated with the input port.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SCES515E − DECEMBER 2003 − REVISED MAY 2004
switching characteristics over recommended operating
VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH†
tPZL†
tPZH†
tPZL†
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.8 V
± 0.15 V
free-air
VCCB = 2.5 V
± 0.2 V
temperature
VCCB = 3.3 V
± 0.3 V
range,
VCCB = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3
17.7
2.2
10.3
1.7
8.3
1.4
7.2
2.8
14.3
2.2
8.5
1.8
7.1
1.7
7
3
17.7
2.3
16
2.1
15.5
1.9
15.1
2.8
14.3
2.1
12.9
2
12.6
1.8
12.2
5.2
19.4
4.8
18.5
4.7
18.4
5.1
17.1
2.3
10.5
2.1
10.5
2.4
10.7
3.1
10.9
7.4
21.9
4.9
11.5
4.6
10.3
2.8
8.2
4.2
16
3.7
9.2
3.3
8.4
2.4
6.4
33.7
25.2
23.9
21.5
36.2
24.4
22.9
20.4
28.2
20.8
19
18.1
33.7
27
25.5
24.1
UNIT
ns
ns
ns
ns
ns
ns
† The enable time is a calculated value, derived using the formula shown in the section entitled enable times on page 16.
switching characteristics over recommended operating
VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH†
tPZL†
tPZH†
tPZL†
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.8 V
± 0.15 V
MIN
free-air
VCCB = 2.5 V
± 0.2 V
temperature
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.3
16
1.5
8.5
1.3
6.4
1.1
5.1
2.1
12.9
1.4
7.5
1.3
5.4
0.9
4.6
2.2
10.3
1.5
8.5
1.4
8
1
7.5
2.2
8.5
1.4
7.5
1.3
7
0.9
6.2
3
8.1
3.1
8.1
2.8
8.1
3.2
8.1
1.3
5.9
1.3
5.9
1.3
5.9
1
5.8
6.5
23.7
4.1
11.4
3.9
10.2
2.4
7.1
3.9
18.9
3.2
9.6
2.8
8.4
1.8
5.3
29.2
18.1
16.4
12.8
32.2
18.9
17.2
13.3
21.9
14.4
12.3
10.9
21
15.6
13.5
12.7
† The enable time is a calculated value, derived using the formula shown in the section entitled enable times on page 16.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
range,
UNIT
ns
ns
ns
ns
ns
ns
SCES515E − DECEMBER 2003 − REVISED MAY 2004
switching characteristics over recommended operating
VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH†
tPZL†
tPZH†
tPZL†
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.8 V
± 0.15 V
free-air
VCCB = 2.5 V
± 0.2 V
temperature
VCCB = 3.3 V
± 0.3 V
range,
VCCB = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.1
15.5
1.4
8
0.7
5.8
0.7
4.4
2
12.6
1.3
7
0.8
5
0.7
4
1.7
8.3
1.3
6.4
0.7
5.8
0.6
5.4
1.8
7.1
1.3
5.4
0.8
5
0.7
4.5
2.9
7.3
3
7.3
2.8
7.3
3.4
7.3
1.8
5.6
1.6
5.6
2.2
5.7
2.2
5.7
5.4
20.5
3.9
10.1
2.9
8.8
2.4
6.8
3.3
14.5
2.9
7.8
2.4
7.1
1.7
4.9
22.8
14.2
12.9
10.3
27.6
15.5
13.8
11.3
21.1
13.6
11.5
10.1
19.9
14.3
12.3
11.3
UNIT
ns
ns
ns
ns
ns
ns
† The enable time is a calculated value, derived using the formula shown in the section entitled enable times on page 16.
switching characteristics over recommended operating
VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH†
tPZL†
tPZH†
tPZL†
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.8 V
± 0.15 V
MIN
MAX
1.9
1.8
free-air
VCCB = 2.5 V
± 0.2 V
temperature
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
15.1
1
7.5
0.6
5.4
0.5
3.9
12.2
0.9
6.2
0.7
4.5
0.5
3.5
1.4
7.2
1
5.1
0.7
4.4
0.5
3.9
1.7
7
0.9
4.6
0.7
4
0.5
3.5
2.1
5.4
2.2
5.4
2.2
5.5
2.2
5.4
0.9
3.8
1
3.8
1
3.7
0.9
3.7
4.8
20.2
2.5
9.8
1
8.5
2.5
6.5
4.2
14.8
2.5
7.4
2.5
7
1.6
4.5
22
12.5
11.4
8.4
27.2
14.4
12.5
10
18.9
11.3
9.1
7.6
17.6
11.6
10
8.9
range,
UNIT
ns
ns
ns
ns
ns
ns
† The enable time is a calculated value, derived using the formula shown in the section entitled enable times on page 16.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SCES515E − DECEMBER 2003 − REVISED MAY 2004
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
VCCA =
VCCB = 1.8 V
TYP
CpdA†
CpdB†
A port input, B port output
B port input, A port output
A port input, B port output
CL = 0,
f = 10 MHz,
tr = tf =1 ns
B port input, A port output
VCCA =
VCCB = 2.5 V
TYP
POST OFFICE BOX 655303
TYP
VCCA =
VCCB = 5 V
3
4
4
4
19
20
21
18
19
20
21
3
4
4
4
• DALLAS, TEXAS 75265
UNIT
TYP
18
† Power-dissipation capacitance per transceiver
8
VCCA =
VCCB = 3.3 V
pF
SCES515E − DECEMBER 2003 − REVISED MAY 2004
power-up considerations
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies. Take the following precautions to guard against such power-up problems:
1. Connect ground before any supply voltage is applied.
2. Power up VCCA.
3. VCCB can be ramped up along with or after VCCA.
typical total static power consumption (ICCA + ICCB)
Table 1
VCCB
0V
1.8 V
VCCA
2.5 V
3.3 V
5V
<1
0V
0
<1
<1
<1
1.8 V
<1
<2
<2
<2
2
2.5 V
<1
<2
<2
<2
<2
3.3 V
<1
<2
<2
<2
<2
5V
<1
2
<2
<2
<2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
µA
9
SCES515E − DECEMBER 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A TO B) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 1.8 V
10
10
9
9
8
VCCB = 1.8 V
8
7
7
6
6
t PLH − ns
t PHL − ns
VCCB = 1.8 V
VCCB = 2.5 V
5
4
VCCB = 2.5 V
5
VCCB = 3.3 V
4
VCCB = 5 V
VCCB = 3.3 V
3
3
VCCB = 5 V
2
2
1
1
0
0
0
5
10
20
15
25
30
35
0
5
10
15
20
25
30
35
25
30
35
CL − pF
CL − pF
TYPICAL PROPAGATION DELAY (B TO A) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 1.8 V
10
10
9
9
VCCB = 1.8 V
8
VCCB = 2.5 V
8
7
7
6
6
t PLH − ns
t PHL − ns
VCCB = 1.8 V
5
VCCB = 2.5 V
4
VCCB = 3.3 V
VCCB = 5 V
5
4
VCCB = 5 V
3
3
2
2
1
1
0
0
5
10
VCCB = 3.3 V
15
20
25
30
35
0
0
5
15
20
CL − pF
CL − pF
10
10
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SCES515E − DECEMBER 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A TO B) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 2.5 V
10
10
9
9
8
8
VCCB = 1.8 V
7
6
t PLH − ns
t PHL − ns
7
5
VCCB = 2.5 V
4
3
VCCB = 3.3 V
2
VCCB = 1.8 V
6
5
VCCB = 2.5 V
4
VCCB = 3.3 V
3
VCCB = 5 V
2
VCCB = 5 V
1
1
0
0
0
5
10
15
20
25
30
35
0
10
5
CL − pF
15
20
25
30
35
CL − pF
Figure 1
10
10
9
9
8
8
7
7
t PLH − ns
t PHL − ns
TYPICAL PROPAGATION DELAY (B TO A) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 2.5 V
6
6
VCCB = 1.8 V
5
5
4
4
3
3
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
2
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
2
1
1
0
VCCB = 1.8 V
0
0
5
10
15
20
CL − pF
25
30
35
0
5
10
15
20
25
30
35
CL − pF
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11
SCES515E − DECEMBER 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A TO B) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 3.3 V
10
10
9
9
8
8
VCCB = 1.8 V
7
7
VCCB = 1.8 V
6
t PLH − ns
t PHL − ns
6
5
4
VCCB = 2.5 V
VCCB = 2.5 V
4
VCCB = 3.3 V
3
3
VCCB = 5 V
2
2
VCCB = 3.3 V
VCCB = 5 V
1
0
5
0
5
10
1
15
20
25
30
0
0
35
5
10
15
20
25
30
35
25
30
35
CL − pF
CL − pF
10
10
9
9
8
8
7
7
6
6
t PLH − ns
t PHL − ns
TYPICAL PROPAGATION DELAY (B TO A) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 3.3 V
5
VCCB = 1.8 V
4
5
VCCB = 1.8 V
4
VCCB = 2.5 V
VCCB = 2.5 V
3
3
2
VCCB = 5 V
1
VCCB = 3.3 V
VCCB = 5 V
2
VCCB = 3.3 V
1
0
0
0
5
10
15
20
25
30
35
0
5
15
CL − pF
CL − pF
12
10
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• DALLAS, TEXAS 75265
20
SCES515E − DECEMBER 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 5 V
10
10
9
9
8
8
7
7
VCCB = 1.8 V
t PLH − ns
t PHL − ns
6
5
4
VCCB = 2.5 V
3
VCCB = 1.8 V
6
5
VCCB = 2.5 V
4
VCCB = 3.3 V
3
2
2
VCCB = 3.3 V
VCCB = 5 V
1
1
0
0
0
5
10
VCCB = 5 V
15
20
25
30
35
0
10
5
20
15
25
30
35
CL − pF
CL − pF
10
10
9
9
8
8
7
7
6
6
t PLH − ns
t PHL− ns
TYPICAL PROPAGATION DELAY (B TO A) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 5 V
5
4
VCCB = 1.8 V
3
VCCB = 2.5 V
VCCB = 1.8 V
4
VCCB = 2.5 V
3
2
2
VCCB = 3.3 V
VCCB = 5 V
1
0
5
0
5
10
VCCB = 3.3 V
VCCB = 5 V
1
15
20
25
30
35
0
0
5
CL − pF
10
15
20
25
30
35
CL − pF
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13
SCES515E − DECEMBER 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
CL
RL
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
VTP
0.15 V
0.15 V
0.3 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
0V
tPLZ
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VOH
VCCO/2
VOL
VCCO/2
VCCA/2
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VTP
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
J. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
14
POST OFFICE BOX 655303
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SCES515E − DECEMBER 2003 − REVISED MAY 2004
APPLICATION INFORMATION
The following circuit is an example of the SN74LVC1T45 being used in a unidirectional logic level-shifting
application.
VCC1
VCC1
VCC2
1
6
2
5
3
4
SYSTEM-1
VCC2
SYSTEM-2
PIN
NAME
FUNCTION
1
VCCA
VCC1
SYSTEM-1 supply voltage (1.65 V to 5.5 V)
DESCRIPTION
2
GND
GND
Device GND
3
A
OUT
Output level depends on VCC1 voltage.
4
B
IN
5
DIR
DIR
6
VCCB
VCC2
Input threshold value depends on VCC2 voltage.
The GND (low level) determines B port to A port direction.
SYSTEM-2 supply voltage (1.65 V to 5.5 V)
Figure 3. Unidirectional Logic Level-Shifting Application
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15
SCES515E − DECEMBER 2003 − REVISED MAY 2004
APPLICATION INFORMATION
Figure 4 shows the SN74LVC1T45 being used in a bidirectional logic level-shifting application. Since the
SN74LVC1T45 does not have an output enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
VCC1
VCC1
VCC2
VCC2
Pullup/Down
or Bus Hold†
I/O-1
Pullup/Down
or Bus Hold†
1
6
2
5
3
4
I/O-2
DIR CTRL
SYSTEM-1
SYSTEM-2
Following is a sequence that illustrates data transmission from SYSTEM-1 to SYSTEM-2 and then from
SYSTEM-2 to SYSTEM-1.
STATE
DIR CTRL
I/O 1
I/O 2
1
H
OUT
IN
DESCRIPTION
2
H
HI-Z
HI-Z
SYSTEM-2 is getting ready to send data to
SYSTEM-1. I/O-1 and I/O-2 are disabled.
The bus-line state depends on pullup or pulldown.†
3
L
HI-Z
HI-Z
DIR bit is flipped. I/O-1 and I/O-2 still are disabled.
The bus-line state depends on pullup or pulldown.†
4
L
OUT
IN
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 data to SYSTEM-1
† SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 4. Bidirectional Logic Level-Shifting Application
enable times
Calculate the enable times for the SN74LVC1T45 using the following formulas:
1. tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
2. tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
3. tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
4. tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74LVC1T45 initially is transmitting from A to B, then
the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the
B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC1T45DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1T45DBVRE4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1T45DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1T45DBVTE4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1T45DCKR
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1T45DCKRG4
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1T45DCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1T45DCKTE4
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1T45YEPR
ACTIVE
WCSP
YEP
6
3000
TBD
SNPB
Level-1-260C-UNLIM
SN74LVC1T45YZPR
ACTIVE
WCSP
YZP
6
3000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
6
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-3/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
POST OFFICE BOX 655303
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