June 1999 PBL 386 21/2 Subscriber Line Interface Circuit Description Key Features The PBL 386 21/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in DAML, FITL and other telecommunications equipment. The PBL 386 21/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications. The PBL 386 21/2 has constant current feed, programmable to max. 30 mA. A second lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current, ground key and ring trip detection functions. The PBL 386 21/2 is compatible with loop start signaling. Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable the two-wire impedance, complex or real, is set by a simple external network. Longitudinal voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet Bellcore TR909 requirements. The PBL 386 21/2 package options are 24-pin SSOP, 24-pin SOIC or 28-pin PLCC. • 24-pin SSOP package • High and low battery with automatic switching • 60 mW on-hook power dissipation in active state • On-hook transmission • Long loop battery feed tracks Vbat for maximum line voltage • Only +5 V feed in addition to battery • Selectable transmit gain (1x or 0.5x) • No power-up sequence • 44V open loop voltage @ -48V battery feed • Full longitudinal current capability during on-hook state • Analog over temperature protection permits transmission while the protection circuit is active • Polarity reversal • Integrated Ring Relay driver • Ground key detector • Programmable signal headroom Ring Relay Driver DT TIPX Ground Key Detector RINGX • -40 °C to +85 °C ambient temperature range C1 Ring Trip Comparator DR RRLY Input Decoder and Control C2 C3 DET HP PSG LP Off-hook Detector PLD REF 21/2 386 PBL VTX AGND BGND 38 PB 6 L 21 /2 P B VBAT2 VBAT 21 / 2 PLC 38 6 Two-wire Interface POV L VCC Line Feed Controller and Longitudinal Signal Suppression VF Signal Transmission PTG RSN 24-pin SOIC, 24-pin SSOP, 28-pin PLCC Figure 1. Block diagram. 1 PBL 386 21/2 Maximum Ratings Parameter Symbol Min Max Unit Temperature, Humidity Storage temperature range Operating temperature range Operating junction temperature range, Note 1 TStg TAmb TJ -55 -40 -40 +150 +110 +140 °C °C °C Power supply, -40 °C ≤ TAmb ≤ +85 °C VCC with respect to A/BGND VBat2 with respect to A/BGND VBat with respect to A/BGND, continuous VBat with respect to A/BGND, 10 ms VCC VBat2 VBat VBat -0.4 VBat -75 -80 6.5 0.4 0.4 0.4 V V V V Power dissipation Continuous power dissipation at TAmb ≤ +85 °C PD 1.5 W 0,3 V Ground Voltage between AGND and BGND Relay Driver Ring relay supply voltage VG -0,3 BGND+14 V Ring trip comparator Input voltage Input current VDT, VDR IDT, IDR VBat -5 AGND 5 V mA Digital inputs, outputs (C1, C2, C3, DET) Input voltage VID -0.4 VCC V Output voltage VOD -0.4 VCC V TIPX and RINGX terminals, -40°C < TAmb < +85°C, VBat = -50V Maximum supplied TIPX or RINGX current TIPX or RINGX voltage, continuous (referenced to AGND), Note 2 ITIPX, IRINGX -100 VTA, VRA -80 +100 2 mA V TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2 VTA, VRA VBat -10 5 V TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2 TIPX or RINGX, pulse < 250 ns, tRep > 10 s, Notes 2 & 3 VTA, VRA VTA, VRA VBat -25 VBat -35 10 15 V V Parameter Symbol Min Max Unit Ambient temperature VCC with respect to AGND VBat with respect to AGND AGND with respect to BGND TAmb VCC VBat VG -40 4.75 -58 -100 +85 5.25 -8 100 °C V V mV Recommended Operating Condition Notes 2 1. The circuit includes thermal protection. Operation at or above 140°C junction temperature may degrade device reliability. 2. With the diodes DVB and DVB2 included, see figure 12. 3. RF1 and RF2 ≥ 20 Ω is also required. Pulse is applied to TIP and RING outside RF1 and RF2. PBL 386 21/2 Electrical Characteristics -40 °C ≤ TAmb ≤ +85 °C, PTG = open (see pin description), VCC = +5V ±5 %, VBat = -58V to -40V, VBat2 = -17V, RLC=38.3 kΩ, IL = 22 mA. RL = 600 Ω, RF1= RF2= RP1= RP2=0, RRef = 49.9 kΩ, CHP = 47 nF, CLP=0.15 µF, RT = 120 kΩ, RSG = 0 kΩ, RRX = 60 kΩ, RR = 52.3 kΩ ROV = ∞ unless otherwise specified. Current definition: current is positive if flowing into a pin. Parameter Ref fig Two-wire port Overload level, VTRO 2 Conditions Min On-Hook, ILdc < 5mA Active state 1% THD Note 1, ROV = ∞ 1.0 1.0 Input impedance, ZTR Longitudinal impedance, ZLOT, ZLOR Longitudinal current limit, ILOT, ILOR Note 2 0 < f < 100 Hz active state Longitudinal to metallic balance, BLM IEEE standard 455-1985, ZTRX=736Ω 0.2 kHz < f < 1.0 kHz 53 1.0 kHz < f < 3.4 kHz 53 Reverse polarity 0.2 kHz < f < 3.4 kHz 53 Longitudinal to metallic balance, BLME VPeak VPeak ZT/200 20 35 10 Ω/wire mArms /wire dB dB dB 0.2 kHz < f < 1.0 kHz 53 1.0 kHz < f < 3.4 kHz 53 Reverse polarity 0.2 kHz < f < 3.4 kHz 53 75 70 68 dB dB dB 0.2 kHz < f < 1.0 kHz 53 1.0 kHz < f < 3.4 kHz 53 Reverse polarity 0.2 kHz < f < 3.4 kHz 53 75 70 68 dB dB dB 4 0.2 kHz < f < 3.4 kHz 50 dB C Figure 2. Overload level, VTRO, two-wire port Unit 3 BLFE = 20 • Log ELo VTX Metallic to longitudinal balance, BMLE V BMLE = 20 • Log TR ; ERX = 0 VLo Max 3 BLME =20 • Log ELo VTR Longitudinal to four-wire balance, BLFE Typ RL VTRO 40 TIPX ILDC 1 << RL, RL= 600 Ω ωC VTX RT PBL 386 21/2 RINGX E RX RSN RRX RT = 120 kΩ, RRX = 60 kΩ Figure 3. Longitudinal to metallic (BLME) and Longitudinal to four-wire (BLFE) balance TIPX ELo C RLT V TR 1 << 150 Ω, RLR =RLT =RL /2=300Ω ωC VTX PBL 386 21/2 RT V TX RLR RINGX RSN RRX RT = 120 kΩ, RRX = 60 kΩ 3 PBL 386 21/2 Ref fig Parameter Four-wire to longitudinal balance, BFLE 4 Two-wire return loss, r Four-wire transmit port (VTX) Overload level, VTXO 5 On-hook, IL < 5mA Output offset voltage ∆VTX Output impedance, zTX Typ 40 50 dB 0.2 kHz < f < 1.0 kHz 1.0 kHz < f < 3.4 kHz, Note 3 active, IL = 0 mA active, IL = 0 mA active, IL = 0 mA 27 20 35 22 - 1.1 VBat +2.5 VBat +3.6 dB dB V V V Load impedance > 20 kΩ, 1% THD, Note 4 1.0 0.2 kHz < f < 3.4 kHz Frequency response Two-wire to four-wire, g2-4 IRSN = -55 µA 0.2 kHz < f < 3.4 kHz 0.3 kHz < f < 3.4 kHz TIPX Unit 1.15 VPeak 0 15 100 50 VPeak mV Ω 1.25 8 1.35 20 V Ω 200 6 relative to 0 dBm, 1.0 kHz. ERX = 0 V 0.3 kHz < f < 3.4 kHz f = 8.0 kHz, 12 kHz, 16 kHz -0.20 -1.0 ratio 0.10 0.1 dB dB Figure 4. Metallic to longitudinal and four-wire to longitudinal balance VTX RLT V TR Max |ZTR + ZL| |ZTR - ZL| 1.0 -100 Four-wire receive port (RSN) Receive summing node (RSN) DC voltage Receive summing node (RSN) impedance Receive summing node (RSN) current (IRSN) to metallic loop current (IL) gain,αRSN VLo Min 0.2 kHz < f < 4.0 kHz E BFLE = 20 • Log RX VLo r = 20 • Log TIPX idle voltage, VTi RINGX idle voltage, VRi VTR C Conditions RT PBL 386 21/2 E RX 1 << 150 Ω, RLT =RLR =RL /2 =300Ω ωC RLR RINGX RSN RT = 120 kΩ, RRX = 60 kΩ RRX C TIPX Figure 5. Overload level, VTXO, four-wire transmit port VTX RL ILDC EL PBL 386 21/2 RINGX RT 1 << RL, RL = 600 Ω ωC RT = 120 kΩ, RRX = 60 kΩ RSN RRX 4 VTXO PBL 386 21/2 Parameter Ref fig Four-wire to two-wire, g4-2 6 Four-wire to four-wire, g4-4 Insertion loss Two-wire to four-wire, G2-4 Four-wire to two-wire, G4-2 Gain tracking Two-wire to four-wire 6 6 PTG = AGND 0 dBm, 1.0 kHz, Note 6 V G4-2 = 20 • Log TR ; EL = 0 ERX 6 Noise Idle channel noise at two-wire (TIPX-RINGX) or four-wire (VTX) output Typ Max Unit -0.2 -1.0 -2.0 0.1 0 0 dB dB dB -0.2 0.1 dB -0.2 0.2 dB -5.82 dB -0.2 0.2 dB -0.1 -0.2 0.1 0.2 dB dB -0.1 -0.2 0.1 0.2 dB dB 12 -78 dBrnC dBmp -50 -50 dB dB -6.22 Ref. -10 dBm, 1.0 kHz, Note 7 -40 dBm to +0 dBm -55 dBm to -40 dBm Ref. -10 dBm, 1.0 kHz, -40 dBm to +0 dBm -55 dBm to -40 dBm 6 Harmonic distortion Two-wire to four-wire Four-wire to two-wire Min 0 dBm, 1.0 kHz, Note 5 V G2-4 = 20 • Log TX ; ERX = 0 VTR 6 Four-wire to two-wire Conditions relative to 0 dBm, 1.0 kHz. EL=0 V 0.3 kHz < f < 3.4 kHz f = 8 kHz, 12 kHz, 16 kHz relative to 0 dBm, 1.0 kHz, EL=0 V 0.3 kHz < f < 3.4 kHz -6.02 C-message weighting Psophometrical weighting Note 8 6 0 dBm 0.3 kHz < f < 3.4 kHz -67 -67 ILProg 12 0.92 ILProg ILProg 1.08 ILProg mA ILProg @ 30 mA 12 ILProg = 1 000 - 4.0 (mA) RLC 1 ILProg = 000 - 4.2 (mA) RLC 0.95 ILProg ILProg 1.05 ILProg mA ILProg @ 18 mA 12 ILProg = 1 000 - 3.9 (mA) RLC RLC in kΩ RL = 0Ω 0.94 ILProg ILProg 1.06 ILProg mA -100 100 µA Battery feed characteristics Constant loop current, Open circuit state loop current, I LOC Figure 6. Frequency response, insertion loss, gain tracking. 1 ωC C TIPX 0 VTX RL << RL, RL = 600 Ω VTR EL RT = 120 kΩ, RRX = 60 kΩ ILDC PBL 386 21/2 RINGX RT E RX VTX RSN RRX 5 PBL 386 21/2 Parameter Loop current detector Programmable threshold, ILTh Ref fig Conditions Min Typ Max Unit 500 RLD RLD in kΩ, ILTh ≥ 7 mA 0.85•ILTh ILTh 1.15•ILTh mA 16 22 mA 0 -20 20 200 -1 mV nA V 0.2 0.5 10 V µA 0.5 VCC -50 50 V V µA µA 0.7 V kΩ 15 mW 80 mW mW mW 2.0 mA mA mA mA ILTh = Ground key detector Ground key detector threshold (ITIPX and IRINGX difference to trigger ground key det.) 10 Ring trip comparator Offset voltage, ∆VDTDR Source resistance, RS = 0 Ω -20 Input bias current, IB IB = (IDT + IDR)/2 -200 Input common mode range, VDT, VDR VBat+1 Ring relay driver Saturation voltage, VOL IOL = 50 mA Off state leakage current, ILk VOH = 12 V Digital inputs (C1, C2, C3) Input low voltage, VIL 0 Input high voltage, VIH 2.5 Input low current, IIL VIL = 0.5 Input high current, IIH VIH = 2.5 V Detector output (DET) Output low voltage IOL = 0.5 mA Internal pull-up resistor Power dissipation (VBat = -48V, VBat2 = -17V) P1 Open circuit state, C1, C2, C3 = 0, 0, 0 P2 P3 P4 Power supply currents (VBat = -48V) VCC current, ICC VBat current, IBat VCC current, ICC VBat current, IBat Power supply rejection ratios VCC to 2- or 4-wire port VBat to 2- or 4-wire port VBat2 to 2- or 4-wire port Temperature guard Junction threshold temperature, TJG Thermal resistance 28-pin PLCC, θJP28plcc 24-pin SOIC, θJP24soic 24-pin SSOP, θJP24ssop 6 15 10 Active state, C1, C2, C3 = 0, 1, 0 Longitudinal current = 0 mA, I L=0 mA (on-hook) 60 RL = 300 Ω (off-hook) 290 RL = 500 Ω (off-hook) 145 Open circuit state -1.5 1.2 -0.05 2.8 -1.0 30 36 40 42 45 60 -0.1 Active state On-hook, Long Current = 0 mA Active State f = 1 kHz, Vn = 100mV 145 39 43 55 4.0 dB dB dB °C °C/W °C/W °C/W PBL 386 21/2 Notes 1. 2. 3. The overload level can be adjusted with the resistor ROV for higher levels e.g. min 3.1 VPeak and is specified at the twowire port with the signal source at the four-wire receive port. The two-wire impedance is programmable by selection of external component values according to: ZTRX = ZT/|G2-4S α RSN| where: ZTRX = impedance between the TIPX and RINGX terminals ZT = programming network between the VTX and RSN terminals G2-4S = transmit gain, nominally = 1 (or 0.5 see pin PTG) α RSN = receive current gain, nominally = 200 (current defined as positive flowing into the receivesumming node, RSN, and when flowing from ring to tip). Higher return loss values can be achieved by adding a reactive component to RT, the two-wire terminating impedance programming resistance, e.g. by dividing R T into two equal halves and connecting a capacitor from the common point to ground. 4. 5. 6. 7. 8. The overload level can be adjusted with the resistor R OV for higher levels e.g. min 3.1 VPeak and is specified at the four-wire transmit port, VTX, with the signal source at the two-wire port. Note that the gain from the two-wire port to the four-wire transmit port is G2-4S = 1 (or 0.5 see pin PTG) Pin PTG = Open sets transmit gain to nom. 0.0dB Pin PTG = AGND sets transmit gain to nom. -6.02 dB Secondary protection resistors R F and resistors RP impact the insertion loss as explained in the text, section Transmission. The specified insertion loss is for RF = RP = 0. The specified insertion loss tolerance does not include errors caused by external components. The level is specified at the two-wire port. The two-wire idle noise is specified with the port terminated in 600 Ω (RL) and with the four-wire receive port grounded (ERX = 0; see figure 6). The four-wire idle noise at VTX is specified with the twowire port terminated in 600 Ω (R L). The noise specification is referenced to a 600 Ω programmed twowire impedance level at VTX. The four-wire receive port is grounded (ERX = 0). 7 18 PLD VBAT2 8 17 VCC PSG 9 16 DET LP 10 15 C1 DT 11 14 C2 DR 13 C3 12 26 RSN VBAT 7 25 NC BGND 6 24 REF TIPX 7 23 PLC 22 POV 28-pin PLCC VBAT 8 VBAT2 9 21 PLD PSG 10 20 VCC NC 11 19 NC DET 18 POV 27 AGND 19 TIPX 6 5 C1 17 PLC 24-pin SOIC and 24-pin SSOP 28 VTX 20 BGND 5 RINGX C2 16 REF PTG 21 1 RINGX 4 C3 15 RSN 2 RRLY 22 DR 14 HP 3 HP AGND 3 23 13 RRLY 2 DT VTX NC 24 LP 12 PTG 1 4 PBL 386 21/2 Figure 7. Pin configuration, 24-pin SSOP, 24-pin SOIC and 28 pin PLCC package, top view. Pin Description Refer to figure 7. PLCC Symbol Description 1 PTG Prog. Transmit Gain. Left open transmit gain = 0.0 dB, connected to AGND transmit gain = -6.02 dB. 2 RRLY Ring Relay driver output. The relay coil may be connected to maximum +14V. 3 HP Connection for High Pass filter capacitor, CHP. Other end of CHP connects to TIPX. 4 NC No internal Connection. 5 RINGX The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay). 6 BGND Battery Ground, should be tied together with AGND. 7 TIPX The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay). 8 VBAT Battery supply Voltage. Negative with respect to GND. 9 VBAT2 An optional second (2) Battery Voltage connects to this pin via an external diode. 10 PSG Programmable Saturation Guard. The resistive part of the DC feed characteristic is not used for PBL 386 21/2, RSG = 0 Ω. 11 NC No internal Connection. 12 LP Connection for Low Pass filter capacitor, CLP. Other end of CLP connects to VBAT. 13 DT Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The external ring trip network connects to this input. 14 DR Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The external ring trip network connects to this input. 8 PBL 386 21/2 } 15 16 17 C3 C2 C1 18 DET Detector output. Active low when indicating loop detection and ring trip, active high when indicating ground key detection. C1, C2 and C3 are digital inputs (internal pull-up) controlling the SLIC operating states. Refer to section "Operating states" for details. 19 NC No internal Connection. 20 VCC +5 V power supply. 21 PLD Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor connected from this pin to AGND. 22 POV Programmable Overhead Voltage. If pin is left open: The overhead voltage is internally set to min 1.0 V in off-and on-hook. If a resistor is connected between this pin and AGND: the overhead voltage can be set to higher values. 23 PLC Prog. Line Current, the constant current part of the DC feed characteristic is programmed by a resistor connected from this pin to AGND. 24 REF A Reference, 49.9 kΩ, resistor should be connected from this pin to AGND. 25 NC No internal Connection. 26 RSN Receive Summing Node. 200 times the AC-current flowing into this pin equals the metallic (transversal) AC-current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain connect to the receive summing node. A resistor should be connected from this pin to AGND. 27 AGND Analog Ground, should be tied together with BGND. 28 VTX Transmit vf output. The AC voltage difference between TIPX and RINGX, the AC metallic voltage, is reproduced as an unbalanced GND referenced signal at VTX with a gain of one (or one half, see pin PTG). The two-wire impedance programming network connects between VTX and RSN. SLIC Operating States State C3 C2 C1 SLIC operating state Active detector 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Open circuit Ringing state Active state Not applicable Not applicable Active state Active reverse Active reverse Ring trip detector (active low) Loop detector (active low) Ground key detector (active high) Loop detector (active low) Ground key detector (active high) Table 1. SLIC operating states. 9 PBL 386 21/2 TIPX TIP + ZL IL RP RF + ZTR VTR RHP - - RING VTX G 2-4S + - + EL For applications where ZT/(αRSN·G2-4S) + 2RF + 2RP is chosen to be equal to ZL the expression for G4-2 simplifies to: RF VTX RP G4 −2 = − ZT 1 ⋅ Z RX 2G2 − 4S IL RINGX - ZT Four-Wire to Four-Wire Gain From (1), (2) and (3) with EL = 0: Z RX + RSN VRX I L /αRSN - PBL 386 21/2 G4 −4 = − Figure 8. Simplified ac transmission circuit. Functional Description and Applications Information Transmission General A simplified ac model of the transmission circuits is shown in figure 8. Circuit analysis yields: VTR = VTX + IL ⋅ (2R F + 2RP ) G2 − 4S (1) αRSN is the receive summing node current to metallic loop current gain = 200. Note that the SLICs two-wire to four-wire gain, G2-4S, is user programmable between two fix values. Refer to the datasheets for values on G2-4S. Two-Wire Impedance To calculate ZTR, the impedance presented to the two-wire line by the SLIC including the fuse and protection resistors RF and RP let: VRX = 0. From (1) and (2): VTX VRX I + = L ZT Z RX α RSN VTR = EL - IL · ZL (2) Z TR = (3) where: VTX G2-4S VTR EL IL RF RP ZL ZT ZRX VRX 10 is a ground referenced version of the ac metallic voltage between the TIPX and RINGX terminals. is the programmable SLIC two-wire to four-wire gain (transmit direction). See note below. is the ac metallic voltage between tip and ring. is the line open circuit ac metallic voltage. is the ac metallic current. is a fuse resistor. is part of the SLIC protection. is the line impedance. determines the SLIC TIPX to RINGX impedance at voice frequencies. controls four- to two-wire gain. is the analog ground referenced receive signal. ZT + 2RF + 2RP α RSN ⋅ G 2− 4S Thus with ZTR, αRSN, G2-4S, RP and RF known: Z T = α RSN ⋅ G2− 4S ⋅ (Z TR − 2RF − 2R P ) Two-Wire to Four-Wire Gain From (1) and (2) with VRX = 0: G2− 4 = VTX = VTR Z T / α RSN ZT + 2RF + 2RP α RSN ⋅ G2 − 4S Four-Wire to Two-Wire Gain From (1), (2) and (3) with EL = 0: G4 −2 = − ZT ⋅ ZRX VTR = VRX ZL ZT + G2 − 4S ⋅ ( ZL + 2RF + 2R P ) α RSN ZT ⋅ ZRX VTX = VRX G 2− 4S ⋅ ( Z L + 2RF + 2R P ) ZT + G2 −4 S ⋅ ( ZL + 2RF + 2RP ) α RSN Hybrid Function The hybrid function can easily be implemented utilizing the uncommitted amplifier in conventional CODEC/filter combinations. Please, refer to figure 9. Via impedance ZB a current proportional to VRX is injected into the summing node of the combination CODEC/filter amplifier. As can be seen from the expression for the four-wire to four-wire gain a voltage proportional to VRX is returned to VTX. This voltage is converted by RTX to a current flowing into the same summing node. These currents can be made to cancel by letting: VTX VRX + = 0(EL = 0 ) R TX ZB The four-wire to four-wire gain, G4-4, includes the required phase shift and thus the balance network ZB can be calculated from: V ZB = −RTX ⋅ RX = VTX ZT + G2 −4 S ⋅ ( ZL + 2RF + 2RP ) ZRX α RSN R TX ⋅ ⋅ ZT G2 −4 S ⋅ ( ZL + 2RF + 2RP ) When choosing RTX, make sure the output load of the VTX terminal is >20 kΩ. If calculation of the ZB formula above yields a balance network containing an inductor, an alternate method is recommended. Contact Ericsson Microelectronics for assistance. The PBL 386 21/2 SLIC may also be used together with programmable CODEC/ filters. The programmable CODEC/filter allows for system controller adjustment of PBL 386 21/2 hybrid balance to accommodate different line impedances without change of hardware. In addition, the transmit and receive gain may be adjusted. Please, refer to the programmable CODEC/filter data sheets for design information. RFB RTX VTX Longitudinal Impedance A feed back loop counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase. Thus longitudinal disturbances will appear as longitudinal currents and the TIPX and RINGX terminals will experience very small longitudinal voltage excursions, leaving metallic voltages well within the SLIC common mode range. The SLIC longitudinal impedance per wire, ZLoT and ZLoR, appears as typically 20Ω to longitudinal disturbances. It should be noted that longitudinal currents may exceed the dc loop current without disturbing the vf transmission. Capacitors CTC and CRC The capacitors designated CTC and CRC in figure 11, connected between TIPX and ground as well as between RINGX and ground, can be used for RFI filtering. The recommended value for CTC and CRC is 2200 pF. Higher capacitance values may be used, but care must be taken to prevent degradation of either longitudinal balance or return loss. CTC and CRC contribute to a metallic impedance of 1/(π·f·CTC) = 1/(π·f·CRC), a TIPX to ground impedance of 1/(2·π·f·CTC) and a RINGX to ground impedance of 1/(2·π·f·CRC). AC - DC Separation Capacitor, CHP The high pass filter capacitor connected between terminals HP and TIPX provides the separation of the ac signal from the dc part. CHP positions the low end frequency response break point of the ac loop in the SLIC. Refer to table 1 for a recommended value of CHP. Example: A CHP value of 47 nF will position the low end frequency response 3dB break point of the ac loop at 5.6 Hz (f3dB) according to f3dB = 1/(2⋅π⋅RHP⋅CHP) where RHP = 600 kΩ. High-Pass Transmit Filter The capacitor CTX in figure 11 connected between the VTX output and the CODEC/filter forms, together with RTX and/ or the input impedance of a programmable CODEC/filter, a high-pass RC filter. It is VT PBL 38621/2 ZT Combination CODEC/Filter ZB Z RX V RX RSN Figure 9. Hybrid function. recommended to position the 3 dB break point of this filter between 30 and 80 Hz to get a faster response for the dc steps that may occur at DTMF signalling. Capacitor CLP The capacitor CLP, which connects between the terminals CLP and VBAT, positions the high end frequency break point of the low pass filter in the dc loop in the SLIC. CLP together with CHP and ZT (see section TwoWire Impedance) forms the total two wire output impedance of the SLIC. The choise of these programmable components have an influence on the power supply rejection ratio (PSRR) from VBAT to the two wire side at sub-audio frequencies. At these frequencies capacitor CLP also influences the transversal to longitudinal balance in the SLIC. Table 1 suggests a suitable value on CLP. The typical value of the transversal to longitudinal balance (T-L bal.) at 200Hz is given in table 1 for the chosen value on CLP. RFeed [Ω] RSG [kΩ] CLP T-L bal. @ 200Hz [nF] [dB] [nF] 2·25 0 150 -46 47 CHP Table 1. RSG, CLP and CHP values for constant current feeding characteristics. For values outside table 1, please contact Ericsson Microelectronics for assistance. Battery Feed The PBL 386 21/2 SLIC emulate a battery characteristic with current limitation adjustable.The open loop voltage measured between the TIPX and RINGX terminals is tracking the battery voltage V Bat. The signalling headroom, or overhead voltage VTRO, is programmable with a resistor ROV connected between terminal POV on the SLIC and ground. Please refer to section “Programmable overhead voltage(POV)”. The battery voltage overhead, VOH, depends on the programmed signal overhead voltage VTRO. VOH defines the TIP to RING voltage at open loop conditions according to VTR(at IL = 0 mA) = |VBat| - VOH. Refer to table 2 for the typical value on VOH. SLIC VOH(typ) [V] PBL 386 21/2 2.5 +VTROprog Table 2. Battery overhead. The current limit (reference A - C in figure 12) is adjusted by connecting a resistor, RLC, between terminal PLC and ground according to the equation: RLC = 1000 ILProg + 4 where RLC is in kΩ for ILProg in mA. A second, lower battery voltage may be connected to the device at terminal VBAT2 to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external control. The silent battery 11 PBL 386 21/2 switching occurs when the line voltage passes the value |VB2| - 40 · IL - VTRO = 3.6 For correct functionality it is important to connect the terminal VBAT2 to the second power supply via the diode DVB2 in figure 11. An optional diode DBB connected between terminal VB and the VB2 power supply, see figure 11, will make sure that the SLIC continues to work on the second battery even if the first battery voltage disappears. If a second battery voltage is not used, VBAT2 is connected to VBAT on the SLIC and CVB2, DBB and DVB2 are removed. CODEC Receive Interface The PBL 386 21/2 SLIC have got a completely new receive interface at the four wire side which makes it possible to reduce the number of capacitors in the applications and to fit both single and dual battery feed CODECs. The RSN terminal, connecting to the CODEC receive output via the resistor RRX, is dc biased with +1.25V. This makes it possible to compensate for currents floating due to dc voltage differences between RSN and the CODEC output without using any capacitors. This is done by connecting a resistor RR between the RSN terminal and ground. With current directions defined as in figure 13, current summation gives: −IRSN = IRT + IRRX + IRR = 1, 25 125 , − VCODEC 125 , + + RT RRX RR where VCODEC is the reference voltage of the CODEC at the receive output. From this equation the resistor RR can be calculated as 125 , RR = , − VCODEC 1, 25 125 −IRSN − − RT RRX For the value on IRSN, see table 3. The resistor RR has no influence on the ac transmission. SLIC IRSN [µA] PBL 386 21/2 -55 Table 3. The SLIC internal bias current with the direction of the current defined as positive when floating into the terminal RSN. 12 Programmable overhead voltage(POV) Loop Monitoring Functions With the POV function the overhead voltage can be increased. If the POV pin is left open the overhead voltage is internally set to 1.1 VPeak. The overhead voltage is equal in on-hook and off-hook. If a resistor ROV is connected between the POV pin and AGND, the overhead voltage can be set to higher values, typical values can be seen in figure 10. The ROV and corresponding VTRO (signal headroom) are typical values for THD <1% and the signal frequency 1000Hz. Observe that the 4-wire output terminal VTX can not handle more than 3.2 VPeak. So if the gain 2-wire to 4-wire is 0dB, 3.2 VPeak is maximum also for the 2-wire side. Signal levels between 3.2 and 6.4 VPeak on the 2-wire side can be handled with the PTG shorted so that the gain G2-4S become -6.02dB. Please note that the 2-wire impedance, RR and the 4-wire to 4-wire gain has to be recalculated if the PTG is shorted. Please note that the maximum signal current at the 2-wire side can not be greater than 9 mA. The loop current, ground key and ring trip detectors report their status through a common output, DET. The detector to be connected to DET is selected via the three bit wide control interface C1, C2 and C3. Please refer to section Control Inputs for a description of the control interface. How to use POV: 1. Decide what overhead voltage(VTRO) is needed. The POV function is only needed if the overhead voltage exceeds 1.1 VPeak 2. In figure 10 the corresponding ROV for the decided VTRO can be found. 3. If the overhead voltage exceeds 3.2 VPeak, the G2-4S gain has to be changed to -6.02dB by connecting the PTG pin to AGND. Please note that the 2-wire impedance, RR and the 4-wire to 4-wire gain has to be recalculated. Analog Temperature Guard The widely varying environmental conditions in which SLICs operate may lead to the chip temperature limitations being exceeded. The PBL 386 21/2 SLIC reduce the dc line current when the chip temperature reaches approximately 145°C and increases it again automatically when the temperature drops. Accordingly transmission is not lost under high ambient temperature conditions. The detector output, DET, is forced to a logic low level when the temperature guard is active. Loop Current Detector The loop current detector is indicating that the telephone is off hook and that current is flowing in the loop by putting the output DET to a logical low level when selected. The loop current threshold value, ILTh, at which the loop current detector changes state is programmable by selecting the value of resistor RLD. RLD connects between pin PLD and ground and is calculated according to RLD = 500 ILTh The current detector is internally filtered and is not influenced by the ac signal at the two wire side. Ground Key Detector The ground key detector is indicating when the ground key is pressed (active) by putting the output pin DET to a logical high level when selected. The ground key detector circuit senses the difference in TIPX and RINGX currents. When the current at the RINGX side exceeds the current at the TIPX side with the threshold value the detector is triggered. For threshold current values, please refer to the datasheet. Ring Trip Detector Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. The ringing source can be balanced or unbalanced superimposed on VB or GND. The unbalanced ringing source may be applied to either the ring lead or the tip lead with return via the other wire. A ring relay driven by the SLIC ring relay driver connects the ringing source to tip and ring. The ring trip function is based on a polarity change at the comparator input when the line goes off-hook. In the on-hook state no dc current flows through the loop and the voltage at comparator input DT is more positive than the voltage at input DR. When the line goes off-hook, while the ring relay PBL 386 21/2 7 VTRO (VPeak) 6 5 4 3 2 1 0 0 10 20 30 40 50 60 ROV (kΩ) Figure 10. Programmable overhead voltage (POV). RL = 600 Ω or ∞. is energized, dc current flows and the comparator input voltage reverses polarity. Figure 11 gives an example of a ring trip detection network. This network is applicable, when the ring voltage is superimposed on VB and is injected on the ring lead of the two-wire port. The dc voltage across sense resistor RRT is monitored by the ring trip comparator input DT and DR via the network R1, R2, R3, R4, C1 and C2. With the line on-hook (no dc current) DT is more positive than DR and the DET output will report logic level high, i.e. the detector is not tripped. When the line goes off-hook, while ringing, a dc current will flow through the loop including sense resistor RRT and will cause input DT to become more negative than input DR. This changes output DET to logic level low, i.e. tripped detector condition. The system controller (or line card processor) responds by deenergizing the ring relay, i.e. ring trip. Complete filtering of the 20 Hz ac component at terminal DT and DR is not necessary. A toggling DET output can be examined by a software routine to determine the duty cycle. When the DET output is at logic level low for more than half the time, off-hook condition is indicated. Relay driver Ringing State The PBL 386 21/2 SLIC incorporates a ring relay driver designed as open collector (npn) with a current sinking capability of 50 mA. The drive transistor emitter is connected to BGND. The relay driver has an internal zener diode clamp for inductive kick-back voltages.Care must be taken when using the relay driver together with relays that have high impedance. The ring relay driver and the ring trip detector are activated and the ring trip detector is indicating off hook with a logic low level at the detector output. As the SLIC do not have any stand by state the SLIC will remain in the active normal state. Control Inputs The PBL 386 21/2 SLIC has three digital control inputs, C1, C2 and C3. A decoder in the SLIC interprets the control input condition and sets up the commanded operating state. C1 to C3 are internal pull-up inputs. Open Circuit State Active States TIPX is the terminal closest to ground and sources loop current while RINGX is the more negative terminal and sinks loop current. Vf signal transmission is normal. The loop current or the ground key detector is activated. The loop current detector is indicating off hook with a logic low level and the ground key detector is indicating active ground key with a logic high level present at the detector output. In the Open Circuit State the TIPX and RINGX line drive amplifiers as well as other circuit blocks are powered down. This causes the SLIC to present a high impedance to the line. Power dissipation is at a minimum and no detectors are active. 13 PBL 386 21/2 R FB PBL 386 21/2 C TX KR PTG R TX - VTX - 0 +12 V /+5V RRLY RT AGND R RX C GG D HP R F2 RING HP RSN NC NC + + RB 0 C HP CODEC/ Filter RR R P2 REF R REF BGND PLC R LC TIPX POV R OV VBAT PLD R LD VBAT2 VCC VCC RINGX C RC TIP VB OVP R F1 C TC R P1 D VB2 VB2 D BB D VB PBL 386 21/2 VCC R SG C VB2 VB C VB PSG NC NC DET LP C1 DT C2 DR C3 C VCC C LP E RG R1 R RT R2 C1 C2 R3 SYSTEM CONTROL INTERFACE R4 SLIC No. 2 etc. RESISTORS (Values according to IEC E96 series): =0Ω 1% 1/10 W RSG = 49.9 kΩ 1% 1/10 W RLD ROV = User programmable = 38.3 kΩ 1% 1/10 W RLC = 49.9 kΩ 1% 1/10 W RREF RR = 64.9 kΩ 1% 1/10 W = 105 kΩ 1% 1/10 W RT = 24.9 kΩ 1% 1/10 W RTX RB = 22.1 kΩ 1% 1/10 W = 52.3 kΩ 1% 1/10 W RRX Depending on CODEC/filter RFB R1 = 604 kΩ 1% 1/10 W = 604 kΩ 1% 1/10 W R2 = 249 kΩ 1% 1/10 W R3 R4 = 280 kΩ 1% 1/10 W = 330 Ω 5% 2 W RRT 1% 1/10 W (Note 1) R , RP2 ≥ 10 Ω P1 RF1, RF2 = Line resistor, 40 Ω 1% CAPACITORS (Values according to IEC E96 series): = 100 nF 100 V 10% CVB = 150 nF 100 V 10% CVB2 = 100 nF 10 V 10% CVCC CTC = 2.2 nF 100 V 10% = 2.2 nF 100 V 10% CRC = 47 nF 100 V 10% CHP CLP = 150 nF 100 V 10% = 100 nF 10 V 10% CTX = 220 nF 100 V 10% CGG C1 = 330 nF 63 V 10% = 330 nF 63 V 10% C2 DIODES: = 1N4448 DVB = 1N4448 DVB2 = 1N4448 DBB DHP = 1N4448 (Note 2) OVP: Secondary protection (e. g. Power Innovations TISPPBL2). The ground terminals of the secondary protection should be connected to the common ground on the Printed Board Assembly with a track as short and wide as possible, preferable a groundplane. NOTES: 1 RP1 and RP2 may be omitted if DVB is in place 2 It is required to connect DHP between terminal HP and ground if CHP > 47 nF Figure 11. single-channel subscriber line interface with PBL 386 21/2 and combination CODEC/filter. Overvoltage Protection The PBL 386 21/2 SLIC must be protected against overvoltages on the telephone line caused by lightning, ac power contact and induction. Refer to Maximum Ratings, TIPX and RINGX terminals, for maximum allowable continuous and transient currents that may be applied to the SLIC. Secondary Protection The circuit shown in figure 11 utilizes series resistors together with a programmable overvoltage protector (e.g Power Innovations TISPPBL2), serving as a secondary protection. The TISPPBL2 is a dual forward-conducting buffered p-gate overvoltage protector. The protector gate references the protection (clamping) voltage to negative supply voltage (i.e the battery voltage,VB ). 14 As the protection voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimized. Positive overvoltages are clamped to ground by a diode. Negative overvoltages are initially clamped close to the SLIC negative supply rail voltage and the protector will crowbar into a low voltage on-state condition, by firing an internal thyristor. A gate decoupling capacitor, CGG, is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. CGG shall be placed close to the overvoltage protection device. Without the capacitor even the low inductance in the track to the VBat supply will limit the current and delay the activation of the thyristor clamp. The fuse resistors RF serve the dual purposes of being non- destructive energy dissipators, when transients are clamped and of being fuses, when the line is exposed to a power cross. If a PTC is choosen for RF, note that it is important to always use PTC´s in series with resistors not sensitive to temperature, as the PTC will act as a capacitance for fast transients and therefore will not protect the SLIC. PBL 386 21/2 DC characteristics A B C I L [mA] D E V TR [V] A: IL(@VTR=0V)=ILProg D: RFeed=2·25 Ω B: Constant current E: VTROpen=|VBat|-VOH C: ILConst(typ) = ILProg = 103 - 4·10-3 RLC VTR=|VBat|-VOH-50·ILProg Figure 12. Battery feed characteristics (without the protection resistors on the line). VTX PBL386 21/2 DC-GND CODEC RT I IRT RSN IRSN IRRX RRX _ + +1.25 V IRR UREFcodec RR Figure 13. CODEC receive interface. 15 PBL 386 21/2 Power-up Sequence No special power-up sequence is necessary except that ground has to be present before all other power supply voltages. Printed Circuit Board Layout Care in PCB layout is essential for proper function. The components connecting to the RSN input should be placed in close proximity to that pin, such that no interference is injected into the RSN pin. Ground plane surrounding the RSN pin is advisable. Analog ground (AGND) should be connected to battery ground (BGND) on the PCB in one point.The capacitors for the battery should be connected with short wide leads of the same length. Ordering Information Package 24 pin SSOP Tape & Reel 24 pin SOIC Tube 24 pin SOIC Tape & Reel 28 pin PLCC Tube 28 pin PLCC Tape & Reel Temp. Range -40° - +85° C -40° - +85° C -40° - +85° C -40° - +85° C -40° - +85° C Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics AB. These products are sold only according to Ericsson Microelectronics AB' general conditions of sale, unless otherwise confirmed in writing. Specifications subject to change without notice. 1522-PBL 386 21/2 Uen Rev. A © Ericsson Microelectronics AB 1999 This product is an original Ericsson product protected by US, European and other patents. Ericsson Microelectronics AB SE-164 81 Kista-Stockholm, Sweden Telephone: +46 8 757 50 00 16 Part No. PBL 386 21/2SHT PBL 386 21/2SOS PBL 386 21/2SOT PBL 386 21/2QNS PBL 386 21/2QNT