MP7628 5 V CMOS Quad Multiplying 8-Bit Digital-to-Analog Converter FEATURES APPLICATIONS • • • • • • • • • • Microprocessor Controlled Gain and Attenuation Circuits • Microprocessor Controlled/Programmable Power Supplies • Hardware Redundant Applications Requiring Data Readback Readback Capability for all DACs On-Chip Latches for All DACs Linearity Grades to +1/8 LSB Single Supply Voltage (5 Volt) DACs Matched to 1% Four Quadrant Multiplication Microprocessor TTL/CMOS Compatible Latch-Up Free Dual Version: MP7529B Data is transferred into any of the four DAC data latches via common 8-bit TTL/CMOS compatible input port. Control inputs DS1, DS2 and A/B determine which DAC is to be loaded. The MP7628’s load cycle is similar to the write cycle of a random access memory and the device is bus compatible with most 8-bit microprocessors. GENERAL DESCRIPTION The MP7628 is a quad 8-bit Digital-to-Analog Converter designed using a decoded DAC architecture featuring excellent DAC-to-DAC matching and guaranteed monotonicity. Separate on-chip latches are provided for each DAC to allow easy microprocessor interface. The device operates at +5 V power supply and dissipates less than 5mW. The readback function allows the user to poll or read the data latches, eliminating the need for storing information in RAM. In the event the microprocessor power supply is interrupted, it can poll the DACs to establish the last known system state. All DACs offer excellent four quadrant multiplication characteristics with a separate reference input and feedback resistor for each DAC. SIMPLIFIED BLOCK DIAGRAM VDD VREFB VREFA LATCH A RFB DAC A DB0 (LSB) DATA BUS DB7 (MSB) IOUT1A THREE-STATE BUFFER BIDIRECTIONAL LINE DRIVER RFBA IOUT2A/ IOUT2B LATCH B IOUT1B DAC B THREE-STATE BUFFER RFB LATCH C RFB RFBB RFBC IOUT1C DAC C THREE-STATE BUFFER IOUT2C/ IOUT2D A/B R/W CONTROL LOGIC LATCH D DS1 DAC D THREE-STATE BUFFER DS2 GND VREFC VREFD Rev. 2.00 1 IOUT1D RFB RFBD MP7628 ORDERING INFORMATION Package Type Temperature Range Part No. INL (LSB) DNL (LSB) Gain Error (% FSR) Plastic Dip –40 to +85°C MP7628JN +1/2 +1/2 +1.8 Plastic Dip –40 to +85°C MP7628KN +1/4 +1/4 +0.9 SOIC –40 to +85°C MP7628JS +1/2 +1/2 +1.8 SOIC –40 to +85°C MP7628KS +1/4 +1/4 +0.9 PLCC –40 to +85°C MP7628JP +1/2 +1/2 +1.8 PLCC –40 to +85°C MP7628KP +1/4 +1/4 +0.9 Ceramic Dip –40 to +85°C MP7628AD +1/2 +1/2 +1.8 Ceramic Dip –40 to +85°C MP7628BD +1/4 +1/4 +0.9 Ceramic Dip –55 to +125°C MP7628SD* +1/2 +1/2 +1.8 Ceramic Dip –55 to +125°C MP7628TD* +1/4 +1/4 +0.9 *Contact factory for non-compliant military processing PIN CONFIGURATIONS See Packaging Section for Package Dimensions VDD VREFA RFBA IOUT1A IOUT2A/IOUT2B IOUT1B RFBB VREFB (LSB) DB0 DB1 DB2 DB3 DB4 DB5 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 GND VREFC RFBC IOUT1C IOUT2C/IOUT2D IOUT1D RFBD VREFD DS2 DS1 R/W A/B DB7 (MSB) DB6 IOUT1A VREFA GND RFBC RFBA VDD VREFC 1 28 2 27 3 26 4 25 5 6 7 24 See Pin Out at Left 4 IOUT2A/ IOUT2B IOUT1B 2 26 25 6 24 IOUT1C IOUT2C/ IOUT2D IOUT1D RFBB 7 23 8 22 RFBD 9 21 VREFD 10 20 DS2 11 19 DS1 20 10 19 11 18 DB2 12 17 13 16 14 15 21 28 Pin SOIC (Jedec, 0.300”) S28 2 27 22 9 Rev. 2.00 28 5 12 13 DB3 14 15 16 17 DB5 DB4 28 Pin CDIP, PDIP (0.600”) D28, N28 1 23 VREFB DB0 (LSB) DB1 8 3 18 DB7 R/W (MSB) DB6 A/B 28 Pin PLCC P28 MP7628 PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION 1 VDD Power Supply 2 VREFA Reference Voltage for DAC A 3 RFBA Feedback Resistor for DAC A 4 IOUT1A Current Output 1 DAC A 5 IOUT2A/ IOUT2B Current Output 2 DAC A/DAC B 6 IOUT1B Current Output 1 DAC B 7 RFBB Feedback Resistor for DAC B 8 VREFB Reference Voltage for DAC B 9 DB0 Data Input Bit 0 (LSB) 10 DB1 Data Input Bit 1 11 DB2 Data Input Bit 2 12 DB3 Data Input Bit 3 13 DB4 Data Input Bit 4 14 DB5 Data Input Bit 5 15 DB6 Data Input Bit 6 16 DB7 Data Input Bit 7 (MSB) 17 A/B DAC Selection 18 R/W Read/Write 19 DS1 Control 1 20 DS2 Control 2 21 VREFD Reference Voltage for DAC D 22 RFBD Feedback Resistor for DAC D 23 IOUT1D Current Output 1 DAC D 24 IOUT2C/ IOUT2D Current Output 2 DAC C/DAC D 25 IOUT1C Current Output 1 DAC C 26 RFBC Feedback Resistor for DAC C 27 VREFC Reference Voltage for DAC C 28 GND Ground Rev. 2.00 3 MP7628 ELECTRICAL CHARACTERISTICS (VDD = + 5 V, VREF = +10 V unless otherwise noted) Parameter Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) J, A, S K, B, T Differential Non-Linearity J, A, S K, B, T Gain Error J, A, S K, B, T Test Conditions/Comments FSR = Full Scale Range N 8 8 Bits INL LSB End Point Linearity Spec. LSB All grades monotonic over full temperature range. % FSR Using Internal RFB Digital Inputs = VINH +2 ppm/°C ∆Gain/∆Temperature +1/2 +1/4 +1/2 +1/4 +1/2 +1/4 +1/2 +1/4 +1.5 +0.8 +1.8 +0.9 DNL GE Gain Temperature Coefficient2 TCGE Power Supply Rejection Ratio PSRR +200 +400 ppm/% |∆Gain/∆VDD| ∆VDD = + 5% Digital Inputs = VINH Output Leakage Current (all) IOUT1 +50 +200 nA Digital Inputs = VINL +20 28 V kΩ 0.8 +1 0.8 +10 V V µA pF +1 +10 REFERENCE INPUT Voltage Range2 Input Resistance RIN +20 28 12 12 DIGITAL INPUTS3 Logic Thresholds VINH VINL Input Leakage Current Input Capacitance2 2.4 ILKG CIN 2.4 3 DATA BUS OUTPUTS Output Capacitance2 Input Leakage Current COUT ILKG 7 pF µA ANALOG OUTPUTS Propagation Delay2 500 750 ns From digital input to 90% of final analog output current 440 pF pF nVs DAC Inputs all 1’s DAC Inputs all 0’s Typical for code transition from all 0’s to all 1’s Output Capacitance2 COUT COUT Glitch Energy2 120 80 160 Rev. 2.00 4 MP7628 ELECTRICAL CHARACTERISTICS (CON’T) Parameter Symbol Min VDD IDD 4.5 tW tDSW 320 200 40 480 240 320 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments POWER SUPPLY5 Functional Voltage Range2 Supply Current 5.5 50 4.5 5.5 50 V µA All digital inputs = 0 V or all = 5 V SWITCHING CHARACTERISTICS2, 4 Data Write Time Write Strobe Req. Data Hold Time Data Read Time 3-state Hold Time Read Strobe Req. tDHLD tR tTSHD tDSR 400 250 50 600 300 400 ns ns ns ns ns ns NOTES: 1 2 3 4 5 Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. See timing diagrams. Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 seconds) . . . . . . +300°C Package Power Dissipation Rating to 75°C CDIP, PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . 1050mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 14mW/°C VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Digital Input Voltage to GND (2) . GND –0.5 to VDD +0.5 V IOUT1, IOUT2 to GND (2) . . . . . . . . GND –0.5 to VDD +0.5 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. Rev. 2.00 5 MP7628 TIMING DIAGRAM READ CYCLE A/B R/W tS DS1 DS2 tNR tDSR H tD BUS (D N ) tD 3-state Data (A) 3-state Set up time for BUS, A/B, R/W Minimum DS = low pulse Minimum time between DS = low pulses Data delay time tR = tDSR + tNR = 40 ns = 320 ns = 120 ns = 200 ns Data (B) tS tDSR (min) tNR tD TIMING DIAGRAM WRITE CYCLE DATA (DN ) Data (A) A/B Data (B) A Select B Select tDHLD R/W DS1 H L DS2 H tS tNW tDSW tD DAC A OUT Last Data Data (A) tS + tD DAC B OUT Last Data Set up time for BUS, A/B, R/W Minimum DS = low pulse Minimum time between DS = low pulses Data delay time tW = tDSW + tNW Data (B) = 40 ns = 200 ns = 120 ns = 110 ns tS tDSW (min) tNW tD MODE SELECTION TABLE DS1 DS2 L L H H L L H H L L H L L H H L L H H L L L L H L L A/B R/W MODE DAC L L L L H H H H L L X H H WRITE WRITE WRITE WRITE READ READ READ READ WRITE WRITE HOLD HOLD HOLD A B C D A B C D A&C B&D A/B/C/D A/B/C/D A/B/C/D H L H L H L H L H L X H L Rev. 2.00 6 L = LOW STATE H = HIGH STATE X = DON’T CARE MP7628 DAC are transparent and its analog output responds to activity on DB0-DB7. INTERFACE LOGIC INFORMATION DAC Selection: All DAC latches share a common 8-bit input port. The control inputs DS1, DS2, A/B select which DAC can accept data from the input port. Hold Mode: The selected DAC latch retains the data which was present on DB0-DB7 just prior to DS and R/W assuming a high state. Both analog outputs remain at the values corresponding to the data in their respective latches. Mode Selection: Inputs DS and R/W control the operating mode of the selected DAC. See Mode Selection Table on the previous page. Read Mode: When DS is low and R/W is high, the selected DAC is in the read mode and the data held in the appropriate latch is outputed to the data bus. Write Mode: When DS and R/W are both low the selected DAC is in the write mode. The input data latches of the selected APPLICATION NOTES Refer to Section 8 for Applications Information Rev. 2.00 7 MP7628 28 LEAD CERAMIC DUAL-IN-LINE (600 MIL CDIP) D28 S S1 28 15 1 14 See Note 1 E1 E D Q Base Plane Seating Plane A L c e b INCHES SYMBOL A L1 b1 NOTES MILLIMETERS MIN MAX MIN MAX –– 0.232 –– 5.89 NOTES –– b 0.014 0.023 0.356 0.584 –– b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– D –– 1.490 –– 37.85 4 E 0.500 0.610 12.70 15.49 4 E1 0.590 0.620 14.99 15.75 7 e 0.100 BSC 2.54 BSC 5 L 0.125 0.200 3.18 5.08 –– L1 0.150 –– 3.81 –– –– Q 0.015 0.060 0.381 1.52 3 S –– 0.100 –– 2.54 6 0.005 –– 0.13 –– 6 0° 15° 0° 15° –– S1 α α Rev. 2.00 8 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. MP7628 28 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) N28 S 28 15 E1 1 14 Q1 E D A1 Seating Plane A L B e B1 α MILLIMETERS INCHES SYMBOL A MIN MAX MIN MAX –– 0.232 –– 5.893 A1 0.015 –– 0.381 –– B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 1.380 1.490 35.05 37.85 E 0.585 0.625 14.86 15.88 E1 0.500 0.610 12.70 15.49 e 0.100 BSC L 0.115 α 0.150 2.54 BSC 2.92 3.81 0° 15° 0° 15° Q1 0.055 0.070 1.40 1.78 S 0.020 0.100 1.508 2.54 Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 9 C MP7628 28 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S28 D 28 15 E H 14 h x 45° C A Seating Plane α B e A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.097 0.104 2.464 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.483 C 0.0091 0.0125 0.231 0.318 D 0.701 0.711 17.81 18.06 E 0.292 0.299 7.42 7.59 e 0.050 BSC MAX 2.642 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° Rev. 2.00 10 MP7628 28 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) P28 D D1 Seating Plane A2 1 B D D1 D2 e1 C D3 A1 A INCHES SYMBOL MILLIMETERS MIN MAX MIN MAX A 0.165 0.180 4.19 4.57 A1 0.100 0.110 2.54 2.79 A2 0.148 0.156 3.76 3.96 B 0.013 0.021 0.330 0.533 C 0.008 0.012 0.203 0.305 D 0.485 0.495 12.32 12.57 D1 (1) 0.450 0.454 11.43 11.53 D2 0.390 0.430 9.91 10.92 D3 0.300 Ref 7.62 Ref. e1 0.050 BSC 1.27 BSC Note: (1) Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in. Rev. 2.00 11 MP7628 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 12