MP7626 Microprocessor Compatible Buffered Multiplying 16-Bit Digital-to-Analog Converter FEATURES APPLICATIONS • • • • • • • • • • • • • Four Quadrant Multiplication 16-Bit Monotonicity Low Power Consumption TTL/5 V CMOS Compatible Single-Buffered or Transparent Data inputs Decoded DAC Approach Latch-Up Free 8-Bit Bus Version: MP7636A Digitally Programmable References Programmable Audio Attenuator High Accuracy Process Control Systems Automatic Test Equipment Easy Interface to 8 and 16-Bit Microprocessor Buses excellent accuracy over temperature and time. 16 bit differential non-linearity is achieved with minimal trimming. GENERAL DESCRIPTION Two 8-bit latches (MSB latch and LSB latch) hold the 16-bit data which are converted by the DAC. A 16-bit bus can load both latches in one cycle. An 8-bit bus loads one latch at a time. By making the latches transparent (MSB latch = LSB latch = High) the DAC will continuously convert the BIT1 - BIT16 inputs. The MP7626 is a CMOS 16-bit Digital-to-Analog Converter (DAC) that is manufactured using advanced thin film resistors on a double metal CMOS process. It incorporates a unique bit decoding technique yielding lower glitch, higher speed and SIMPLIFIED BLOCK AND TIMING DIAGRAM VDD VREF DB15-DB8 MSB Latch D Q Latch E 8 DATA 16 16 LATCH RFB DB7-DB0 LSB Latch D Q Latch E 8 16-Bit Multiplying DAC IOUT1 IOUT2 GND Rev. 2.00 1 OUTPUT MP7626 ORDERING INFORMATION Package Type Temperature Range Part No. INL (LSB) DNL (LSB) Gain Error (% FSR) Plastic Dip –40 to +85°C MP7626JN +4 +4 +0.1 Plastic Dip –40 to +85°C MP7626KN +2 +2 +0.1 PLCC –40 to +85°C MP7626JP +4 +4 +0.1 PLCC –40 to +85°C MP7626KP +2 +2 +0.1 Ceramic Dip –40 to +85°C MP7626JD* +4 +4 +0.1 Ceramic Dip –40 to +85°C MP7626KD* +2 +2 +0.1 *Recommend using MP7626KN or JN PIN CONFIGURATION See Packaging Section for Package Dimensions DB6 DB4 N/C DB8 N/C DB7 DB5 4 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 (MSB) DB15 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 DB3 DB2 DB1 DB0 (LSB) MSB LATCH LSB LATCH GND VDD IOUT1 IOUT2 RFB VREF 3 2 1 28 27 26 DB9 5 25 DB3 DB10 6 24 DB2 DB11 7 23 DB1 DB12 8 22 DB0 (LSB) DB13 9 21 MSB LATCH DB14 10 20 LSB LATCH (MSB) DB15 11 19 GND 12 13 14 15 16 17 18 N/C RFB IOUT1 N/C VREF IOUT2 VDD 24 Pin PDIP, CDIP (0.600”) N24, D24, C24 28 Pin PLCC P28 PIN OUT DEFINITIONS DIP 1 2 3 4 5 6 7 8 9 10 11 12 PLCC NAME 26 27 28 1 2 5 6 7 8 9 10 11 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DESCRIPTION DIP Data Input Bit 4 Data Input Bit 5 Data Input Bit 6 Data Input Bit 7 Data Input Bit 8 Data Input Bit 9 Data Input Bit 10 Data Input Bit 11 Data Input Bit 12 Data Input Bit 13 Data Input Bit 14 Data Input Bit 15 (MSB) 13 14 15 16 17 18 19 20 21 22 23 24 Rev. 2.00 2 PLCC NAME 13 14 15 16 17 19 20 21 22 23 24 25 VREF RFB IOUT2 IOUT1 VDD GND LSB MSB DB0 DB1 DB2 DB3 DESCRIPTION Reference Input Voltage Internal Feedback Resistor Pin Current Output 2 Current Output 1 Power Supply Ground LSB Latch Enable MSB Latch Enable Data Input Bit 0 (LSB) Data Input Bit 1 Data Input Bit 2 Data Input Bit 3 MP7626 ELECTRICAL CHARACTERISTICS (VDD = + 15 V, VREF = +10 V unless otherwise noted) Parameter Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units STATIC PERFORMANCE1 Resolution (All Grades) Relative Accuracy J K Differential Non-Linearity J K Gain Error FSR = Full Scale Range N 16 16 Bits INL LSB +4 +2 +4 +2 +4 +2 +0.1 +0.1 % FSR Using Internal RFB +2 ppm/°C ∆Gain/∆Temperature ppm/% |∆Gain/∆VDD| ∆VDD = + 5% nA IOUT1 DNL LSB GE TCGE Power Supply Rejection Ratio PSRR +50 +50 IOUT +10 +200 DYNAMIC PERFORMANCE2 Current Settling Time AC Feedthrough at IOUT1 Best Fit Straight Line Spec. (Max INL – Min INL) / 2 +4 +2 Gain Temperature Coefficient2 Output Leakage Current Test Conditions/Comments RL=100Ω, CL=13pF tS FT µs mV p-p 2 2 Full Scale Change to 0.1% VREF = 10kHz, 20 Vp-p, sinewave REFERENCE INPUT Input Resistance RIN 2.5 VIH VIL 3.0 7.5 2.5 7.5 kΩ 0.8 +1 V V µA DIGITAL INPUTS3 Logical “1” Voltage Logical “0” Voltage Input Leakage Current Input Capacitance2 Data Control 2.4 3.0 0.8 +1 ILKG CIN CIN 5 5 pF pF ANALOG OUTPUTS2 Output Capacitance 280 120 100 240 COUT1 COUT1 COUT2 COUT2 pF pF pF pF DAC Inputs all 1’s DAC Inputs all 0’s DAC Inputs all 1’s DAC Inputs all 0’s V mA All digital inputs = 0 V or all = 5 V POWER SUPPLY Functional Voltage Range5 Supply Current VDD IDD 4.5 16.5 1 Rev. 2.00 3 5.0 16.5 1 MP7626 ELECTRICAL CHARACTERISTICS (CON’T) Parameter Symbol Min tDS tSW 250 125 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments SWITCHING CHARACTERISTICS2, 4 Data Valid to Write Set-Up Time Write Strobe Width ns ns NOTES: 1 Full Scale Range (FSR) is 10V for unipolar mode. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See timing diagram. 5 Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 Storage Temperature Range . . . . . . . . . . . . –65°C to 150°C Package Power Dissipation Rating to 75°C CDIP, PDIP, PLCC . . . . . . . . . . . . . . . . . . . . . . . 1050mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 14mW/°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 VDC Voltage at Any Digital Input . . . . . GND –0.5 to VDD +0.5 V DC Voltage Applied to IOUT1 or IOUT2 . . GND –0.5 to +17 V Voltage at VREF, RFB Inputs . . . . . . . . . . . . . . . . . . . . . . +25 V NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. APPLICATION NOTES Refer to Applications Section for Additional Information LATCH CONTROL TIMING DIAGRAM Data Changing Data Stable MSB LATCH LSB LATCH 0 0 Data Latched (Held) 1 0 Transfer (DB15-DB8) to DAC 0 1 Transfer (DB7-DB0) to DAC 1 1 Transparent Mode ÉÉÉ ÉÉÉÉÉÉ ÉÉ ÉÉÉ ÉÉÉÉÉÉ ÉÉ FUNCTION DATA LATCH tS OUTPUT tDS Rev. 2.00 4 tSW MP7626 LSB PERFORMANCE CHARACTERISTICS Graph 1. Relative Accuracy vs. Digital Code APPLICATION NOTES Refer to Section 8 for Applications Information Rev. 2.00 5 MP7626 24 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) N24 S 24 13 E1 1 12 Q1 E D A1 Seating Plane A L B e B1 α MILLIMETERS INCHES SYMBOL A MIN MAX MIN –– 0.225 –– MAX 5.72 A1 0.015 –– 0.38 –– B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 1.160 1.290 29.46 32.77 E 0.585 0.625 14.86 15.88 E1 0.500 0.610 12.70 15.49 e 0.100 BSC 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q1 0.055 0.070 1.40 1.78 S 0.040 0.098 1.02 2.49 Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 6 C MP7626 24 LEAD CERAMIC DUAL-IN-LINE (600 MIL CDIP) D24 S S1 24 13 1 12 See Note 1 E1 E D Q Base Plane Seating Plane A L c e b L1 b α 1 INCHES SYMBOL A NOTES MILLIMETERS MIN MAX MIN MAX –– 0.225 –– 5.72 NOTES –– b 0.014 0.023 0.356 0.584 –– b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– D –– 1.290 –– 32.77 4 E 0.500 0.610 12.70 15.49 4 E1 0.590 0.620 14.99 15.75 7 e 0.100 BSC 2.54 BSC 5 L 0.120 0.200 3.05 5.08 –– L1 0.150 –– 3.81 –– –– Q 0.015 0.075 0.381 1.91 3 S –– 0.098 –– 2.49 6 0.005 –– 0.13 –– 6 0° 15° 0° 15° –– S1 α Rev. 2.00 7 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. MP7626 24 LEAD CERAMIC SIDE-BRAZED DUAL-IN-LINE (600 MIL S/B DIP) C24 S S1 24 13 1 12 E D Q Base Plane Seating Plane A L c e b INCHES SYMBOL b1 MIN MAX A –– 0.225 –– 5.72 –– b 0.014 0.023 0.356 0.584 –– MAX NOTES b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– D –– 1.290 –– 32.77 4 E 0.500 0.610 12.70 15.49 4 E1 0.590 0.620 14.99 15.75 7 e 0.100 BSC 2.54 BSC 5 L 0.120 0.200 3.05 5.08 –– L1 0.150 –– 3.81 –– –– Q 0.015 0.075 0.381 1.91 3 S –– 0.098 –– 2.49 6 0.005 –– 0.13 –– 6 S1 E1 NOTES MILLIMETERS MIN L1 Rev. 2.00 8 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. E1 shall be measured at the centerline of the leads. MP7626 28 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) P28 D D1 Seating Plane A2 1 B D D1 D2 e1 C D3 A1 A INCHES SYMBOL MILLIMETERS MIN MAX MIN MAX A 0.165 0.180 4.19 4.57 A1 0.100 0.110 2.54 2.79 A2 0.148 0.156 3.76 3.96 B 0.013 0.021 0.330 0.533 C 0.008 0.012 0.203 0.305 D 0.485 0.495 12.32 12.57 D1 (1) 0.450 0.454 11.43 11.53 D2 0.390 0.430 9.91 10.92 D3 0.300 Ref 7.62 Ref. e1 0.050 BSC 1.27 BSC Note: (1) Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in. Rev. 2.00 9 MP7626 Notes Rev. 2.00 10 MP7626 Notes Rev. 2.00 11 MP7626 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 12