October 1992 DP83220 CDL TM Twisted Pair FDDI Transceiver Device General Description Features The Copper Data Link (CDL) Transceiver is an integrated circuit designed to interface directly with the National Semiconductor FDDI Chip Set or other FDDI PHY silicon, allowing low cost FDDI compatible data links over copper based media. The DP83220 Transceiver, with the proper compensation selected, will allow links of up to 100 meters over both Shielded Twisted Pair (STP) and Datagrade unshielded Twisted Pair (DTP). CDL surpasses a Bit Error Rate (BER) of k1 c 10b12 over both STP and DTP. The CDL is designed to meet the SDDI specification for FDDI transmission across Type 1 STP cable when used in conjunction with the appropriate transformer/filter module from Pulse Engineering. Y Y Y Y Y Y Y Y Fully compatible with current FDDI PHY standard Fully compatible with the SDDI PMD specification Requires a single a 5V supply Isolated TX and RX power supplies for minimum noise coupling Allows use of Type 1 STP and Category 5 DTP cables No Transmit Clock required Loopback feature for board diagnostics Link Detect input provided Block Diagram Transmit Section TL/F/11724 – 1 Receive Section TL/F/11724 – 2 FIGURE 1. DP83220 Transceiver Block Diagram CDLTM , CDDTM , CRDTM and PLAYERTM are trademarks of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/11724 RRD-B30M105/Printed in U. S. A. DP83220 CDL Twisted Pair FDDI Transceiver Device ADVANCE INFORMATION 1.0 Functional Description is routed to the differential 100K Output Driver. When in Loopback mode, the Signal Detect output driver is forced true. When receiving data from copper media, the signal detect circuit provides valid states to the Signal Detect output driver depending on the amplitude of the incoming signal and also allows the PMID g outputs to switch. Cable Detect is the final gating function for data reception. If no media is detected, the transceiver will generate a logic low Signal Detect which will inhibit data reception by the PHY. The CDL Transceiver consists of nine major functional blocks as shown in Figure 1. The Transmit section includes the following: the Delay Line, the Delay Line Calibrator, the Media Format Logic, and the Current Output Driver circuitry with its bias circuitry. The Delay Line accepts the NRZI encoded data from the PMRD g pins and provides a short ‘‘memory’’ of the bit that preceded the bit currently being transmitted. The Delay Line Calibrator allows the use of an external resistor which governs the time calibration of the delay line. The Delay Line outputs the data via taps which are tied to the Media Format Logic. The encoding logic is dependent on the state of the Media Select pin. The encoded data is routed to the Current Output Driver, through the TXO g output pins and transformer coupled to the media. The Receive section consists of the following: a differential input amplifier, Signal Detect circuitry, a Loopback Multiplexer, and differential 100K output drivers for data and Signal Detect. The Receive signal is input to the RXI g pins from the receive isolation transformer. The input signal is sensed by the Signal Detect circuit. The input signal also drives a differential input amplifier whose output is coupled to the Loopback Mux logic. The ‘sel’ input which is driven by LBEN controls which data stream, RXI g or Loopback data, 1.1 SDDI OPERATION The CDL allows full compatibility with the current SDDI specification. By allowing the MSEL pin to float, which forces the pin to VCC/2 internally, the SDDI mode of operation is selected. The appropriate transmit voltage amplitude must also be set by selecting a value of 2.6 kX for the TXREF resistor. Finally, it is important to note that the CDL must be used in conjunction with the Pulse Engineering 8.3 magnetics module in order to conform to the current SDDI specification. No special terminations are required in connecting the Pulse Engineering 8.3 module to the CDL. (Refer to the typical SDDI schematic, Figure 9. ) 2.0 Pinout Summary Signal Pin No. Description Type VCC 13, 26 VCC Supply GND 14, 22 GND Supply RXVCC 4, 27 Receive VCC Supply RXGND 3, 28 Receive GND Supply TXVCC 5, 11 Transmit VCC Supply TXGND 7, 10 Transmit GND Supply Supply EXTVCC 23 External VCC RXI g 2, 1 Receive Data Inputs Current In PMID g 25, 24 Physical Media Indicate Data ECL Out PMRD g 15, 16 TXO g SD g Physical Media Request Data ECL In 9, 8 Transmit Data Outputs Current Out 20, 21 Signal Detect Outputs ECL Out TXREF 6 Transmit Amplitude Reference Current Out DELREF 12 Delay Line Calibration Reference Current Out LBEN 19 Loopback Enable CMOS In MSEL 17 Media Select 3-Level Select CDET 18 Cable Detect Bar CMOS Schmitt Trigger In 2 3.0 Pin Definitions VCC (13,26): Positive power supply for the 100K ECL compatible circuitry. The Transceiver operates from a single a 5 VDC power supply. TXO g (9,8): Differential current driver outputs precompensated for twisted pair cable. SD g (20,21): Differential 100K ECL compatible Signal Detect outputs indicating that a valid signal is present at the RXI g inputs. DELREF (12): A resistor is connected between this pin and GND. The value of this resistor controls the current into the delay line calibrator which, in turn controls the delay time of the delay line. TXREF (6): A resistor is connected between this pin and TXGND. The value of this resistor controls the signal amplitude of the TXO g data which drives the twisted pair. LBEN (19): TTL compatible CMOS Loopback Enable input pin selects the internal loopback path which effectively routes the PMRD g data to the PMID g differential outputs. MSEL (17): The Media Select input controls the compensation and output current required to drive to 100 meters of either STP or DTP media. This is a tri-Ievel control pin. When forced to a low voltage, STP compensation is selected. Forcing a high voltage level will select the DTP compensation mode. Forcing a median voltage allows the device to operate in the transparent mode by deasserting pre-emphasis. CDET (18): The Cable Detect input is provided to support the option of external Cable Detection circuitry. With CDET low, the CDL transceiver functions normally. When CDET is high, the signal detect output is forced low which inhibits data reception by the PHY. The exception is in the case of Loop Back, where Signal Detect is forced high regardless. GND (14,22): Return path for the 100K ECL compatible circuitry power supply. RXVCC (4,27): Positive power supply for the small signal receive circuitry. This power supply is intentionally separated from others to eliminate receive errors due to coupled supply noise. RXGND (3,28): Return path for the receive power supply circuitry. This Power supply return is intentionally separated from others to eliminate receive errors due to coupled supply noise. TXVCC (5,11): Positive power supply required by the analog portion of the transmit circuitry. This power supply is intentionally separated from the others to prevent supply noise from coupling to the transmit outputs. TXGND (7,10): Return path for the analog transmit power supply circuitry. This supply return is intentionally separated from others to prevent supply noise from being coupled to the transmit outputs. EXTVCC (23): Positive power supply for receiver output circuitry. RXI g (2,1): Balanced differential line receiver inputs. Signals meeting the input threshold for a given media type are output through PMID g as differential ECL. PMID g (25,24): 100K ECL compatible differential outputs used as the source of the receive data for the DP83231 Clock Recover Device (CRDTM ). PMRD g (15,16): Differential 100K compatible 4B5B NRZI transmit data inputs originating from the DP83251/55 Physical Layer Device (PLAYER TM ). 28-Pin PLCC TL/F/11724 – 3 Order Number DP83220V See NS Package Number V28A FIGURE 2. Pin Configuration TL/F/11724 – 4 FIGURE 3. System Connection Diagram 3 4.0 Electrical Characteristics ABSOLUTE MAXIMUM RATINGS Max Units VCC Symbol Logic Power Parameter Referenced to GND b 0.5 6.0 V RXVCC Received Power Referenced to RXGND b 0.5 6.0 V TXVCC Transmit Power Referenced to TXGND b 0.5 6.0 V Referenced to GND b 0.5 EXTVCC ECL Output Power IECL DC Output Current (High) Conditions Min Typ ESD Tstorage 6.0 V b 50 mA a 150 §C TBD Storage Temperature b 65 4.1 RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage TA Operating Temperature PD Power Dissipation Conditions Min Typ Max Units 4.5 5.0 5.5 V 0 25 70 §C 600 mW 4.2 DC ELECTRICAL CHARACTERISTICS TA e 25§ C Symbol Parameter Conditions Min Typ Max Units 0.8 V 1.5 V 1.5 V VCC b 1165 VCC b 870 mV VCC b 1830 VCC b 1475 mV VCC b 1035 VCC b 870 mV VCC b 1605 mV VIHt TTL High Level Input 2.0 VILt TTL Low Level Input V VIHschmitt Schmitt High Level Input VILschmitt Schmitt Low Level Input VIHmsel MSEL High Level Input VILmsel MSEL Low Level Input VIMmsel MSEL Middle Level Input VIHe ECL High Level Input VILe ECL Low Level Input VOHe ECL High Level Output Refer to Figure 4 VOLe ECL Low Level Output Refer to Figure 4 VCC b 1830 3.7 V 3.7 V VCC/2 V Refer to Figure 4 90 mA ICCT Total Supply Current Refer to Figure 4 145 mA ITXO1 Transmit Current 1 Transmit Current / 100X ZO 20 mA ITXO2 Transmit Current 2 Transmit Current / 150X ZO 15 mA SDTHon Sig Det Turn-On Threshold Refer to Figure 5, Note 1 SDTHoff Sig Det Turn-Off Threshold Refer to Figure 5, Note 1 15 mV Max Units ICC1 60 mV 4.3 AC ELECTRICAL CHARACTERISTICS TA e 25§ C Symbol Parameter Conditions Min Typ tTXr/f TX Driver Rise and Fall Into 25X in Parallel with 50 pF 1.6 ns tTXr/f TX Driver Rise and Fall Into 37.5X in Parallel with 50 pF 2.5 ns tTXpd TX Propagation Delay From PMRD g to TXO g 6 ns tRXpd RX Propagation Delay From RXI g to PMID g 10 ns TTXskew TX Driver Skew 0 ps Note 1: Subject to change. 4 4.0 Electrical Characteristics (Continued) TL/F/11724 – 5 FIGURE 4. ICC Diagram TL/F/11724 – 6 FIGURE 5. Signal Detect Threshold 5 4.0 Electrical Characteristics (Continued) TL/F/11724 – 7 FIGURE 6. Transmit Timing TL/F/11724 – 8 FIGURE 7. Receive Timing 6 4.0 Electrical Characteristics (Continued) 4.3 TRANSMIT DATA AND CURRENT DRIVER OUTPUT TXDn TXDnb1 ITXO a ITXOb 0 0 (I1) Imax (I2) Imax 0 1 (I1 a I2) Imax 0 1 0 0 (I1 a I2) Imax 1 1 (I2) Imax (I1) Imax TL/F/11724 – 9 FIGURE 8. Typical Pre-Emphasized Current Waveform, ITXO a TABLE I. Media Select TABLE II. Data Paths and Signal Detect Mode MSEL LBEN CDET STP k 1.5V 0 1 RXI g 0 DTP l 3.7V 0 0 RXI g 1 1 1 PMRD g 1 1 0 PMRD g 1 SDDI Float Data @ PMID g SD a Note: This table assumes that minimum signal’s levels required by Signal Detect have been met. 7 4.0 Electrical Characteristics (Continued) TL/F/11724 – 10 Refer to the Pulse Engineering datasheet for detailed information on the 8.3 SDDI magnetics module. FIGURE 9. Typical Schematic for SDDI Application 8 9 DP83220 CDL Twisted Pair FDDI Transceiver Device Physical Dimensions inches (millimeters) 28-Pin Plastic Leaded Chip Carrier (V) Order Number DP83220V NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. 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