FILTRONIC LPS200

LPS200
HIGH PERFORMANCE LOW NOISE PHEMT
•
FEATURES
♦ 1.0 dB Noise Figure at 18 GHz
♦ 10 dB Associated Gain at 18 GHz
♦ Low DC Power Consumption
GATE
BOND
PAD (2X)
DRAIN
BOND
PAD (2X)
SOURCE
BOND
PAD (2x)
DIE SIZE: 12.6X10.2mils (320x260 µm)
DIE THICKNESS: 3.9 mils (100 µm)
BONDING PADS: 3.3X2.6 mils (85x65 µm)
•
DESCRIPTION AND APPLICATIONS
The LPS200 is an Aluminum Gallium Arsenide / Indium Gallium Arsenide (AlGaAs/InGaAs)
Pseudomorphic High Electron Mobility Transistor (PHEMT), utilizing an Electron-Beam directwrite 0.25 µm by 200 µm Schottky barrier gate. The recessed “mushroom” gate structure minimizes
parasitic gate-source and gate resistances. The epitaxial structure and processing have been
optimized for high dynamic range. The LPS200 also features Si3 N4 passivation and is available in
various packages.
Typical applications are as low noise devices for both narrowband and broadband amplifiers.
•
ELECTRICAL SPECIFICATIONS @ TAmbient = 25°C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Saturated Drain-Source Current
IDSS
VDS = 2 V; VGS = 0 V
15
25
50
mA
Noise Figure
NF
VDS = 2 V; IDS = 25% IDSS
0.7
1.3
dB
Associated Gain at minimum NF
GA
VDS = 2 V; IDS = 25% IDSS
Maximum Drain-Source Current
IMAX
VDS = 2 V; VGS = 1 V
Transconductance
GM
VDS = 2 V; VGS = 0 V
Gate-Source Leakage Current
IGSO
VGS = -5 V
Pinch-Off Voltage
VP
VDS = 2 V; IDS = 1 mA
Thermal Resistivity
ΘJC
9
50
-0.25
10
dB
125
mA
70
mS
1
10
µA
-0.8
-1.5
V
285
°C/W
frequency=18 GHz
Phone: (408) 988-1845
Fax: (408) 970-9950
http:// www.filss.com
Revised: 1/23/01
Email: [email protected]
LPS200
HIGH PERFORMANCE LOW NOISE PHEMT
•
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Test Conditions
Drain-Source Voltage
VDS
Gate-Source Voltage
Min
Max
Units
TAmbient = 22 ± 3 °C
4
V
VGS
TAmbient = 22 ± 3 °C
-2
V
Drain-Source Current
IDS
TAmbient = 22 ± 3 °C
IDSS
mA
Gate Current
IG
TAmbient = 22 ± 3 °C
10
mA
RF Input Power
PIN
TAmbient = 22 ± 3 °C
100
mW
Channel Operating Temperature
TCH
TAmbient = 22 ± 3 °C
175
ºC
Storage Temperature
TSTG
—
175
ºC
Total Power Dissipation
PTOT
TAmbient = 22 ± 3 °C
460
mW
-65
Notes:
• Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device.
• Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where
PDC: DC Bias Power
PIN: RF Input Power
POUT: RF Output Power
• Absolute Maximum Power Dissipation to be de-rated as follows above 25°C:
PTOT= 460mW – (37mW/°C) x THS
where THS = heatsink or ambient temperature.
•
HANDLING PRECAUTIONS
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic
Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and
testing. These devices should be treated as Class 1A (0-500 V). Further information on ESD control
measures can be found in MIL-STD-1686 and MIL-HDBK-263.
•
ASSEMBLY INSTRUCTIONS
The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage
temperature should be 280-290°C; maximum time at temperature is one minute. The recommended
wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm)
gold wire. Stage temperature should be 250-260°C.
•
APPLICATIONS NOTES & DESIGN DATA
Applications Notes are available from your local Filtronic Sales Representative or directly from the
factory. Complete design data, including S-parameters, noise data, and large-signal models are
available on the Filtronic web site.
All information and specifications are subject to change without notice.
Phone: (408) 988-1845
Fax: (408) 970-9950
http:// www.filss.com
Revised: 1/23/01
Email: [email protected]