TI BQ29312PWR

RGE
PW
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
FEATURES
APPLICATIONS
D Notebook PCs
D Medical and Test Equipment
D Portable Instrumentation
D 2-, 3-, or 4-Cell Series Protection Control
D Can Directly Interface With the bq2084 Gas
Gauges
D Provides Individual Cell Voltages and Battery
Voltage to Battery Management Host
D Integrated Cell Balancing Drive
D I2C Compatible User Interface Allows Access
to Battery Information
D Programmable Threshold and Delay for Over
Load and Short Circuit During Charge and
Discharge
D System Alert Interrupt Output
D Host Control Can Initiate Sleep Power Mode
DESCRIPTION
The bq29312 is a 2-, 3-, or 4-cell lithium-ion battery pack
protection analog front end (AFE) IC that incorporates a
3.3-V, 25-mA low-dropout regulator (LDO). The bq29312
also integrates an I2C compatible interface to extract
battery parameters such as cell voltages and control
output status. Other parameters such as current protection
thresholds and delays can be programmed into the
bq29312 to increase the flexibility of the battery
management system.
The bq29312 provides safety protection for overcharge,
overload, short-circuit, overvoltage, and undervoltage
conditions in conjunction with the battery management
host. In overload and short-circuit conditions, the bq29312
turns the FET drive off autonomously dependant on the
internal configuration setting.
and Ship Mode
D Integrated 3.3-V, 25-mA LDO
D Supply Voltage Range From 4.5 V to 25 V
D Low Supply Current of 60-µA Typical
SYSTEM PARTITIONING DIAGRAM
Discharge / Charge /
Pre−Charge FETs
Fuse
Pack +
bq29312
PF Input
PCH FET Drive
Power Management
LDO, TOUT and Power mode control
Temperature Measurement
<1% Error
768 Bytes of
User Flash
SMBus
TINT
32kHz Clock
Generator
Supply Voltage
T1
Pre−Charge
FET Drive
Cell Balancing
Drive
LDO, Therm Output Drive & UVLO
System Watchdog
Delay Counters
System Interface
RAM Registers
32kHz
Cell Balancing Algorithm and Control
SBS v1.1 Data
System Interface
bq29312 RAM/Comms Validation
1st Level OC
Protection
1st Level OV and
UV Protection
Pack Under Voltage
Power Mode
Control
Cell and Pack
Voltage
Measurement
I2 C
XAlert
Sleep
Power Mode Control
2nd Level Over Voltage Protection
bq2084
Pre-charge Control Fail-Safe Protection
2−Tier Over Current Protection
Capacity Prediction <1% Error
Voltage Level Translator
Pack −
Sense Resistor
(10 − 30 mΩ)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
! " #$%! " &$'#! (!%) ($#!"
# ! "&%##!" &% !*% !%" %+" "!$%!" "!(( ,!-)
($#! &#%"". (%" ! %#%""'- #'$(% !%"!. '' &%!%")
Copyright  2004, Texas Instruments Incorporated
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
The communications inter-face allows the host to observe and control the current status of the bq29312. It enables cell
balancing, enters different power modes, sets overload levels, sets the over- load blanking delay time, sets short-circuit
threshold levels for charge and discharge, and sets the short-circuit blanking delay time.
Cell balancing of each cell is performed via a cell bypass path, which is enabled via the internal control register accessible
via the I2C compatible interface. The maximum bypass current is set via an external series resistor and internal FET on
resistance (typical 400 Ω).
ORDERING INFORMATION
PACKAGED
TA
−25°C to 85°C
TSSOP (PW)
QFN (RGE)
bq29312PW
bq29312PWR
bq29312RGE
bq29312RGER
PACKAGE DISSIPATION RATINGS
PACKAGE
POWER RATING
TA ≤ 25°C
DERATING FACTOR
ABOVE TA ≤ 25°C
PW
874 mW
6.99 W/°C
POWER RATING
TA ≤ 70°C
559 mW
TA = 85°C
454 mW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
bq29312
Supply voltage range
Input voltage range
PACK, BAT
−0.3 V to 34 V
VC1, VC2, VC3, VC4
−0.3 V to 34 V
SR1, SR2
−1.0 V to 1.0 V
VC5
−1.0 V to 4.0 V
VC1 to VC2, VC2 to VC3, VC3 to VC4, VC4 to VC5
WDI, SLEEP, SCLK, SDATA
ZVCHG
Output voltage range
−0.3 to 8.5 V
−0.3 to 8.5 V
−0.3 V to 34 V
DSG, CHG
−0.3 V to BAT
OD
−0.3 V to 34 V
PMS
TOUT, SCLK, SDATA, CELL, XALERT
Current for cell balancing
Continuous total power dissipation
Storage temperature range, Tstg
Lead temperature (soldering, 10 sec)
−0.3 V to PACK−0.2 V
−0.3 to 7 V
10 mA
See Dissipation Rating Table
−65°C to 150°C
300°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground of this device except VCn−VC(n+1), where n=1, 2, 3, 4 cell voltage.
2
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
RECOMMENDED OPERATING CONDITIONS
MIN
4.5(1)
Supply Voltage (BAT or PACK)
VI(STARTUP)
Start-up voltage (PACK)
VIH
VIL
VIH
VIL
VO
IO
II
Input voltage range
Logic level input voltage
IOL
SR1, SR2
−0.5
0.5
VC5
−0.5
3.0
VCn – VC(n+1), (n=1, 2, 3, 4 )
0
5.0
PMS
0
PACK
SLEEP
0
REG
0.8×REG
REG
SCLK, SDATA, WDI
PMS pull up/pull down resistance
RPMS
Output voltage
OD
Output current
Input frequency
WDI high time
UNIT
V
V
BAT
PMS
Extend CELL output filter
25
0
PMS logic level
Input current,
External 3.3 V REG capacitor
MAX
5.0
VC1, VC2, VC3, VC4
VI
NOM
0
0.2×REG
VPACK −0.2
0
VPACK
0.2
100
1000
V
V
V
kΩ
25
V
XALERT, SDATA
200
µA
CELL
±10
µA
1.0
µA
SLEEP
C(REG)
R(CELL)
−0.5
µF
4.7
C(CELL)
OD
100
Ω
100
nF
1
WDI
32.768
2
mA
kHz
28
µs
TA
Operating temperature
−25
85
°C
(1) V(PACK) supply voltage must rise above start-up voltage on power up to enable the internal regulator which drives REG and TOUT as required.
Once V(PACK) is above the start-up voltage, it can fall down to the minimum supply voltage and still meet the specifications of the bq29312.
3
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
TA = 25°C, C(REG) = 4.7 µF, BAT = 14 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
60
90
UNIT
SUPPLY CURRENT
No load at REG, TOUT, XALERT, SCLK,
and SDATA. ZVCHG = off ,VMEN = on,
WDI no clock, Select VC5 = VC4 = 0 V
µA
A
ICC1
Supply current 1
ICC2
Supply current 2
(Depends of VM
topology
selected)
No load at REG, TOUT, XALERT, SCLK,
and SDATA. ZVCHG = off, VMEN = off,
WDI no clock
TA = −25°C to 85°C
25
50
µA
I(SLEEP)
Sleep current
No load at REG, TOUT, XALERT, SCLK,
and SDATA.
CHG, DSG and ZVCHG = off, REG = on,
VMEN = off, WDI no clock,
SLEEP = REG or OPEN
TA = −25°C to 85°C
20
40
µA
I(SHIP)
Ship current
REG, CHG, DSG and ZVCHG = off,
REG = off, VMEN = off, WDI no clock,
VPACK= 0 V
TA = −25°C to 85°C
0.1
1.0
µA
TA = −25°C to 85°C
100
3.3 V LDO
V(REG)
Regulator output
voltage
∆V(EGTEMP)
Regulator output
change with
temperature
∆V(REGLINE)
Line regulation
∆V(REGLOAD) Load regulation
IMAX
Current limit
8.0 V< BAT or PACK ≤ 25 V, IOUT ≤ 25 mA
−4%
3.3
2%
6.5 V< BAT or PACK ≤ 8 V, IOUT ≤ 25 mA
−9%
3.3
2%
−9%
3.3
2%
V
−2%
3.3
2%
V
3
10
mV
7
15
40
100
5.4 V ≤ BAT or PACK ≤ 6.5 V,
IO ≤ 16 mA
4.5 V ≤ BAT or PACK ≤ 25 V,
IO ≤ 2 mA
5.4 V≤ BAT ≤ 25 V, IO = 2 mA,
TA =− 25°C to 85°C
V
±0.2%
TA =− 25°C to 85°C
5.4 V ≤ BAT or PACK ≤ 25 V, IO = 2 mA
BAT = 14 V, 0.2 mA ≤ IO ≤ 2 mA
BAT = 14 V, 0.2 mA ≤ IO ≤ 25 mA
BAT = 14 V, REG = 3.0 V
25
100
BAT = 14 V, REG = 0 V
12
50
mV
mA
CELL VOLTAGE MONITOR
CELL output
V(Cn) – V(Cn + 1) = 0 V, 8.0 V ≤ BAT or PACK ≤ 25 V
V(Cn) – V(Cn + 1) = 4.5 V, 8.0 V ≤ BAT or PACK ≤ 25 V
Mode(1), 8.0 V ≤ BAT or PACK ≤ 25 V
−1%
0.975
1%
V
CELL output
Mode(2)
−5%
PACK
/25
5%
V
K = {CELL output (VC5 = 0.0 V, VC4 = 4.5 V)
−CELL output (VC5 = VC4 = 0.0 V)/ 4.5
0.147
0.150
0.153
K = {CELL output (VC2 = 13.5 V, VC1 = 18.0 V)
−CELL output (VC2 = VC1 = 13.5 V)/ 4.5
0.147
0.150
0.153
V(CELL OUT)
CELL output
REF
PACK
K
CELL scale factor
VICR
CELL output
offset error
CELL output (VC2 = 17.0 V, VC1 = 17.0 V)
CELL output (VC2 = VC1 = 0.0 V)
R(BAL)
Cell balance
internal
resistance
rds(ON) for internal FET switch at VDS = 2.0 V
(1) Register Address =0x04, b2(CAL0) = b3(CAL1) = 1, Register Address = 0x03,b0(VMEN) = 1
(2) Register Address = 0x03, b1(PACKOUT) = 1, b0( VMEN) = 1
4
0.975
V
0.3
−1
200
400
mV
800
Ω
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS (Continued)
TA = 25°C, C(REG) = 4.7 µF, BAT = 14 V (unless otherwise noted)
PARAMETER
TEST CONDITION
OVER LOAD (OL) AND SHORT CIRCUIT (SC) DETECTION
VOL
OL detection threshold range, typical(1)
∆VOL
VHYS(OL)
MIN
−50
OL detection threshold program step
7
SC detection threshold range, typical(2)
∆V(SC)
SC detection threshold program step
VHYS(SC)
SC detection threshold hysteresis
Charge
UNIT
−205
mV
Discharge
mV
13
475
−100
−475
VOL = 50 mV (min)
VOL = 100 mV
40
50
60
40
50
60
90
100
110
VOL = 205 mV (max)
VSC = 100 mV (min)
184
205
226
80
100
120
VSC = 200 mV
VSC = 475 mV (max)
180
200
220
426
475
523
MIN
TYP
MAX
V(FETOND)= V(BAT) –V(DSG)
BAT = 20 V
VGS connect 1 MΩ
12
15
18
V(FETONC)=V(PACK)–V(CHG)
PACK = 20 V
VGS connect 1 MΩ
12
15
18
PACK = 4.5 V
3.3
3.5
3.7
Charge and
Discharge
SC detection threshold accuracy(2)
mV
mV
−25
Charge and Discharge
Discharge
mV
25
Discharge
OL detection threshold accuracy(1)
10
100
Charge
V(SC_acr)
MAX
5
OL detection threshold hysteresis
V(SC)
V(OL_acr)
NOM
mV
mV
mV
(1) See OL register for setting detection threshold
(2) See SC register for setting detection threshold
PARAMETER
TEST CONDITION
UNIT
FET DRIVE CIRCUIT
V(FETON)
V(ZCHG)
Output voltage, charge and discharge
FETs on
ZVCHG clamp voltage
V
V
V(FETOFF)
Output voltage, charge and discharge
FETs off
V(FETOFF)= V(PACK) –V(DSG) PACK = 16 V
V(FETOFF)=V(BAT) – V(CHG) BAT = 16 V
200
Rise time
CL = 4700 pF
VDSG :10%−90%
VCHG :10%−90%
40
tr
40
200
tf
Fall time
CL = 4700 pF
VDSG :90%−10%
VCHG :90%−10%
40
200
40
200
NOM
MAX
UNIT
50
100
Ω
MIN
NOM
MAX
UNIT
60
100
200
6
10
20
PARAMETER
TEST CONDITION
0.2
0.2
MIN
V
µss
µs
THERMISTOR DRIVE
rDS(on)
TOUT pass-element series resistance
IO = −1 mA at TOUT pin, rds(ON) = (VREG – VO
(TOUT))/1 mA, TA = −25°C to 85°C
PARAMETER
TEST CONDITION
LOGIC
XALERT
R(PUP)
Internal pullup resistance
VOL
Logic level output voltage
SDATA, SCLK,
XALERT, IO = 200 µA,
TA = −25°C to 85°C
TA = −25°C to 85°C
TA = −25°C to 85°C
TA = −25°C to 85°C
0.2
SDATA, IO = 50 µA,
OD IO=1 mA,
TA = −25°C to 85°C
0.6
0.4
kΩ
V
5
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
AC ELECTRICAL CHARACTERISTICS
TA = 25°C, C(REG) = 4.7 µF, BAT = 14 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
NOM
MAX
UNIT
250
700
2000
ms
t(WDTINT) WDT start-up detect time
t(WDWT) WDT detect time
µs
100
AC TIMING SPECIFICATIONS (I2C COMPATIBLE SERIAL INTERFACE)
PARAMETER
MIN
MAX
UNIT
1000
ns
tr
tf
SCLK SDATA rise time
tw(H)
tw(L)
SCLK pulse width high
4.0
µs
SCLK pulse width low
4.7
µs
tsu(STA)
th(STA)
Setup time for START condition
4.7
µs
START condition hold time after which first clock pulse is generated
4.0
µs
tsu(DAT)
th(DAT)
Data setup time
250
ns
0
µs
tsu(STOP)
tsu(BUF)
Setup time for STOP condition
4.0
µs
Time the bus must be free before new transmission can start
4.7
tV
Clock low to data out valid
th(CH)
fSCL
Data out hold time after clock low
0
Clock frequency
0
SCLK SDAT fall time
300
Data hold time
µs
900
tsu(STA)
tw(H)
tf
tw(L)
SDATA
Start
Condition
SDA
Input
100
tr
th(DAT)
th(STA)
1
SCLK
tf
Stop
Condition
SDA
Change
2
th(ch)
tsu(DAT)
3
7
8
9
MSB
SDATA
ACK
Start Condition
tv
tsu(STOP)
SCLK
SDATA
1
MSB
2
3
7
8
9
ACK
Stop Condition
6
ns
ns
SCLK
tr
ns
tsu(BUF)
kHz
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
PIN ASSIGNMENTS
PW PACKAGE
(TOP VIEW)
OD
PMS
PACK
ZVCHG
CHG
SLEEP
REG
TOUT
XALERT
GND
SDATA
SCLK
VC1
DSG
BAT
OD
PMS
PACK
24
23
22
21
20
19
18
17
16
15
14
13
ZVCHG
CHG
SLEEP
REG
TOUT
XALERT
VC2
VC3
VC4
VC5
SR1
SR2
WDI
CELL
GND
SCLK
SDATA
GND
1
2
3
4
5
6
7
8
9
10
11
12
BAT
DSG
VC1
VC2
VC3
VC4
VC5
SR1
SR2
WDI
CELL
GND
RGE PACKAGE
(TOP VIEW)
Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
QFN
PW
1
VC2
BAT
Diode protected BAT+ terminal and primary power source.
2
VC3
DSG
Push-pull output discharge FET gate drive
3
VC4
VC1
Sense voltage input terminal for most positive cell and balance current input for most positive cell.
4
VC5
VC2
Sense voltage input terminal for second most positive cell, balance current input for second most positive cell
and return balance current for most positive cell.
5
SR1
VC3
Sense voltage input terminal for third most positive cell, balance current input for third most positive cell and
return balance current for second most positive cell.
6
SR2
VC4
Sense voltage input terminal for least positive cell, balance current input for least positive cell and return balance
current for third most positive cell.
7
WDI
VC5
Sense voltage input terminal for most negative cell, return balance current for least positive cell.
8
CELL
SR1
Current sense positive terminal when charging relative to SR2
Current sense negative terminal when discharging relative to SR2
9
GND
SR2
Current sense terminal
10
SCLK
WDI
Digital input that provides the timing clock for the OC and SC delays and also acts as the watchdog clock.
11
SDATA
CELL
Output of scaled value of the measured cell voltage.
12
GND
GND
Analog ground pin and negative pack terminal
13
XALERT
SCLK
Open-drain bidirectional serial interface clock with internal 10 kΩ pull-up to V(REG).
14
TOUT
SDATA
Open-drain bidirectional serial interface data with internal 10 kΩ pull-up to V(REG).
15
REG
GND
16
SLEEP
XALERT
17
CHG
TOUT
Provides thermistor bias current
18
ZVCHG
REG
Integrated 3.3-V regulator output
19
PACK
SLEEP
20
PMS
CHG
21
OD
ZVCHG
22
BAT
PACK
PACK positive terminal and alternative power source
23
DSG
PMS
0-V charge configuration select pin, CHG terminal ON/OFF is determined by this pin.
24
VC1
OD
Connect to GND
Open-drain output used to indicate status register changes. With internal 100 kΩ pull-up to V(REG)
This pin is pulled up to V(REG) internally, open or H level makes Sleep mode
Push-pull output charge FET gate drive
The ZVCHG FET drive is connected here
NCH FET open drain output
7
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
FUNCTIONAL BLOCK DIAGRAM
PACK−
GG VDD
PACK+
R(ZVCHG)
C (REG)
PMS
ZVCHG
REG
0.2 mA
Current Source
CHG
DSG
BAT
ZVCHG_ON
Gate Driver CHG_ON
DSG_ON
+
_
−
PACK
FET
Logic
REG
3.3V LDO
POR
SLEEP
CONTROL
32kHz INPUT
FROM GG
SLEEP
Watchdog
Timer
WDI
GG INTERFACE
SDATA
GG INTERFACE
SCLK
SDATA
SCLK
REG
SERIAL INTERFACE
Registers
Status
Function Ctl
CELL 2
VC4
CELL 1
VC5
Drive
Control
TOUT
C THERM
THERMISTOR
R CELL
VCELL
OCDV
OCDT
Over-Load
Comparator
SCC
Open
Drain
Output
C CELL
GG ANALOG
INPUT
OVER_CURRENT
SR1
DELAY
SHORT_CIRCUIT
Short Circuit
Comparator
R SNS
SR2
GND
8
GG TS
INPUT
R THERM
Cell Voltage
Translation
CELL_SEL
SCD
OD
CELL 3
VC3
State Ctl
200 kW
OPEN DRAIN
OUTPUT
Power
Mode
Circuit
CELL 4
VC2
Output Ctl
ALERT TO GG
XALERT
SHIP_ON
SLEEP_ON
CELL1..4
200 kW
Cell
Selection
Switches
VC1
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
STATE DIAGRAM
No Power
SHIP MODE EXIT BY POWER
SUPPLY TO PACK
POWER SUPPLY TO PACK
INITIALIZE
FETS: OFF(*2)
REG: start Working
I2C: OFF
CURRENT FAULT : OFF
CELL MONITOR : OFF
WATCHDOG : OFF
THERMISTOR PWER CTRL : OFF
REG >2.4 V
IFAULT
RESET CURRENT LATCH
HOST FAULT MODE
FETS: OFF
REG: ON
I2C: ON
CURRENT FAULT : OFF
CELL MONITOR : OFF
WATCHDOG : ON
THERMISTOR PWER CTRL : OFF
REG < 2.3 V
NORMAL MODE
FETS: ON *2
REG: ON
I2C: ON
CURRENT FAULT : ON
CELL MONITOR : ON
WATCHDOG : ON
THERMISTOR PWER CTRL : ON
HOST CLOCK STOP
RESET WDTF LATCH
STATE CTL REGISTER b1 = 1
AND NO SUPPLY POWER TO PACK
SLEEP MODE EXIT BY
STATE CTL REGISTER b1 = 0
AND SLEEP PIN = GND
*1
STATE CTL REGISTER b0 = 1
or SLEEP PIN = REG or OPEN
*1
CURRENT DETECT MODE
SLEEP MODE
SHIP MODE
FETS: OFF
REG: ON
I2C: ON
CURRENT FAULT : ON
CELL MONITOR : ON
WATCHDOG : ON
THERMISTOR PWER CTRL : ON
FETS: OFF
REG: ON
I2C: ON
CURRENT FAULT : OFF
CELL MONITOR : OFF
WATCHDOG : OFF
THERMISTOR PWER CTRL : OFF
FETS: OFF
REG: OFF
I2C: OFF
CURRENT FAULT : OFF
CELL MONITOR : OFF
WATCHDOG : OFF
THERMISTOR PWER CTRL : OFF
SHIP MODE SET BY
STATE CTL REGISTER
b1 = 1 AND NO SUPPLY
POWER TO PACK
SHIP MODE SET BY STATE CTL REGISTER
b1 = 1 AND NO SUPPLY POWER TO PACK
Interrupt Request When
Enrering These States
*1: Interrupt Request is Granted When Only External Sleep Pin Changes
*2: When PMS connect to Pack, Default State of CHG FET is ON.
9
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
FUNCTIONAL DESCRIPTION
Low-Dropout Regulator (REG)
The inputs for this regulator can be derived from the battery cell stack (BAT) or the pack positive terminal (PACK). The output
is typically 3.3 V with the minimum output capacitance for stable operation is 4.7 µF and is also internally current limited.
During normal operation, the regulator limits output current to typically 50 mA.
Initialization
The bq29312 internal control circuit is powered by the REG voltage, which it also monitors. When the voltage at REG falls
below 2.3 V, the internal circuit turns off the FETs and disables all controllable functions, including the REG and TOUT
outputs. REG does not start up unless a voltage above V(STARTUP) is supplied to the PACK terminal. After the regulator
has started, based on PACK voltage, it keeps operating through the BAT input, even if the PACK voltage is removed. If
the BAT input is below the minimum operating range, then the bq29312 does not operate if the supply to the PACK input
is removed. After start up, when the REG voltage is above 2.4 V, the bq29312 is in Normal mode.
The initial state of the CHG output depends on the PMS input. If PMS = PACK then CHG = ON however, if PMS= GND
then CHG = OFF.
Overload Detection
The overload detection is used to detect abnormal currents in the discharge direction. This feature is used to protect the
pass FETs, cells and any other inline components from excessive current conditions. The detection circuit also incorporates
a blanking delay before driving the control for the pass FETs to the OFF state. The overload sense voltage is set in the OLV
register, and delay time is set in the OLT register. The overload threshold can be programmed from 50 mV to 205 mV in
5-mV steps with the default being 50 mV and hysteresis of 10 mV.
Short-Circuit Detection
The short current circuit detection is used to detect abnormal current in either the charge or discharge direction. This safety
feature is used to protect the pass FETs, cells, and any other inline components from excessive current conditions. The
detection circuit also incorporates a blanking delay before driving the control for the pass FETs to the OFF state. The shortcircuit thresholds and delay time are set in the SCC and SCD registers respectively where SCC is for charging and SCD
is for discharge. The short-circuit threshold can be programmed from 100 mV to 475 mV in 25-mV steps with the default
being 100 mV and hysteresis of 50 mV.
Overload and Short-Circuit Delay
The overload delay (default =1 ms) allows the system to momentarily accept a high current condition without disconnecting
the supply to the load. The delay time can be increased via the OLT register, which can be programmed for a range of 1
ms to 31 ms with steps of 2 ms.
The short-circuit delay (default = 0 µs) is programmable in the SCC and SCD registers. This register can be programmed
from 0 µs to 915 µs with steps of 61 µs.
Overload and Short-Circuit Response
When an overload or short-circuit fault is detected, the FETs are turned off. The STATUS (b0…b2) register reports the
details of short-circuit (charge), short-circuit (discharge), and overload. The respective STATUS (b0…b2) bits are set to
1 and the XALERT output is triggered. This condition is latched until the CONTROL (b0) is set and then reset. If a FET is
turned on via resetting CONTROL (b0) and the error condition is still present on the system, then the device reenters the
protection response state.
Cell Voltage
The cell voltage is translated to allow a system host to measure individual series elements of the battery. The series element
voltage is translated to a GND-based voltage equal to 0.15 ±0.002 of the series element voltage. This provides a range
from 0 V to 4.5 V. The translation output is inversely proportional to the input using the following equation.
Where, V(CELL OUT) = −K × V(CELL IN) + 0.975 (V)
Programming CELL_SEL (b1, b0) selects the individual series element. The CELL_SEL (b3, b2) selects the voltage
monitor mode, cell monitor, offset etc.
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Calibration of Cell Voltage Monitor Amplifier Gain
The cell voltage monitor amplifier has an offset and to increase accuracy this can be calibrated.
There are a couple of method by calibration circumstance.
The following procedure shows how to measure and calculate the offset and gain as one of example.
D Step 1
−
Set CAL1=1, CAL0=1, CELL1=0, CELL0=0, VMEN=1
−
VREF is trimmed to 0.975 V within ±1%, measuring VREF eliminates its error.
−
Measure internal reference voltage VREF from VCELL directly.
−
VREF=measured reference voltage
−
Set CAL1=0, CAL0=0, CELL1=0, CELL0=0, VMEN=1
−
The output voltage includes the offset and represented by:
VO(4−5) = VREF + (1 + K) × VOS (V)
Where K = CELL Scaling Factor
−
VOS = Offset voltage at input of the internal Op-Amp
−
Set CAL1=1, CAL0=0, CELL1=0, CELL0=0, VMEN=1
−
Measuring scaled REF voltage through VCELL amp.
−
The output voltage includes the scale factor error and offset and is represented by:
V(OUTR) = VREF + (1 + K) × VOS – K × VREF (V)
D Step 2
D Step 3
D Step 4
−
Calculate (VO(4−5) −V(OUTR)/VREF
−
The result will be the actual scaling factor, K(ACT) and is represented by:
−
K(ACT) = (VO(4−5) −V(OUTR))/VREF = (VREF + (1 + K) × VOS) − (VREF + (1 + K) × VOS – K × VREF)/
VREF= K × VREF/VREF = K
D Step 5
−
Calculate the actual offset value where:
VOS(ACT) = (VO(4−5) – VREF)/(1 + K(ACT))
D Step 6
−
Calibrated cell voltage is calculated by:
VCn – VC(n+1) = { VREF + (1 + K(ACT) ) × VOS(ACT) – V(CELLOUT)}/K(ACT) = {VO(4−5) – V(CELLOUT)}/K(ACT)
For improved measurement accuracy, VOS(ACT) for each cell voltage should be measured.
Set CAL1=0, CAL0=0, CELL1=0, CELL0=1, VMEN=1
Set CAL1=0, CAL0=0, CELL1=1, CELL0=0, VMEN=1
Set CAL1=0, CAL0=0, CELL1=1, CELL0=1, VMEN=1
Measuring VO(3−4) , VO(2−3), VO(1−2),
VC4 – VC5 = {VO(4−5) – V(CELLOUT)}/ K(ACT)
VC3 – VC4 = {VO(3−4) – V(CELLOUT)}/ K(ACT)
VC2 – VC3 = {VO(2−3) – V(CELLOUT)}/ K(ACT)
VC1 – VC2 = {VO(1−2) – V(CELLOUT)}/ K(ACT)
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Cell Balance Control
The cell balance control allows a small bypass path to be controlled for any one series element. The purpose of this bypass
path is to reduce the current into any one cell during charging to bring the series elements to the same voltage. Series
resistors placed between the input pins and the positive series element nodes control the bypass current value. Individual
series element selection is made using bits 4 through 7 of the CELL_SEL register.
Thermistor Drive Circuit (TOUT)
The TOUT pin can be enabled to drive a thermistor from REG. The typical thermistor resistance is 10 kΩ at 25°C. The
default-state is OFF to conserve power. The maximum output impedance is 100 Ω. TOUT is enabled in FUNCTION CTL
Register (bit 5).
Open Drain Drive Circuit (OD)
The open drain output has 1-mA current source drive with a maximum output voltage of 25 V. The OD output is enabled
or disabled by OUTPUT CTL Register (bit 4) and has a default state of OFF.
XALERT (XALERT)
XALERT is driven low when an OL or SC current fault is detected, if the SLEEP pin changes state or a watchdog fault
occurs. To clear XALERT, toggle (from 0, set to 1 then reset to 0) OUTPUT CTL (bit 0), then read the STATUS register.
Latch Clear (LTCLR)
When a current limit fault or watch dog timer fault occurs, the state is latched. To clear these faults, toggle (from 0, set 1
then reset to 0) LTCLR in the OUTPUT CTL register (bit 0).
Figure 1 is the LTCLR and XALERT clear example after sensing short-circuit.
I2C
OUTPUT CTRL (b2-b1)
DSG, CHG
OUTPUT CTRL (b3)
XZVCHG
LTCLR
Write = 1
LTCLR
Write = 0
Read STATUS
Register
Staied Disable
Access Enable
Staied Disable
Access Enable
OUTPUT CTRL (b0)
LTCLR
Short Current Timeout
in Discharge Direction
STATUS (b0)
SCDSG
XALERT Pin
Figure 1. LTCLR and XALERT Clear Example After Sensing Short LTCLR and XALER Clear Example
2-, 3-, or 4-Cell Configuration
In a 3-cell configuration, VC1 is shorted to VC2. In a 2-cell configuration, VC1 and VC2 are shorted to VC3.
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Watchdog Input (WDI)
The WDI input is required as a time base for delay timing when determining overload and short-circuit delay periods and
is used as part of the system watchdog.
Initially the watchdog monitors the hosts oscillator start up, if there is no response from the host within 700 ms of the
bq29312 reaching its minimum operating voltage, then the bq29312 turns both CHG, DSG and ZVCHG FETs OFF.
Once the watchdog has been started during this wake up period, it monitors the host for an oscillation stop condition, which
is defined as a period of 100 µs (typ) where no clock input is received. If an oscillator stop condition is identified, then the
watchdog turns the CHG, DSG and ZVCHG FETs OFF. When the host clock oscillation is started, WDF is released, but
the flag is latched until LTCLR is toggled.
REG
GG 32 kHz Output
GG Clock Never Starts
tWDTINT ∼ 700 mS
EXT FET Control
CHG, DSG and
ZVCHG = OFF
Figure 2. Watchdog Timing Chart—WDI Fault at Startup
REG
GG 32 kHz Output
GG Clock Stop
Watchdog Sense
EXT FET Control
tWDWT About 100 µS
CHG, DSG and
ZVCHG = OFF
Figure 3. Watchdog Timing Chart—WDI Fault After Startup
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DSG and CHG FET Driver Control
The bq29312 drives the DSG, CHG, and ZVCHG FET off if an OL or SC safety threshold is breached depending on the
current direction. The host can force any FET on or off only if the bq29312 integrated protection control allows. The DSG
and CHG FET drive gate-to-drain voltage is clamped to 15 V (typ).
The default−state of the CHG and DSG FET drive is off, when PMS = GND. A host can control the FET drive by
programming OUTPUT CTL (b3...b1) where b1 is used to control the discharge FET, b2 is used to control the charge FET
and b3 is used to control the ZVCHG FET. These controls are only valid when not in the initialized state. The CHG drive
FET can be powered by PACK and the DSG FET can be powered by BAT.
Precharge and 0 V Charging—Theory of Operation
The bq29312 supports both a charger that has a precharge mode and one that doesn’t. The bq29312 also supports
charging even when the battery falls to 0 V. Detail is described in the application section.
SLEEP Control Input (SLEEP)
The SLEEP input is pulled-up internally to REG. When SLEEP is pulled to REG, the bq29312 enters the SLEEP mode.
The SLEEP mode disables all the FET outputs and the OL, SC and watchdog faults are also disabled. The RAM
configuration is still valid on exit of the SLEEP mode. The host can force the bq29312 into SLEEP mode via register control
also.
ITEM
FUNCTION
I2C Read/Write
SLEEP
I2C READ/WRITE
EXIT SLEEP
Active
REG Output
Active
External pin control:
CHG, DSG, ZVCHG, TOUT, OD
OC and SC protection:
SCD, SCC and OCD
CELL Translation
PACKOUT, VMEN
Cell Balancing:
CB[3:0]
Watchdog: WDDIS
Disabled
Write is available, but read is disabled
Last pre-sleep entry configuration is valid.
(If change configuration, latest write data is
valid.)
Power Modes
The bq29312 has three power modes, Normal, Sleep, and Ship. The following table outlines the operational functions
during these power modes.
POWER
MODE
Normal
Sleep
Ship
14
TO ENTER POWER MODE
TO EXIT POWER MODE
SLEEP = GND and
STATE CTL( b0) = 0 and
STATE CTL( b1) = 0
MODE DESCRIPTION
The battery is in normal operation with protection, power
management and battery monitoring functions available and
operating.
{SLEEP = REG (floating) or
STATE CTL( b0) = 1 } and
STATE CTL( b1) = 0
SLEEP = GND and
STATE CTL( b0) = 0
STATE CTL( b1) = 1
And supply at the PACK pin is
removed
Supply voltage to PACK
The supply current of this mode varies as the host can enable and
disable various power management features.
All functions stop except LDO and I2C interface.
On entry to this mode, all registers are masked off keeping their
state.
The host controller can change the RAM registers via the I2C
interface, but reading data is disabled until exit of Sleep mode.
The bq29312 is completely shut down as in the sleep mode. In
addition the REG output is disabled, I2C interface is powered
down and memory is not valid.
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
Communications
The I2C compatible serial communications provides read and write access to the bq29312 data area. The data is clocked
via separate data (SDATA) and clock (SCLK) pins. The bq29312 acts as a slave device and does not generate clock pulses.
Communication to the bq29312 is provided from GPIO pins or an I2C supporting port of a host system controller. The slave
address for the bq29312 is 7 bits and the value is 0100 000 (0x20).
I2C ADDRESS +R/W BIT
2
I C ADDRESS (0X20)
(MSB)
(MSB)
(LSB)
(LSB)
Write
0
0
1
0
Read
NOTE: Bit 0: 0 = write, 1= read
0
0
0
0
1
The bq29312 does not have the following functions compatible with the I2C specification.
D
D
D
D
D
The bq29312 is always regarded as a slave.
The bq29312 does not return a NACK for an invalid register address.
The bq29312 does not support the general code of the I2C specification, and therefore does not return an ACK.
The bq29312 does not support the address auto increment, which allows continuous reading and writing.
The bq29312 allows data to written or read from the same location without resending the location address.
…
SCLK
SDATA
A6
Start
…
A5 A4 … A0
R7
R/W ACK
0
0
Slave Address
R6
R5
…
… R0
ACK
0
D7
D5 … D0 ACK
0
Data
Stop
D6
Register Address
Note: Slave = bq29312
Figure 4. I2C-Bus Write to bq29312
…
SCLK
SDATA
A6
…
A5 … A0 R/W
ACK
R7
R6 … R0
ACK
0
0
A6
…
A0
0
Slave Address
Start
…
R/W ACK
1
Register Address
0
Slave Address
D6 … D0 NACK
D7
Slave Drives
The Data
Stop
Master Drives
NACK and Stop
Data
Note: Slave = bq29312
Figure 5. I2C-Bus Read from bq29312: Protocol A
…
SCLK
SDATA
Start
A6
…
A5 … A0 R/W ACK
0
Slave Address
0
R7
…
R6 … R0 ACK
Register
Address
A6
A5 …
…
A0
R/W ACK
0
Stop Start
Slave Address
D7 … D0 NACK
Slave Drives
The Data
Stop
Master Drives
NACK and Stop
Note: Slave = bq29312
Figure 6. I2C-Bus Read from bq29312: Protocol B
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Register Map
The bq29312 has 9 addressable registers. These registers provide status, control, and configuration information for the
battery protection system.
ADDR
TYPE
STATUS
NAME
0x00
R
DESCRIPTION
OUTPUT CTL
0x01
R/W
Output pin control from system host
STATE CTL
0x02
R/W
State control
FUNCTION CTL
0x03
R/W
Function control
CELL _SEL
0x04
R/W
Battery cell select for cell translation and balance bypass and select mode for calibration
OLV
0x05
R/W
Overload threshold voltage
OLT
0x06
R/W
Overload delay time
SCC
0x07
R/W
Short-circuit current threshold voltage and delay for charge
SCD
0x08
R/W
Short-circuit current threshold voltage and delay for discharge
Status register
STATUS : Status register
STATUS REGISTER (0X00)
7
6
5
4
3
2
1
0
0
0
ZVCLMP
SLEEPDET
WDF
OL
SCCHG
SCDSG
The STATUS register provides information about the current state of the bq29312. Reading the STATUS register clears
the XALERT pin.
STATUS b0 (SCDSG): This bit indicates a short-circuit in the discharge direction.
0 = Current below the short-circuit threshold in the discharge direction (default).
1 = Current greater than or equal to the short-circuit threshold in the discharge direction.
STATUS b1 (SCCHG): This bit indicates a short-circuit in the charge direction.
0 = Current below the short-circuit threshold in the charge direction (default).
1 = Current greater than or equal to the short-circuit threshold in the charge direction.
STATUS b2 (OL): This bit indicates an overload condition.
0 = Current less than or equal to the overload threshold (default).
1 = Current greater than overload threshold.
STATUS b3 (WDF): This bit indicates a watchdog fault condition has occurred.
0 = 32kHz oscillation is normal (default).
1 = 32kHz oscillation stopped or not started and the watchdog has timed out.
STATUS b4 (SLEEPDET): This bit indicates the bq29312 is SLEEP mode
0 = bq29312 is not SLEEP mode (default).
1 = bq29312 is SLEEP mode.
STATUS b5 (ZVCLMP): This bit indicates ZVCHG output is clamped.
0 = ZVCHG pin is not clamped (default).
1 = ZVCHG pin is clamped.
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OUTPUT CTL: Output Control Register
OUTPUT CTL REGISTER (0X01)
7
6
5
4
3
2
1
0
0
0
0
OD
XZVCHG
CHG
DSG
LTCLR
The OUPTU CTL register controls the outputs of the bq29312 and can be used to clear certain states.
OUTPUT CTL b0 (LTCLR): When a current limit fault or watchdog timer fault is latched, this bit releases the fault latch when
toggled from 0 to 1 and back to 0 (default =0).
0 = (default)
0−>1 −>0 clears the fault latches
OUTPUT CTL b1 (DSG): This bit controls the external discharge FET.
0 = discharge FET is off and is controlled by the system host (default).
1 = discharge FET is on and the bq29312 is in normal operating mode.
OUTPUT CTL b2 (CHG): This bit controls the external charge FET.
PMS=GND
0 = charge FET is off and is controlled by the system host (default).
1 = charge FET is on and the bq29312 is in normal operating mode.
PMS=PACK
0 = charge FET is off and is controlled by the system host.
1 = charge FET is on and the bq29312 is in normal operating mode (default).
OUTPUT CTL b3 (XZVCHG): This bit controls the external ZVCHG FET.
0 = ZVCHG FET is on and is controlled by the system host (default).
1 = ZVCHG FET is off and the bq29312 is in normal operating mode.
OUTPUT CTL b4 (OD): This bit enables or disables the OD output.
0 = OD is high impedance (default).
1 = OD output is active (GND).
STATE CTL: State Control Register
STATE CTL REGISTER (0X02)
7
6
5
4
3
2
1
0
0
0
0
0
0
WDDIS
SHIP
SLEEP
The STATE CTL register controls the state of the bq29312.
STATE CTL b0 (SLEEP): This bit is used to enter the sleep power mode.
0 = bq29312 exits sleep mode (default).
1 = bq29312 enters the sleep mode.
STATE CTL b1 (SHIP): This bit is used to enter the ship power mode when pack supply voltage is not applied.
0 = bq29312 in normal mode (default).
1 = bq29312 enters ship mode when pack voltage is removed.
STATE CTL b2 (WDDIS): This bit is used to enable or disable the watchdog timer function.
0 = enable clock monitoring (default).
1 = disable clock monitoring.
NOTE: Use caution when setting the WDDIS. For example, when the 32-kHz input fails, the overload and short-circuit delay timers no longer function
because they use the same WDI input. If the WDI input clock stops, these current protections do not function. WDF should be enabled at
any time for maximum safety. If the watchdog function is disabled, the CHG and DSG FETs should be turned off.
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FUNCTION CTL: Function Control Register
FUNCTION CTL REGISTER (0X03)
7
6
5
4
3
2
1
0
0
0
TOUT
XSCD
SSCC
XOL
PACKOUT
VMEN
The FUNCTION CTL register enables and disables functons of the bq29312.
FUNCTION CTL b0 (VMEN): This bit enables or disables the cell and battery voltage monitoring function.
0 = disable voltage monitoring (default). CELL output is pulled down to GND level.
1 = enable voltage monitoring.
FUNCTION CTL b1 (PACKOUT): This bit is used to translate the PACK input to the CELL pin when VMEN=1
The pack voltage is divided by 25 and is presented on CELL regardless of the CELL_SEL register settings.
0 = disable PACK OUT (default).
1 = enable PACK OUT.
FUNCTION CTL b2 (XOL): This bit enables or disables the over current sense function.
0 = enable over load sense (default).
1 = disable over load sense.
FUNCTION CTL b3 (XSCC): This bit enables or disables the short current sense function of charging.
0 = enable short-circuit current sense in charge direction (default).
1 = disable short-circuit current sense in charge direction.
FUNCTION CTL b4 (XSCD): This bit enables or disables the short current sense function of discharge
0 = enable short-circuit current sense in discharge direction (default).
1 = disable short-circuit current sense in discharge direction.
FUNCTION CTL b5 (TOUT): This bit controls the power to the thermistor.
0 = thermistor power is off (default).
1 = thermistor power is on.
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CELL SEL: Cell Select Register
CELL_SEL REGISTER (0X04)
7
6
5
4
3
2
1
0
CB3
CB2
CB1
CB0
CAL1
CAL0
CELL1
CELL0
This register determines cell selection for voltage measurement and translation, cell balancing and the operational mode
of the cell voltage monitoring.
CELL_SEL b0−b1 (CELL0 – CELL1): These two bits select the series cell for voltage measurement translation.
CELL1
CELL0
SELECTED CELL
0
0
VC4−VC5, Bottom series element (Default)
0
1
VC4−VC3, Second lowest series element
1
0
VC3−VC2, Second highest series element
1
1
VC1−VC2, Top series element
CELL_SEL b2−b3 (CAL1, CAL0): These bits determine the mode of the voltage monitor block.
CAL1
CAL0
0
0
Cell translation for selected cell (default)
SELECTED MODE
0
1
Offset measurement for selected cell
1
0
Monitor the VREF value for gain calibration
1
1
Monitor the VREF directly value for gain calibration, bypassing the translation circuit
CELL_SEL b4−b7 (CB0 – CB3): These 4 bits select the series cell for cell balance bypass path.
CELL SEL b4 (CB0): This bit enables or disables the bottom series cell balance charge bypass path
0 = disable bottom series cell balance charge bypass path (default).
1 = enable bottom series cell balance charge bypass path.
CELL SEL b5 (CB1): This bit enables or disables the second lowest series cell balance charge bypass path.
0 = disable series cell balance charge bypass path (default).
1 = enable series cell balance charge bypass path.
CELL SEL b6 (CB2): This bit enables or disables the second highest cell balance charge bypass path.
0 = disable series cell balance charge bypass path (default).
1 = enable series cell balance charge bypass path.
CELL SEL b7 (CB3): This bit enables or disables the highest series cell balance charge bypass path.
0 = disable series cell balance charge bypass path (default).
1 = enable series cell balance charge bypass path.
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OLV: Overload Voltage Threshold Register
OLV REGISTER (0X05)
7
6
5
4
3
2
1
0
0
0
0
OLV4
OLV3
OLV2
OLV1
OLV0
OLV (b4−b0): These five bits select the value of the over load threshold with a default of 00000.
OLV (b4−b0) configuration bits with corresponding voltage threshold
00000
0.050 V
01000
0.090 V
10000
0.130 V
11000
0.170 V
00001
0.055 V
01001
0.095 V
10001
0.135 V
11001
0.175 V
00010
0.060 V
01010
0.100 V
10010
0.140 V
11010
0.180 V
00011
0.065 V
01011
0.105 V
10011
0.145 V
11011
0.185 V
00100
0.070 V
01100
0.110 V
10100
0.150 V
11100
0.190 V
00101
0.075 V
01101
0.115 V
10101
0.155 V
11101
0.195 V
00110
0.080 V
01110
0.120 V
10110
0.160 V
11110
0.200 V
00111
0.085 V
01111
0.125 V
10111
0.165 V
11111
0.205 V
OLT: Overload Blanking Delay Time Register
OLT REGISTER (0X06)
7
6
5
4
3
2
1
0
0
0
0
0
OLT3
OLT2
OLT1
OLT0
OLT(b3−b0): These four bits select the value of the delay time for overload with a default of 0000.
OLT(b3−b0) configuration bits with corresponding delay time
0000
1 ms
0100
9 ms
1000
17 ms
1100
25 ms
0001
3 ms
0101
11 ms
1001
19 ms
1101
27 ms
0010
5 ms
0110
13 ms
1010
21 ms
1110
29 ms
0011
7 ms
0111
15 ms
1011
23 ms
1111
31 ms
SCC: Short Circuit in Charge Configuration Register
SCC REGISTER (0X07)
7
6
5
4
3
2
1
0
SCCT3
SCCT2
SCCT1
SCCT0
SCCV3
SCCV2
SCCV1
SCCV0
This register selects the short-circuit threshold voltage and delay for charge.
SCC(b3−b0) : These bits select the value of the short-circuit voltage threshold with 0000 as the default.
SCC(b3−b0) with corresponding SC threshold voltage
0000
0.100 V
0100
0.200 V
1000
0.300 V
1100
0.400 V
0001
0.125 V
0101
0.225 V
1001
0.325 V
1101
0.425 V
0010
0.150 V
0110
0.250 V
1010
0.350 V
1110
0.450 V
0011
0.175 V
0111
0.275 V
1011
0.375 V
1111
0.475 V
SCC(b7−b4): These bits select the value of the short-circuit delay time. Exceeding the short-circuit voltage threshold for
longer than this period will turn off the corresponding CHG, DSG, and ZVCHG output. 0000 is the default.
SCC(b7−b4) with corresponding SC delay time
20
0000
0 µs
0100
244 µs
1000
488 µs
1100
732 µs
0001
61 µs
0101
305 µs
1001
549 µs
1101
793 µs
0010
122 µs
0110
366 µs
1010
610 µs
1110
854 µs
0011
183 µs
0111
427 µs
1011
671 µs
1111
915 µs
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SCD: Short Circuit in Discharge Configuration Register
SCD REGISTER (0X08)
7
6
5
4
3
2
1
0
SCDT3
SCDT2
SCDT1
SCDT0
SCDV3
SCDV2
SCDV1
SCDV0
This register selects the short-circuit threshold voltage and delay for discharge.
SCD(b3−b0) with corresponding SC threshold voltage with 0000 as the default.
SCD(b3−b0): These bits select the value of the short-circuit voltage threshold
0000
0.10 V
0100
0.20 V
1000
0.30 V
1100
0.40 V
0001
0.125 V
0101
0.225 V
1001
0.325 V
1101
0.425 V
0010
0.150 V
0110
0.250 V
1010
0.350 V
1110
0.450 V
0011
0.175 V
0111
0.275 V
1011
0.375 V
1111
0.475 V
SCD(b7−b4): These bits select the value of the short-circuit delay time. Exceeding the short-circuit voltage threshold for
longer than this period will turn off the corresponding CHG, DSG, and ZVCHG output as has 0000 as the default.
SCD(b7−b4) with corresponding SC delay time
0000
0 µs
0100
244 µs
1000
488 µs
1100
732 µs
0001
61 µs
0101
305 µs
1001
549 µs
1101
793 µs
0010
122 µs
0110
366 µs
1010
610 µs
1110
854 µs
0011
183 µs
0111
427 µs
1011
671 µs
1111
915 µs
21
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
PRECHARGE AND 0-V CHARGING—THEORY OF OPERATION
In order to charge, the charge FET (CHG-FET) must be turned on to create a current path. When the V(BAT) is 0 V and
CHG-FET = ON, the V(PACK) is as low as the battery voltage. In this case, the supply voltage for the device is too low to
operate. There are 3 possible configurations for this function and the bq29312 can be easily configured according to the
application needs. The 3 modes are 0-V Charge FET Mode, Common FET Mode and Precharge FET Mode.
1.
0-V Charge FET Mode − Dedicates a precharge current path using an additional FET (ZVCHG-FET) to sustain
the PACK+ voltage level. The host charger is expected to provide a precharge function.
2.
Common FET Mode − Does not use a dedicated precharge FET. The charge FET (CHG-FET) is assured to be
set to ON state as default. The charger is expected to provide a precharge function.
3.
Precharge FET Mode − Dedicates a precharge current path using an additional open drain (OD) pin drive FET
(PCHG-FET) FET to sustain the PACK+ voltage level. The charger does not provide any precharge function.
0-V Charge FET Mode
In this mode, a dedicated precharge current path using an additional FET (ZVCHG-FET) is required to sustain a suitable
PACK+ voltage level. The charger is expected to provide the precharge function in this mode where the precharge current
level is suitable to charge cells below a set level, typically below 3 V per cell. When the lowest cell voltage rises above this
level, then a fast charging current is applied by the charger.
The circuit diagram for this method is shown in Figure 7, showing how the additional FET is added in parallel with the charge
FET (CHG−FET).
R(ZVCHG)
Charger
ZVCHG-FET
CC
DSG-FET
CHG-FET
DSG
BAT
CHG
bq29312
IZVCHG
Pack+
IFASTCHG
PACK
ZVCHG
Battery
REG
OD
4.7 µF
NC
CV
PMS
I(ZVCHG) = 0 V Percharge Current
I(FASTCHG) = Fast Current
Figure 7. 0-V Charge FET Mode Circuit
22
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
In order to pass 0 V or precharge current an appropriate gate-source voltage V(GS), for ZVCHG-FET must be applied. Here,
V(PACK) can be expressed in terms of V(GS) as follows:
V(PACK) = V(ZVCHG) + V(GS)(ZVCHG−FET gate – source voltage)
ID
Point B
Point A
Precharge
Current
VGS
VDS
Figure 8. Drain Current vs Drain-Source Voltage Characteristics
In the bq29312, the initial state is for CHG-FET = OFF and ZVCHG-FET = ON with the V(ZVCHG) clamped at 3.5 V initially.
Then the charger applies a constant current and raises V(PACK) high enough to pass the precharge current, point A. For
example, if the V(GS) is 2 V at this point, V(PACK) is 3.5 V + 2 V = 5.5 V. Also, the ZVCHG−FET is used in its MOS saturation
region at this point so that V(DS) is expressed as follows:
V(PACK) = V(BAT) + VF + VDS(ZVCHG-FET)
where V(F) = 0.7 V is the forward voltage of a DSG-FET back diode and is typically 0.7 V.
This derives the following equation:
VDS = 4.8 V – V(BAT)
As the battery is charged V(BAT) increases and the V(DS) voltage decreases reaching its linear region. For example: If the
linear region is 0.2 V, this state continues until V(BAT) = 4.6 V, (4.8 V – 0.2 V).
As V(BAT) increases further, V(PACK) and the V(GS) voltage increase. But the VDS remains at 0.2 V because the ZVCHG-FET
is driven in its MOS linear region, point B.
V(PACK) = VF + 0.2 V + V(BAT)
where VF = 0.7 V is the forward voltage of a DSG-FET back diode and is typically 0.7 V
The R(ZVCHG) purpose is to split heat dissipation across the ZVCHG-FET and the resistor.
ZVCHG pin behavior is shown in Figure 9 where V(ZVCHG) is set to 0 V at the beginning.
23
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
20
18
16
V(PACK)
14
Voltage − V
V(ZVCHG)=
V(PACK) − 8 V
V(BAT)
12
10
8
6
4
V(ZVCHG)= V(PACK) / 2
2
3.5 V
0
0
4
8
12
t − Time − mS
16
20
Figure 9. Voltage Transition at ZVCHG, PACK and BAT
As V(PACK) exceeds 7 V, V(ZVCHG) = V(PACK)/2. However, V(ZVCHG) is maintained to limit the voltage between PACK and
ZVCHG at a maximum of 8 V(typ). This limitation is intended to avoid excessive voltage between the gate and the source
of ZVCHG-FET.
The signal timing is shown in Figure 10. When precharge begins (V(BAT) = 0 V) V(PACK) is clamped to 3.5 V and holds the
supply voltage for bq29312 operation. After V(BAT) reaches sufficient voltage high enough for bq29312 operation, the
CHG-FET and the DSG-FET are turned ON and ZVCHG-FET is turned OFF.
Although the current path is changed, the same precharging current is still applied. When V(BAT) reaches the fast charging
voltage (typical 3 V per cell), the charger switches into fast charging mode.
24
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
V(PACK)
3.5 V+VGS(ZVCHGFET)
0V
3.3 V
0V
REG
ZVCHG FET = OFF
ON
V = VPACK*(1/2)
ZVCHG
3.5 V (typ.)
0V
OFF
CHG FET = ON
GHD
”L” (1 V)
OFF
CHG FET = ON
DSG
”L” (1 V)
Battery
Voltage
0V
Charge
Current
Fast Charge Current
0 V and Precharge Current
0A
0 V Charge
Mode
Precharge
Mode
Fast Charge Mode
Figure 10. Signal Timing of Pins During 0 V Charging and Precharging (0 V Charge FET)
Common FET
This mode does not require a dedicated precharge FET (ZVCHG-FET). The charge FET (CHG-FET) is ON at initialization
of the bq29312 when PMS = V(PACK) allowing for 0 V or precharge current to flow. The application circuit is shown in Figure
11. The charger is expected to provide the precharge function in this mode, where the charger provides a precharge current
level suitable to charge cells below a set level, typically below 3.0 V per cell. When the lowest cell voltage rises above this
level then a fast charging current is applied.
When the charger is connected the voltage at PMS rises. Once it is above 0.7 V, the CHG output is driven to GND which
turns ON the CHG-FET. The charging current flows through the CHG-FET and a back diode of DSG-FET. The pack voltage
is represented by the following equation.
V(PACK) = V(BAT) + VF + VDS(CHG-FET)
Where VF = 0.7 V is the forward voltage of a DSG-FET back diode and is typically 0.7 V.
While V(PACK) is maintained above 0.7 V the precharging current is maintained. While V(PACK) and V(BAT) are under the
bq29312 supply voltage then the bq29312 regulator is inactive and the host controller is not functional. Thus, any protection
features of this chipset do not function during this period. This state continues until V(PACK) goes higher than the bq29312
minimum supply voltage.
When V(BAT) rises and V(PACK) reaches bq29312 minimum supply voltage, the REG output is active providing a 3.3 V (typ)
supply to the host. When this level is reached the CHG pin changes its state from GND to the level controlled with CHG
bit in bq29312 registers. In this state, the CHG output level is driven by a clamp circuit so that its voltage level changes
from 0 V to 1 V. Also, the host controller is active and can turn ON the DSG-FET.
The disadvantages is that during 0 V charging, bq29312 is inactive. The device does not protect the battery and does not
update battery information (now is 0 V charging) to the PC.
25
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
There are two advantage of this configuration:
1.
The voltage between BAT and PACK is lower. Higher precharge current is allowed due to less heat loss is the
FET and no external resistor required.
2.
The charge FET is turned on during precharging. The precharge current can be fully controlled by the charger.
Charger
CC
DSG-FET
CHG-FET
DSG
BAT
CHG
PACK
bq29312
Battery
REG
OD
4.7 µF
NC
ZVCHG
DC Input
I(ZVCHG)
Pack+
I(FASTCHG)
CV
PMS
I(ZVCHG) = 0 V Percharge Current
I(FASTCHG) = Fast Current
Figure 11. Common FET Mode Circuit Diagram
The signal timing during the common FET mode is shown in Figure 12. The CHG-FET is turned on when the charger is
connected. As V(BAT) rises and V(PACK) reaches the bq29312 minimum supply voltage, the REG output becomes active
and the host controller starts to work.
When V(PACK) becomes high enough, the host controller turns ON the DSG-FET. The charger enters the fast charging mode
when V(BAT) reaches the fast charge level.
26
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
0.7 V
0V
V(PACK)
Host =
Inactive
Host = Active
REG
3.3 V
0V
PMS
0V
Set to ”L” as
PMS = PACK
CHG
Set to ”L” by Host
”L” (1 V)
0V
Host Sets
DSG-FET to ON
DSG
”L” (1 V)
Battery
Voltage
0V
Charge
Current
Fast Charge Current
0 V and Precharge Current
0A
0 V Precharge Mode
Fast Charge Mode
Figure 12. Signal Timing of Pins During 0 V Charging and Precharging (Common FET)
Precharge FET
This mode has a dedicated precharge current path using an additional open drain driven FET (PCHG-FET) and sustains
the V(PACK) level. In this mode, where the PMS input is connected to GND, the bq29312 and host combine to provide the
precharge function by limiting the fast charge current which is provided by the system side charger.
Figure 13 shows the bq29312 application circuit in this mode.
R(PCHG)
Charger
PCHG-FET
CC
DC Input
I(FASTCHG)
DSG-FET
CHG-FET
DSG
CHG
PACK
OD
BAT
CV
bq29312
Battery
Pack+
ZVCHG
PMS
REG
SCLK SDATA
4.7 µF
I(FASTCHG) = Fast Current
Host
Figure 13. Precharge FET Mode Circuit Diagram
27
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
The PCHG-FET is driven by the OD output and the resister R(PCHG) in the precharge path limits the precharge current.
When OD = GND then the PCHG-FET is ON. The precharge current is represented by the following equation:
I(PCHG) = ID = ( V(PACK) – V(BAT) – VDS )/R(PCHG)
A load curve of the PCHG-FET is shown in Figure 13. When the drain-source voltage (VDS) is high enough, the PCHG-FET
operates in the linear region and has low resistance. By approximating VDS as 0 V, the precharge current, I(PCHG) is
expressed as below.
I(PCHG) = ( V(PACK) – V(BAT) )/R(PCHG)
ID
ID = (V(PACK) − V(BAT) − VDS)/R(PCHG)
VSD
Figure 14. PCHG-FET ID—VDS Characteristic
During the precharge phase, CHG-FET is turned OFF and PCHG-FET is turned ON. When all the cell voltages measured
by the host reach the fast charge threshold, the host controller turns ON CHG-FET and turns OFF PCHG-FET. The signal
timing is shown in Figure 15.
When the charger is connected, CHG-FET, DSG-FET and PCHG-FET are already in the OFF state. When the charger in
connected it applies V(PACK). The bq29312 REG output then becomes active and supplies power to the host controller. As
the host controller starts up, it turns on the OD pin and the precharge current is enabled.
In this configuration, attention must be paid to high power consumption in the PCHG-FET and the series resistor R(PCHG).
The highest power is consumed when VBAT = 0 V, where it is the highest differential between the PACK and BAT pins. For
example, the power consumption in 4 series cells with 17.4 V fast charge voltage and R(PCHG) = 188 Ω is expressed below.
IPCHG = (17.4 V – 0.0 V)/188 Ω = 92.6 mA
17.4 V x 92.6 mA = 1.61 W
An optional solution is to combine a thermistor with a resistor to create R(PCHG), therefore, as temperature increases, the
current reduces.
Once the lowest cell voltage reaches the fast charge level (typ 3.0v per cell), the host controller turns ON CHG-FET and
DSG-FET, and turns OFF PCHG-FET.
It is also appropriate to turn on DSG-FET during precharge in order to supply precharge current efficiently, as shown in
Figure 15.
28
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
Charge CV
V(PACK)
0V
Host : Active
REG
3.3 V
0V
OD
OFF
PCHG FET = ON
OFF
0V
CHG
CHG FET = OFF
”L” (1 V)
DSG FET = ON
DSG
”L” (1 V)
OFF
Battery
Voltage
Charge
Current
0V
Fast Charge Current
Charge
0 V and Precharge Current
0A
Charge Mode
0 V and
Precharge Mode
Fast Charge
Mode
Figure 15. Signal Timing of Pins During 0 V Charging and Precharging (Precharge FET)
Summary
The three types of 0-V charge options available with the bq29312 are summarized below:
CHARGE OPTIONS
CHARGE MODE TYPE
HOST CHARGE CAPABILITIES
KEY APPLICATION CIRCUIT NOTES
1) 0-V Charge FET
Fast charge and precharge
PMS = GND
ZVCHG: Drives 0-V charge FET
(ZVCHG-FET)
OD: Not used
2) Common FET
Fast charge and precharge
PMS = PACK
ZVCHG: Not used
OD: Not used
3) Precharge FET
Fast charge but no precharge function
PMS = GND
ZVCHG: Not used
OD: Drives the precharge FET
(PCHG-FET)
29
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SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
There a number of tradeoffs between the various 0-V charge modes which are discussed below.
D 0-V Charge FET (1) vs Common FET (2)
When the charger has both of precharge and charging functions, there are two types of circuit configuration available.
1.
0-V Charge FET − The bq29312 is active even during precharge. Therefore, the host can update the battery
status to the system and protect the battery pack by detecting abnormal conditions.
− A high voltage is applied on the 0-V charge FET at 0-V cell voltage. In order to avoid excessive heat generation
the 0-V charge current must be limited.
2.
Common FET − During 0-V charge the bq29312 and the host are not active. Therefore, they cannot protect the
cells and cannot update the battery status to the system.
− The bq29312 can tolerate high 0-V charge current as heat generation is not excessive.
− A dedicated FET for the 0-V charge is not required.
D 0-V Charge FET (1) vs Precharge FET (3)
The current paths of the 0-V charge FET (1) and Precharge FET (3) modes are the same. If the 0-V charge FET (1) mode
is used with chargers without precharge function, the bq29312 consumes extra current of up to 1 mA in order to turn ON
the ZVCHG output.
1.
If the charger has a precharge function − ZVCHG-FET is turned ON only during 0-V charging. In this case, 1 mA
increase is not a concern because the charger is connected during the 0-V charging period.
2.
If the charger does not have precharge function − The ZVCHG-FET must be turned ON during 0-V charging and
also precharging. When the battery reaches an over discharged state, it must turn OFF DSG-FET and CHG-FET
and turn ON ZVCHG-FET. The reason for this is the battery must keep the 0-V charge path while waiting for a
charger to be connected to limit the current.
− Consuming 1 mA, while waiting for a charger to be connected in over discharge state, is significant if compared
to current consumption of other modes.
D Precharge FET (3)
If the precharge FET (3) mode is used with a charger with precharge function, care must be taken as limiting the 0-V charge
current with resistance may cause some issues. The charger may start fast charge immediately, or detect an abnormal
condition.
When the charger is connected, the charger may raise the output voltage to force the precharge current. In order to assure
a supply voltage for the bq29312 during 0-V charging, the resistance of a series resister (RPCHG) must be high enough.
This may result in a very high VPACK, and some chargers may detect it as an abnormal condition.
30
MECHANICAL DATA
MPQF124A – FEBRUARY 2002 – REVISED DECEMBER 2002
RGE (S-PQFP-N24)
PLASTIC QUAD FLATPACK
4,15
3,85
4,15
3,85
Pin 1 Index Area
Top and Bottom
1,00
0,80
0,20 REF.
Seating Plane
0,05
0,08
0,00
2,55 MAX SQ.
0,50
24X
0,30
1
6
0,50
24
7
19
12
18
2,50
13
Exposed Thermal Die Pad
(See Note D)
0,30
24X
0,18
0,10
4204104/B 11/02
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Quad Flatpack, No-leads, (QFN) package configuration.
The package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane.
Falls within JEDEC M0-220.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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