TI TLV70033-Q1

TLV70033-Q1
www.ti.com
SLVSA61 – FEBRUARY 2010
200-mA LOW-IQ LOW-DROPOUT REGULATOR FOR PORTABLE DEVICES
Check for Samples: TLV70033-Q1
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
1
23
•
Qualified for Automotive Applications
Very Low Dropout: 175 mV at 200 mA
2% Accuracy
Low IQ: 31 mA
Fixed-Output Voltage of 3.3 V
High PSRR: 68 dB at 1 kHz
Stable with Effective Capacitance of 0.1 mF
Thermal Shutdown and Overcurrent Protection
Latch-Up Performance Meets 100 mA
Per AEC-Q100, Level I
Available in the SOT23-5 (DDC) Package
MP3 Players
ZigBee® Networks
Bluetooth® Devices
DDC PACKAGE
SOT23-5
(TOP VIEW)
IN
1
GND
2
EN
3
5
OUT
4
N/C
(1)
DESCRIPTION
The TLV700xx series of low-dropout (LDO) linear regulators are low quiescent current devices with excellent line
and load transient performance. These LDOs are designed for power-sensitive applications. A precision bandgap
and error amplifier provides overall 2% accuracy. Low output noise, very high power-supply rejection ratio
(PSRR), and low dropout voltage make this series of devices ideal for most battery-operated handheld
equipment. All device versions have thermal shutdown and current limit for safety.
Furthermore, these devices are stable with an effective output capacitance of only 0.1 mF. This feature enables
the use of cost-effective capacitors that have higher bias voltages and temperature derating. The devices
regulate to specified accuracy with no output load.
The TLV700xx LDOs are available in the SOT23-5 (DDC) package.
VIN
IN
OUT
CIN
COUT
VOUT
1 mF
Ceramic
TLV700xx
On
Off
EN
GND
Typical Application Circuit (Fixed-Voltage Versions)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a registered trademark of Bluetooth SIG.
ZigBee is a registered trademark of ZigBee Alliance.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TLV70033-Q1
SLVSA61 – FEBRUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PACKAGE (2)
TJ
–40°C to 125°C
(1)
SOT23 – DDC
ORDERABLE PART NUMBER
Reel of 3000
TLV70033QDDCRQ1
TOP-SIDE MARKING
OFL
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2)
ABSOLUTE MAXIMUM RATINGS (1)
At TJ = –40°C to 125°C (unless otherwise noted). All voltages are with respect to GND.
VIN
Input voltage range
–0.3 V to 6 V
VEN
Enable voltage range
–0.3 V to 6 V
VOUT
Output voltage range
–0.3 V to 6 V
IOUT
Maximum output current
Internally limited
Output short-circuit duration
Indefinite
PD
Total continuous power dissipation
TJ
Operating junction temperature range
–55°C to 150°C
TSTG
Storage temperature range
–55°C to 150°C
(1)
See Dissipation Ratings
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
DISSIPATION RATINGS
BOARD
PACKAGE
RqJC
RqJA
DERATING FACTOR
ABOVE TA = 25°C
TA ≤ 25°C
TA = 70°C
TA = 85°C
Low-K (1)
DDC
90°C/W
280°C/W
3.6 mW/°C
360 mW
200 mW
145 mW
High-K (2)
DDC
90°C/W
200°C/W
5.0 mW/°C
500 mW
275 mW
200 mW
(1)
(2)
2
The JEDEC low-K (1s) board used to derive this data was a 3-inch × 3-inch, two-layer board with 2-ounce copper traces on top of the
board.
The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
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SLVSA61 – FEBRUARY 2010
ELECTRICAL CHARACTERISTICS
VIN = VOUT(Typ) + 0.3 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF, and TJ = –40°C to 125°C
(unless otherwise noted). Typical values are at TJ = 25°C.
space
TLV700xx
PARAMETER
VIN
TEST CONDITIONS
Input voltage range
MAX
UNIT
2.0
5.5
V
–2
+2
%
VOUT < 1 V
–20
20
mV
5
mV
–40°C ≤ TJ ≤ 125°C
ΔVO/ΔVIN
Line regulation
VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V,
IOUT = 10 mA
ΔVO/ΔIOUT
Load regulation
0 mA ≤ IOUT ≤ 200 mA
VDO
Dropout voltage (1)
VIN = 0.98 × VOUT(NOM), IOUT = 200 mA
ICL
Output current limit
VOUT = 0.9 × VOUT(NOM)
1
220
IOUT = 0 mA
1
15
mV
175
250
mV
350
550
mA
31
55
mA
IGND
Ground pin current
ISHDN
Ground pin current (shutdown)
VEN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 4.5 V
Power-supply rejection ratio
VIN = 2.3 V, VOUT = 1.8 V,
IOUT = 10 mA, f = 1 kHz
68
dB
Output noise voltage
BW = 100 Hz to 100 kHz,
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
48
mVRMS
PSRR
VN
tSTR
Startup time
(2)
VEN(HI)
Enable pin high (enabled)
VEN(LO)
Enable pin low (disabled)
IEN
UVLO
(1)
(2)
TYP
VOUT ≥ 1 V
DC output accuracy
VOUT
MIN
IOUT = 200 mA, VIN = VOUT + 0.5 V
270
1
COUT = 1.0 mF, IOUT = 200 mA
mA
2
mA
100
0.9
ms
VIN
0
0.4
V
0.5
mA
Enable pin current
VEN = 5.5 V , IOUT = 10 mA
Undervoltage lockout
VIN rising
1.9
V
Shutdown, temperature increasing
160
°C
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
0.04
V
Reset, temperature decreasing
140
–40
°C
125
°C
VDO is measured for devices with VOUT(NOM) ≥ 2.35 V.
Startup time = time from EN assertion to 0.98 × VOUT(NOM).
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TLV70033-Q1
SLVSA61 – FEBRUARY 2010
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FUNCTIONAL BLOCK DIAGRAM
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EN
Bandgap
LOGIC
TLV700xx Series
GND
PIN CONFIGURATIONS
DDC PACKAGE
SOT23-5
(TOP VIEW)
IN
1
GND
2
EN
3
5
OUT
4
N/C
(1)
PIN DESCRIPTIONS
4
NAME
NO.
DESCRIPTION
IN
1
Input pin. A small 1-mF ceramic capacitor is recommended from this pin to ground to assure stability and good
transient performance. See Input and Output Capacitor Requirements in the Application Information section for
more details.
GND
2
Ground pin
EN
3
Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown
mode and reduces operating current to 1 mA, nominal.
NC
4
No connection. This pin can be tied to ground to improve thermal dissipation.
OUT
5
Regulated output voltage pin. A small 1-mF ceramic capacitor is needed from this pin to ground to assure stability.
See Input and Output Capacitor Requirements in the Application Information section for more details.
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TLV70033-Q1
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SLVSA61 – FEBRUARY 2010
TYPICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF (unless
otherwise noted). Typical values are at TJ = 25°C.
TLV70018
LINE REGULATION
1.90
TLV70018
LINE REGULATION
1.90
IOUT = 10 mA
1.88
1.88
1.86
1.84
1.82
1.80
1.78
1.76
+125°C
+85°C
+25°C
-40°C
1.74
1.72
Output Voltage (V)
Output Voltage (V)
1.86
IOUT = 200 mA
1.84
1.82
1.80
1.78
1.76
+125°C
+85°C
+25°C
-40°C
1.74
1.72
1.70
1.70
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
2.1
2.6
Input Voltage (V)
5.1
TLV70018
LOAD REGULATION
TLV70048
DROPOUT VOLTAGE vs INPUT VOLTAGE
1.84
1.82
1.80
1.78
1.76
+125°C
+85°C
+25°C
-40°C
1.74
1.72
1.70
60
80
100 120 140
160
180 200
Dropout Voltage (mV)
1.86
Output Voltage (V)
4.6
Figure 2.
250
40
4.1
Figure 1.
1.88
20
3.6
5.6
Input Voltage (V)
1.90
0
3.1
IOUT = 200 mA
200
150
100
+125°C
+85°C
+25°C
-40°C
50
0
2.25
2.75
3.25
3.75
4.25
4.75
Input Voltage (V)
Output Current (mA)
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF (unless
otherwise noted). Typical values are at TJ = 25°C.
TLV70018
OUTPUT VOLTAGE vs TEMPERATURE
180
1.90
160
1.88
140
1.86
120
100
80
60
+125°C
+85°C
+25°C
-40°C
40
20
Output Voltage (V)
Dropout Voltage (V)
TLV70048
DROPOUT VOLTAGE vs OUTPUT CURRENT
30
60
90
120
150
180
1.82
1.80
1.78
1.76
IOUT = 200 mA
IOUT = 10 mA
IOUT = 150 mA
1.74
1.72
1.70
0
0
1.84
-40 -25 -10
210
5
Ground Pin Current (mA)
45
50
65
80
Figure 6.
TLV70018
GROUND PIN CURRENT vs INPUT VOLTAGE
TLV70018
GROUND PIN CURRENT vs LOAD
95
110 125
300
IOUT = 0 mA
40
35
30
25
20
15
+125°C
+85°C
+25°C
-40°C
10
5
250
200
150
100
+125°C
+85°C
+25°C
-40°C
50
0
0
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
0
20
40
60
80
100 120 140 160 180 200
Output Current (mA)
Input Voltage (V)
Figure 7.
6
35
Figure 5.
Ground Pin Current (mA)
50
20
Temperature (°C)
Output Current (mA)
Figure 8.
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SLVSA61 – FEBRUARY 2010
TYPICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF (unless
otherwise noted). Typical values are at TJ = 25°C.
TLV70018
SHUTDOWN CURRENT vs INPUT VOLTAGE
40
2.0
35
1.8
Shutdown Current (mA)
Ground Pin Current (mA)
TLV70018
GROUND PIN CURRENT vs TEMPERATURE
30
25
20
15
10
5
1.6
1.4
1.2
1.0
0.8
0.6
+125°C
+85°C
+25°C
0.4
0.2
IOUT = 0 mA
0
0
-40 -25 -10
5
20
35
50
65
80
95
110 125
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
Input Voltage (V)
Figure 9.
Figure 10.
TLV70018
CURRENT LIMIT vs INPUT VOLTAGE
TLV70018
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
440
100
430
90
420
80
IOUT = 10 mA
IOUT = 150 mA
70
410
PSRR (dB)
Current Limit (mA)
Temperature (°C)
400
390
380
60
50
40
30
370
20
360
TA = +25°C
350
2.0
2.5
3.0
3.5
4.0
4..5
10
VIN - VOUT = 0.5 V
0
10
Input Voltage (V)
100
1k
10 k
100 k
1M
10 M
Frequency (Hz)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF (unless
otherwise noted). Typical values are at TJ = 25°C.
TLV70018
POWER-SUPPLY RIPPLE REJECTION vs INPUT VOLTAGE
1 kHz
70
60
PSRR (dB)
Output Spectral Noise Density (mV/ÖHz)
80
10 kHz
50
100 kHz
40
30
20
10
0
2.1
2.2
2.3
TLV70018
OUTPUT SPECTRAL NOISE DENSITY vs OUTPUT VOLTAGE
2.4
2.5
2.6
2.7
10
1
0.1
0.01
IOUT = 10 mA
CIN = COUT = 1 mF
0
10
2.8
100
100 k
TLV70018
LOAD TRANSIENT RESPONSE
TLV70018
LOAD TRANSIENT RESPONSE
IOUT
0 mA
5 mV/div
VOUT
10 mA
0 mA
IOUT
VOUT
VIN = 2.3 V
10 ms/div
10 ms/div
Figure 15.
Figure 16.
TLV70018
LOAD TRANSIENT RESPONSE
TLV70018
LINE TRANSIENT RESPONSE
Slew Rate = 1 V/ms
IOUT
50 mA
1 V/div
0 mA
VIN
2.9 V
2.3 V
5 mV/div
50 mA/div
tR = tF = 1 ms
20 mV/div
10 M
tR = tF = 1 ms
200 mA
VIN = 2.1 V
VOUT
VIN = 2.3 V
8
1M
Figure 14.
20 mA/div
100 mA/div
10 k
Figure 13.
tR = tF = 1 ms
50 mV/div
1k
Frequency (Hz)
Input Voltage (V)
VOUT
IOUT = 200 mA
10 ms/div
1 ms/div
Figure 17.
Figure 18.
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SLVSA61 – FEBRUARY 2010
TYPICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF (unless
otherwise noted). Typical values are at TJ = 25°C.
VIN
TLV70018
LINE TRANSIENT RESPONSE
Slew Rate = 1 V/ms
Slew Rate = 1 V/ms
2.7 V
1 V/div
1 V/div
TLV70018
LINE TRANSIENT RESPONSE
2.3 V
VIN
5.5 V
10 mV/div
5 mV/div
2.1 V
VOUT
VOUT
IOUT = 200 mA
IOUT = 1 mA
1 ms/div
1 ms/div
Figure 19.
Figure 20.
TLV70018
VIN RAMP UP, RAMP DOWN RESPONSE
IOUT = 1 mA
1 V/div
VIN
VOUT
200 ms/div
Figure 21.
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APPLICATION INFORMATION
The TLV700xx belongs to a new family of next-generation value LDO regulators. It consumes low quiescent
current and delivers excellent line and load transient performance. These characteristics, combined with low
noise, very good PSRR with little (VIN – VOUT) headroom, make this device ideal for RF portable applications.
This family of regulators offers sub-bandgap output voltages down to 0.7 V, current limit, and thermal protection,
and is specified from –40°C to 125°C.
Input and Output Capacitor Requirements
1.0-mF X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal
variation in value and equivalent series resistance (ESR) over temperature.
However, the TLV700xx is designed to be stable with an effective capacitance of 0.1 mF or larger at the output.
Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective capacitance
under operating bias voltage and temperature is greater than 0.1 mF. This effective capacitance refers to the
capacitance that the LDO sees under operating bias voltage and temperature conditions; that is, the capacitance
after taking both bias voltage and temperature derating into consideration. In addition to allowing the use of
cheaper dielectrics, this capability of being stable with 0.1-mF effective capacitance also enables the use of
smaller footprint capacitors that have higher derating in size- and space-constrained applications.
Note that using a 0.1-mF rated capacitor at the output of the LDO does not ensure stability because the effective
capacitance under the specified operating conditions would be less than 0.1 mF. Maximum ESR should be less
than 200 mΩ.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-mF to
1.0-mF, low ESR capacitor across the IN pin and GND in of the regulator. This capacitor counteracts reactive
input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor
may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the
power source. If source impedance is more than 2 Ω, a 0.1-mF input capacitor may be necessary to ensure
stability.
Board Layout Recommendations to Improve PSRR and Noise Performance
Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance
such as PSRR, output noise, and transient response, it is recommended that the board be designed with
separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In
addition, the ground connection for the output capacitor should be connected directly to the GND pin of the
device. High ESR capacitors may degrade PSRR performance.
Internal Current Limit
The TLV700xx internal current limit helps to protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the
output voltage is not regulated, and is VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) ×
ILIMIT until thermal shutdown is triggered and the device turns off. As the device cools down, it is turned on by the
internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and
thermal shutdown. See the Thermal Information section for more details.
The PMOS pass element in the TLV700xx has a built-in body diode that conducts current when the voltage at
OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is
anticipated, external limiting to 5% of the rated output current is recommended.
Shutdown
The enable pin (EN) is active high and is compatible with standard and low-voltage, TTL-CMOS levels. When
shutdown capability is not required, EN can be connected to the IN pin.
10
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Dropout Voltage
The TLV700xx uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves as a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.
This effect is shown in Figure 13 in the Typical Characteristics section.
Transient Response
As with any regulator, increasing the size of the output capacitor reduces over-/undershoot magnitude but
increases the duration of the transient response.
Undervoltage Lockout (UVLO)
The TLV700xx uses an undervoltage lockout circuit to keep the output shut off until internal circuitry is operating
properly.
Thermal Information
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 35°C above the maximum expected ambient condition of the particular application. This
configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature
and worst-case load.
The internal protection circuitry of the TLV700xx has been designed to protect against overload conditions. It was
not intended to replace proper heatsinking. Continuously running the TLV700xx into thermal shutdown degrades
device reliability.
Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low and high-K boards are given in the
Dissipation Ratings table. Using heavier copper increases the effectiveness in removing heat from the device.
The addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current and the voltage drop across the output pass element, as shown in Equation 1.
PD = (VIN - VOUT) ´ IOUT
(1)
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PACKAGE OPTION ADDENDUM
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18-Feb-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TLV70033QDDCRQ1
ACTIVE
SOT
DDC
Pins Package Eco Plan (2)
Qty
5
3000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV70033-Q1 :
• Catalog: TLV70033
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
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