FUJITSU SEMICONDUCTOR DATA SHEET DS05-20886-1E FLASH MEMORY CMOS 64M (4M × 16) BIT MBM29LV652UE -90/12 ■ GENERAL DESCRIPTION The MBM29LV652UE is a 64M-bit, 3.0 V-only Flash memory organized as 4M words of 16 bits each. The device is designed to MBM29LV652UEbe programmed in system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29LV652UE is entirely command set compatible with JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Typically, each sector can be programmed and verified in about 0.5 seconds. ■ PRODUCT LINE UP Part No. MBM29LV652UE VCC = 3.3 V +0.3 V –0.3 V 90 — VCC = 3.0 V +0.6 V –0.3 V — 12 Max. Address Access Time (ns) 90 120 Max. CE Access Time (ns) 90 120 Max. OE Access Time (ns) 35 50 Ordering Part No. ■ PACKAGES 63-pin plastic FBGA BGA-63P-M02 MBM29LV652UE-90/12 (Continued) A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV652UE is erased when shipped from the factory. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. The devices electrically erase all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The words are programmed one word at a time using the EPROM programming mechanism of hot electron injection. ■ FEATURES • 0.23 µm Process Technology • Single 3.0 V read, program and erase Minimizes system level power requirements • Compatible with JEDEC-standards Uses same software commands with single-power supply Flash • Address don’t care during the command sequence • Industry-standard pinouts 63-ball FBGA (Package suffix: PBT) • Minimum 100,000 program/erase cycles • High performance 90 ns maximum access time • Flexible sector architecture One hundred twenty-eight 32K word sectors Any combination of sectors can be concurrently erased. Also supports full chip erase • Hidden ROM (Hi-ROM) region 128 word of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • ACC input pin At VACC, increases program performance • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded programTM* Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Sector group protection Hardware method disables any combination of sector groups from program or erase operations • Sector Group Protection Set function by Extended sector protect command • Fast Programming Function by Extended Command (Continued) 2 MBM29LV652UE-90/12 (Continued) • Temporary sector group unprotection Temporary sector group unprotection via the RESET pin This feature allows code changes in previously locked sectors • In accordance with CFI (Common Flash Memory Interface) *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 3 MBM29LV652UE-90/12 ■ PIN ASSIGNMENT FBGA (TOP VIEW) Marking Side A8 B8 L8 M8 N.C. N.C. N.C. N.C. A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 L7 M7 N.C. N.C. A13 A12 A14 A15 A16 Vccq DQ15 Vss N.C. N.C. C6 D6 E6 F6 G6 H6 J6 K6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 C5 D5 E5 F5 G5 H5 J5 K5 WE RESET A21 A19 DQ5 DQ12 Vcc DQ4 C4 D4 E4 F4 G4 H4 J4 K4 RY/BY ACC A18 A20 DQ2 DQ10 DQ11 DQ3 C3 D3 E3 F3 G3 H3 J3 K3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N.C. A3 A4 A2 A1 A0 CE OE Vss N.C. N.C. A1 B1 L1 M1 N.C. N.C. N.C. N.C. BGA-63P-M02 *:Peripheral balls on each corner are shorted together via the substrate but not connected to the die. 4 MBM29LV652UE-90/12 ■ PIN DESCRIPTION Table1 MBM29LV652UE Pin Configuration Pin A0 to A21 DQ0 to DQ15 Function Address Inputs Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable RY/BY Ready/Busy Output RESET Hardware Reset Pin/Temporary Sector Group Unprotection ACC Program Acceleration VCCq Output Buffer Power N.C. No Internal Connection VSS Device Ground VCC Device Power Supply 5 MBM29LV652UE-90/12 ■ BLOCK DIAGRAM RY/BY Buffers VCC VSS WE DQ0 to DQ15 RY/BY Input/Output Buffers Erase Voltage Generator State Control RESET ACC Command Register Program Voltage Generator Chip Enable Output Enable Logic CE OE STB Timer for Program/Erase A0 to A21 6 Address Latch STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix VCCq MBM29LV652UE-90/12 ■ LOGIC SYMBOL 22 A0 to A21 16 DQ 0 to DQ 15 CE OE RY/BY WE RESET ACC VCCq 7 MBM29LV652UE-90/12 ■ DEVICE BUS OPERATION Table2 MBM29LV652UE User Bus Operations CE OE WE A0 A1 A6 A9 Auto-Select Manufacture Code *1 L L H L L L VID Code H Auto-Select Device Code *1 L L H H L L VID Code H Read *3 L L H A0 A1 A6 A9 DOUT H Standby H X X X X X X HIGH-Z H Output Disable L H H X X X X HIGH-Z H Write (Program/Erase) L H L A0 A1 A6 A9 DIN H Enable Sector Group Protection *2 *4 L VID L H L VID X H Verify Sector Group Protection *2 *4 L L H L H L VID Code H Temporary Sector Group Unprotection *5 X X X X X X X X VID Reset (Hardware)/Standby X X X X X X X HIGH-Z L Operation Legend: L = VIL, H = VIH, X = VIL or VIH. DQ0 to DQ15 RESET = Pulse input. See DC Characteristics for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See Table 3. *2: Refer to the section on Sector Group Protection. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.3 V ±10% *5: It is also used for the extended sector group protection. 8 MBM29LV652UE-90/12 Table3 MBM29LV652UE Command Definitions Command Sequence Bus First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Write Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Cycles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read/Reset 1 XXXh Read/Reset 3 Autoselect F0h — — — — — — — — — — XXXh AAh XXXh 55h XXXh F0h RA RD — — — — 3 XXXh AAh XXXh 55h XXXh 90h — — — — — — Program 4 XXXh AAh XXXh 55h XXXh A0h PA PD — — — — Chip Erase 6 XXXh AAh XXXh 55h XXXh 80h XXXh AAh XXXh 55h XXXh 10h Sector Erase 6 XXXh AAh XXXh 55h XXXh 80h XXXh AAh XXXh 55h SA 30h Erase Suspend 1 XXXh B0h — — — — — — — — — — Erase Resume 1 XXXh 30h — — — — — — — — — — Set to Fast Mode 3 XXXh AAh XXXh 55h XXXh 20h — — — — — — Fast Program *1 2 XXXh A0h PA PD — — — — — — — — Reset from Fast Mode *1 2 XXXh 90h XXXh F0h — — — — — — — — Extended Sector Group Protection *2 4 XXXh 60h SPA 60h SPA 40h SPA SD — — — — Query *3 1 XXh 98h — — — — — — — — — — Hi-ROM Entry 3 XXXh AAh XXXh 55h XXXh 88h — — — — — — Hi-ROM Program *4 4 XXXh AAh XXXh 55h XXXh A0h PA PD — — — — Hi-ROM Exit *4 4 XXXh AAh XXXh 55h XXXh 90h XXXh 00h — — — — 9 MBM29LV652UE-90/12 *1: This command is valid while Fast Mode. *2: This command is valid while RESET = VID. *3: The valid addresses are A6 to A0. *4: This command is valid while Hi-ROM mode. Notes: 1. Address bits = X = “H” or “L” for all address commands except or Program Address (PA) and Sector Address (SA). 2. Bus operations are defined in Table 2. 3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16 and A15 will uniquely select any sector. 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse. 5. SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. 6. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. 10 MBM29LV652UE-90/12 Table 4 .1 MBM29LV652UE Sector Group Protection Verify Autoselect Codes A17 to A21 A6 A1 A0 Code (HEX) Manufacturer’s Code X VIL VIL VIL 04h Device Code MBM29LV652UE X VIL VIL VIH 22D7h Sector Group Addresses VIL VIH VIL 01h * Type Sector Group Protection *: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. Table 4 .2 Type Manufacturer’s Code Device MBM29LV652UE Code Sector Group Protection Code Expanded Autoselect Code Table DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04h 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 22D7h 0 0 1 0 0 0 1 0 1 1 0 1 0 1 1 1 01h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 11 MBM29LV652UE-90/12 ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE Table 5 Sector Address Tables Sector Address A21 A20 A19 A18 A17 A16 A15 Sector Size Address Range SA0 0 0 0 0 0 0 0 32K words 000000h to 007FFFh SA1 0 0 0 0 0 0 1 32K words 008000h to 00FFFFh SA2 0 0 0 0 0 1 0 32K words 010000h to 017FFFh SA3 0 0 0 0 0 1 1 32K words 018000h to 01FFFFh SA4 0 0 0 0 1 0 0 32K words 020000h to 027FFFh SA5 0 0 0 0 1 0 1 32K words 028000h to 02FFFFh SA6 0 0 0 0 1 1 0 32K words 030000h to 037FFFh SA7 0 0 0 0 1 1 1 32K words 038000h to 03FFFFh SA8 0 0 0 1 0 0 0 32K words 040000h to 047FFFh SA9 0 0 0 1 0 0 1 32K words 048000h to 04FFFFh SA10 0 0 0 1 0 1 0 32K words 050000h to 057FFFh SA11 0 0 0 1 0 1 1 32K words 058000h to 05FFFFh SA12 0 0 0 1 1 0 0 32K words 060000h to 067FFFh SA13 0 0 0 1 1 0 1 32K words 068000h to 06FFFFh SA14 0 0 0 1 1 1 0 32K words 070000h to 077FFFh SA15 0 0 0 1 1 1 1 32K words 078000h to 07FFFFh SA16 0 0 1 0 0 0 0 32K words 080000h to 087FFFh SA17 0 0 1 0 0 0 1 32K words 088000h to 08FFFFh SA18 0 0 1 0 0 1 0 32K words 090000h to 097FFFh SA19 0 0 1 0 0 1 1 32K words 098000h to 09FFFFh SA20 0 0 1 0 1 0 0 32K words 0A0000h to 0A7FFFh SA21 0 0 1 0 1 0 1 32K words 0A8000h to 0AFFFFh SA22 0 0 1 0 1 1 0 32K words 0B0000h to 0B7FFFh SA23 0 0 1 0 1 1 1 32K words 0B8000h to 0BFFFFh SA24 0 0 1 1 0 0 0 32K words 0C0000h to 0C7FFFh SA25 0 0 1 1 0 0 1 32K words 0C8000h to 0CFFFFh SA26 0 0 1 1 0 1 0 32K words 0D0000h to 0D7FFFh SA27 0 0 1 1 0 1 1 32K words 0D8000h to 0DFFFFh SA28 0 0 1 1 1 0 0 32K words 0E0000h to 0E7FFFh SA29 0 0 1 1 1 0 1 32K words 0E8000h to 0EFFFFh SA30 0 0 1 1 1 1 0 32K words 0F0000h to 0F7FFFh SA31 0 0 1 1 1 1 1 32K words 0F8000h to 0FFFFFh (Continued) 12 MBM29LV652UE-90/12 (Continued) Sector Address A21 A20 A19 A18 A17 A16 A15 Sector Size Address Range SA32 0 1 0 0 0 0 0 32K words 100000h to 107FFFh SA33 0 1 0 0 0 0 1 32K words 108000h to 10FFFFh SA34 0 1 0 0 0 1 0 32K words 110000h to 117FFFh SA35 0 1 0 0 0 1 1 32K words 118000h to 11FFFFh SA36 0 1 0 0 1 0 0 32K words 120000h to 127FFFh SA37 0 1 0 0 1 0 1 32K words 128000h to 12FFFFh SA38 0 1 0 0 1 1 0 32K words 130000h to 137FFFh SA39 0 1 0 0 1 1 1 32K words 138000h to 13FFFFh SA40 0 1 0 1 0 0 0 32K words 140000h to 147FFFh SA41 0 1 0 1 0 0 1 32K words 148000h to 14FFFFh SA42 0 1 0 1 0 1 0 32K words 150000h to 157FFFh SA43 0 1 0 1 0 1 1 32K words 158000h to 15FFFFh SA44 0 1 0 1 1 0 0 32K words 160000h to 167FFFh SA45 0 1 0 1 1 0 1 32K words 168000h to 16FFFFh SA46 0 1 0 1 1 1 0 32K words 170000h to 177FFFh SA47 0 1 0 1 1 1 1 32K words 178000h to 17FFFFh SA48 0 1 1 0 0 0 0 32K words 180000h to 187FFFh SA49 0 1 1 0 0 0 1 32K words 188000h to 18FFFFh SA50 0 1 1 0 0 1 0 32K words 190000h to 197FFFh SA51 0 1 1 0 0 1 1 32K words 198000h to 19FFFFh SA52 0 1 1 0 1 0 0 32K words 1A0000h to 1A7FFFh SA53 0 1 1 0 1 0 1 32K words 1A8000h to 1AFFFFh SA54 0 1 1 0 1 1 0 32K words 1B0000h to 1B7FFFh SA55 0 1 1 0 1 1 1 32K words 1B8000h to 1BFFFFh SA56 0 1 1 1 0 0 0 32K words 1C0000h to 1C7FFFh SA57 0 1 1 1 0 0 1 32K words 1C8000h to 1CFFFFh SA58 0 1 1 1 0 1 0 32K words 1D0000h to 1D7FFFh SA59 0 1 1 1 0 1 1 32K words 1D8000h to 1DFFFFh SA60 0 1 1 1 1 0 0 32K words 1E0000h to 1E7FFFh SA61 0 1 1 1 1 0 1 32K words 1E8000h to 1EFFFFh SA62 0 1 1 1 1 1 0 32K words 1F0000h to 1F7FFFh SA63 0 1 1 1 1 1 1 32K words 1F8000h to 1FFFFFh (Continued) 13 MBM29LV652UE-90/12 (Continued) Sector Address A21 A20 A19 A18 A17 A16 A15 Sector Size Address Range SA64 1 0 0 0 0 0 0 32K words 200000h to 207FFFh SA65 1 0 0 0 0 0 1 32K words 208000h to 20FFFFh SA66 1 0 0 0 0 1 0 32K words 210000h to 217FFFh SA67 1 0 0 0 0 1 1 32K words 218000h to 21FFFFh SA68 1 0 0 0 1 0 0 32K words 220000h to 227FFFh SA69 1 0 0 0 1 0 1 32K words 228000h to 22FFFFh SA70 1 0 0 0 1 1 0 32K words 230000h to 237FFFh SA71 1 0 0 0 1 1 1 32K words 238000h to 23FFFFh SA72 1 0 0 1 0 0 0 32K words 240000h to 247FFFh SA73 1 0 0 1 0 0 1 32K words 248000h to 24FFFFh SA74 1 0 0 1 0 1 0 32K words 250000h to 257FFFh SA75 1 0 0 1 0 1 1 32K words 258000h to 25FFFFh SA76 1 0 0 1 1 0 0 32K words 260000h to 267FFFh SA77 1 0 0 1 1 0 1 32K words 268000h to 26FFFFh SA78 1 0 0 1 1 1 0 32K words 270000h to 277FFFh SA79 1 0 0 1 1 1 1 32K words 278000h to 27FFFFh SA80 1 0 1 0 0 0 0 32K words 280000h to 287FFFh SA81 1 0 1 0 0 0 1 32K words 288000h to 28FFFFh SA82 1 0 1 0 0 1 0 32K words 290000h to 297FFFh SA83 1 0 1 0 0 1 1 32K words 298000h to 29FFFFh SA84 1 0 1 0 1 0 0 32K words 2A0000h to 2A7FFFh SA85 1 0 1 0 1 0 1 32K words 2A8000h to 2AFFFFh SA86 1 0 1 0 1 1 0 32K words 2B0000h to 2B7FFFh SA87 1 0 1 0 1 1 1 32K words 2B8000h to 2BFFFFh SA88 1 0 1 1 0 0 0 32K words 2C0000h to 2C7FFFh SA89 1 0 1 1 0 0 1 32K words 2C8000h to 2CFFFFh SA90 1 0 1 1 0 1 0 32K words 2D0000h to 2D7FFFh SA91 1 0 1 1 0 1 1 32K words 2D8000h to 2DFFFFh SA92 1 0 1 1 1 0 0 32K words 2E0000h to 2E7FFFh SA93 1 0 1 1 1 0 1 32K words 2E8000h to 2EFFFFh SA94 1 0 1 1 1 1 0 32K words 2F0000h to 2F7FFFh SA95 1 0 1 1 1 1 1 32K words 2F8000h to 2FFFFFh (Continued) 14 MBM29LV652UE-90/12 (Continued) Sector Address A21 A20 A19 A18 A17 A16 A15 Sector Size Address Range SA96 1 1 0 0 0 0 0 32K words 300000h to 307FFFh SA97 1 1 0 0 0 0 1 32K words 308000h to 30FFFFh SA98 1 1 0 0 0 1 0 32K words 310000h to 317FFFh SA99 1 1 0 0 0 1 1 32K words 318000h to 31FFFFh SA100 1 1 0 0 1 0 0 32K words 320000h to 327FFFh SA101 1 1 0 0 1 0 1 32K words 328000h to 32FFFFh SA102 1 1 0 0 1 1 0 32K words 330000h to 337FFFh SA103 1 1 0 0 1 1 1 32K words 338000h to 33FFFFh SA104 1 1 0 1 0 0 0 32K words 340000h to 347FFFh SA105 1 1 0 1 0 0 1 32K words 348000h to 34FFFFh SA106 1 1 0 1 0 1 0 32K words 350000h to 357FFFh SA107 1 1 0 1 0 1 1 32K words 358000h to 35FFFFh SA108 1 1 0 1 1 0 0 32K words 360000h to 367FFFh SA109 1 1 0 1 1 0 1 32K words 368000h to 36FFFFh SA110 1 1 0 1 1 1 0 32K words 370000h to 377FFFh SA111 1 1 0 1 1 1 1 32K words 378000h to 37FFFFh SA112 1 1 1 0 0 0 0 32K words 380000h to 387FFFh SA113 1 1 1 0 0 0 1 32K words 388000h to 38FFFFh SA114 1 1 1 0 0 1 0 32K words 390000h to 397FFFh SA115 1 1 1 0 0 1 1 32K words 398000h to 39FFFFh SA116 1 1 1 0 1 0 0 32K words 3A0000h to 3A7FFFh SA117 1 1 1 0 1 0 1 32K words 3A8000h to 3AFFFFh SA118 1 1 1 0 1 1 0 32K words 3B0000h to 3B7FFFh SA119 1 1 1 0 1 1 1 32K words 3B8000h to 3BFFFFh SA120 1 1 1 1 0 0 0 32K words 3C0000h to 3C7FFFh SA121 1 1 1 1 0 0 1 32K words 3C8000h to 3CFFFFh SA122 1 1 1 1 0 1 0 32K words 3D0000h to 3D7FFFh SA123 1 1 1 1 0 1 1 32K words 3D8000h to 3DFFFFh SA124 1 1 1 1 1 0 0 32K words 3E0000h to 3E7FFFh SA125 1 1 1 1 1 0 1 32K words 3E8000h to 3EFFFFh SA126 1 1 1 1 1 1 0 32K words 3F0000h to 3F7FFFh SA127 1 1 1 1 1 1 1 32K words 3F8000h to 3FFFFFh 15 MBM29LV652UE-90/12 Table 6 16 Sector Group Address Sector Group Address A21 A20 A19 A18 A17 Sector Group Size Sectors SGA0 0 0 0 0 0 128K words SA0 to SA3 SGA1 0 0 0 0 1 128K words SA4 to SA7 SGA2 0 0 0 1 0 128K words SA8 to SA11 SGA3 0 0 0 1 1 128K words SA12 to SA15 SGA4 0 0 1 0 0 128K words SA16 to SA19 SGA5 0 0 1 0 1 128K words SA20 to SA23 SGA6 0 0 1 1 0 128K words SA24 to SA27 SGA7 0 0 1 1 1 128K words SA28 to SA31 SGA8 0 1 0 0 0 128K words SA32 to SA35 SGA9 0 1 0 0 1 128K words SA36 to SA39 SGA10 0 1 0 1 0 128K words SA40 to SA43 SGA11 0 1 0 1 1 128K words SA44 to SA47 SGA12 0 1 1 0 0 128K words SA48 to SA51 SGA13 0 1 1 0 1 128K words SA52 to SA55 SGA14 0 1 1 1 0 128K words SA56 to SA59 SGA15 0 1 1 1 1 128K words SA60 to SA63 SGA16 1 0 0 0 0 128K words SA64 to SA67 SGA17 1 0 0 0 1 128K words SA68 to SA71 SGA18 1 0 0 1 0 128K words SA72 to SA75 SGA19 1 0 0 1 1 128K words SA76 to SA79 SGA20 1 0 1 0 0 128K words SA80 to SA83 SGA21 1 0 1 0 1 128K words SA84 to SA87 SGA22 1 0 1 1 0 128K words SA88 to SA91 SGA23 1 0 1 1 1 128K words SA92 to SA95 SGA24 1 1 0 0 0 128K words SA96 to SA99 SGA25 1 1 0 0 1 128K words SA100 to SA103 SGA26 1 1 0 1 0 128K words SA104 to SA107 SGA27 1 1 0 1 1 128K words SA108 to SA111 SGA28 1 1 1 0 0 128K words SA112 to SA115 SGA29 1 1 1 0 1 128K words SA116 to SA119 SGA30 1 1 1 1 0 128K words SA120 to SA123 SGA31 1 1 1 1 1 128K words SA124 to SA127 MBM29LV652UE-90/12 Table 7 Description Query-unique ASCII string “QRY” Primary OEM Command Set 2h: AMD/FJ standard type Address for Primary Extended Table Alternate OEM Command Set (00h = not applicable) Address for Alternate OEM Extended Table VCC Min. (write/erase) D7-4: volt, D3-0: 100 mvolt VCC Max. (write/erase) D7-4: volt, D3-0: 100 mvolt VPP Min. voltage VPP Max. voltage Typical timeout per single byte/word write 2N µs Typical timeout for Min. size buffer write 2N µs Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical Device Size = 2N byte Flash Device Interface description Max. number of byte in multi-byte write = 2N Number of Erase Block Regions within device Erase Block Region 1 Information A0 to A6 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh Common Flash Memory Interface Code DQ0 to DQ15 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0027h 1Ch 0036h 1Dh 1Eh 1Fh 0000h 0000h 0004h 20h 0000h 21h 000Ah 22h 0000h 23h 0005h 24h 0000h 25h 0004h 26h 0000h 27h 28h 29h 2Ah 2Bh 2Ch 0017h 0001h 0000h 0000h 0000h 0001h 2Dh 2Eh 2Fh 30h 007Fh 0000h 0000h 0001h Description Erase Block Region 2 Information Query-unique ASCII string “PRI” Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0h = Required 1h = Not Required Erase Suspend 0h = Not Supported 1h = To Read Only 2h = To Read & Write Sector Protection 0h = Not Supported X = Number of sectors in per group Sector Temporary Unprotection 00h = Not Supported 01h = Supported Sector Protection Algorithm Number of Sector for Bank 2 00h = Not Supported Burst Mode Type 00h = Not Supported Page Mode Type 00h = Not Supported ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-4: volt, D3-0: 100 mvolt ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-4: volt, D3-0: 100 mvolt A0 to A6 31h 32h 33h 34h 40h 41h 42h 43h 44h 45h DQ0 to DQ15 46h 0002h 47h 0004h 48h 0001h 49h 4Ah 0004h 0000h 4Bh 0000h 4Ch 0000h 4Dh 00B5h 4Eh 00C5h 0000h 0000h 0000h 0000h 0050h 0052h 0049h 0031h 0031h 0001h 17 MBM29LV652UE-90/12 ■ FUNCTIONAL DESCRIPTION Read Mode The MBM29LV652UE has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”. Standby Mode There are two ways to implement the standby mode on the MBM29LV652UE devices, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ±0.3 V. Under this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ±0.3 V (CE = “H” or “L”). Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs are valid for read access. In the standby mode the outputs are in the high impedance state, independent of the OE input. Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29LV652UE data. This mode can be used effectively with an application requesting low power consumption such as handy terminals. To activate this mode, MBM29LV652UE automatically switch themselves to low power mode when MBM29LV652UE addresses remain stable during access fine of 150 ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level). Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically and MBM29LV652UE read-out the data for changed addresses. Output Disable With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. Autoselect The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. The Autoselect command may also be used to check the status of write-protected sectors (see Tables 4.1 and 4.2). This mode is functional over the entire temperature range of the devices. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON’T CARES except A0, A1, and A6. (See Table 2.) The manufacturer and device codes may also be read via the command register, for instances when the MBM29LV652UE is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 3. (Refer to Autoselect Command section.) 18 MBM29LV652UE-90/12 Word 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device identifier code (MBM29LV652UE = 22D7h).These two words are given in the tables 4.1 to 4.2. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See Tables 4.1 to 4.2.) In order to determine which sectors are write protected, A1 must be at VIH while running through the sector addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ0 (DQ0 = 1). Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Group Protection The MBM29LV652UE features hardware sector group protection. This feature will disable both program and erase operations in any combination of thirty two sector groups of memory. (See Table 6). The sector group protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sector groups unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V), CE = VIL and A0 = A6 = VIL, A1 = VIH. The sector group addresses (A21, A20, A19, A18, and A17) should be set to the sector to be protected. Table 5 defines the sector address for each of the one hundred twenty-eight (128) individual sectors, and tables 2 defines the sector group address for each of the thirty-two (32) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See figures 14 and 22 for sector group protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A21, A20, A19, A18, and A17) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A21, A20, A19, A18, and A17) are the desired sector group address will produce a logical “1” at DQ0 for a protected sector group. See Tables 4.1 and 4.2 for Autoselect codes. Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the MBM29LV652UE devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to Figures 15 and 23. This temporary sector group unprotect mode is disabled whenever the chip is in the Hidden ROM (Hi-ROM) mode. This area can not be programmed within this mode. Moreover once this area is programmed, it is always protected no matter in which mode. 19 MBM29LV652UE-90/12 RESET Hardware Reset Pin The MBM29LV652UE devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode “tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an additional “tRH” before it will allow read access. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Accelerated Program Operation MBM29LV652UE offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 50%. This function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. The system would use a fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode is not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the present sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the ACC pin returns the device to normal operation. Do not remove VACC from the ACC pin while programming. (See Figure 17) 20 MBM29LV652UE-90/12 ■ COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect data values or writing them in the improper sequence will reset the devices to the read mode. Table 3 defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the command register contents are altered. The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the address and the Autoselect command. Then the manufacture and device codes can be read from the address, and an actual data of memory cell can be read from the another address. Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read cycle from address XX01h returns the device code (MBM29LV652UE = 22D7h). All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address XX02h. Scanning the sector group addresses (A21, A20, A19, A18, and A17) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector group. The programming verification should be performed by verify sector group protection on the protected sector. (See Table 2.) To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and also to write the Autoselect command during the operation, execute it after writing Read/Reset command sequence. 21 MBM29LV652UE-90/12 Word Programming The devices are programmed on a word-by-word basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling), and DQ6 (Toggle Bit) or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 8, Hardware Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1” Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0” Only erase operations can convert “0”s to “1”s. Figure 18 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Chip Erase Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), and DQ6 (Toggle Bit). The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming) Figure 19 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Sector Erase Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first. After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin. 22 MBM29LV652UE-90/12 Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 3. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 127). Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), and DQ6 (Toggle Bit)or RY/BY. The sector erase begins after the “tTOW” time out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of Sector Erase Figure 19 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The addresses are “Don’t Care” when writting the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of “tSPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/ BY output pin will be at Hi-z and the DQ7 bit will be at logic “1” and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) 23 MBM29LV652UE-90/12 After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Extended Command (1) Fast Mode MBM29LV652UE has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to the Figure 24.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to the Figure 24.) (3) Extended Sector Group Protection In addition to normal sector group protection, the MBM29LV652UE has Extended Sector Group Protection as extended function. This function enable to protect sector group by forcing VID on RESET pin and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then, the sector group addresses pins (A21, A20, A19, A18, and A17) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other addresses pins), and write extended sector group protection command (60h). A sector group is typically protected in 250 µs. To verify programming of the protection circuitry, the sector group addresses pins (A21, A20, A19, A18, and A17) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h). Following the command write, a logical “1” at device output DQ0 will produce for protected sector in the read operation. If the output data is logical “0”, please repeat to write extended sector group protection command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. (Refer to the Figures 16 and 25.) (4) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98h) into the command register. Following the command write, a read cycle from specific address retrieves device information. Please note that output data of upper byte (DQ8 to DQ15) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary to write the read/reset command sequence into the register. (See Table 7.) 24 MBM29LV652UE-90/12 Hidden ROM (Hi-ROM) Region The Hi-ROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the Hi-ROM region is programmed, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The Hi-ROM region is 128 words in length. After the system has written the Enter Hi-ROM command sequence, it may read the Hidden ROM region by using device addresses A0 to A6 (A7 to A14 are “00”, A15 to A21 are don’t care). That is, the device sends only program command that would normally be sent to the address to the HiROM region. This mode of operation continues until the system issues the Exit Hi-ROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the address. Hidden ROM (Hi-ROM) Entry Command MBM29LV652UE has a Hidden ROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program is possible in this area until it is protected. However, once it is protected, it is impossible to unprotect, so please use this with caution. Hidden ROM area is 128words in length. Write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called as Hidden ROM mode when the Hidden ROM area appears. After the system has written the Enter Hi-ROM command sequence, it may read the Hidden ROM region by using device addresses A0 to A6 (A7 to A14 are “00”, A15 to A21 are don’t care). Read/program of the Hidden ROM area is possible during Hidden ROM mode. Write the Hidden ROM reset command sequence to exit the Hidden ROM mode. Hidden ROM (Hi-ROM) Program Command To program the data to the Hidden ROM area, write the Hidden ROM program command sequence during Hidden ROM mode. This command is same as the program command in the past except to write the command during Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. Hidden ROM (Hi-ROM) Protect Command There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup command(60h), set the sector address to select (A6, A1, A0) = (0,1,0) and Hidden ROM area and write the sector group protect command(60h) during the Hidden ROM mode. Same command sequence could be used because other then the Hidden ROM mode and that is does not apply high voltage to RESET pin, it is same as the extension sector group protect in the past. Please refer "Function Explanation Extended Command (3) Extentended Sector Group Protection" for details of extention sector group protect setting. The other is to apply high voltage (VID) to A9 and OE, specify the sector address to select (A6, A1, A0) = (0,1,0) and Hidden ROM area, and apply the write pulse during the Hidden ROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A1, A0) = (0,1,0) and the sector address to select the Hidden ROM area, and read. When "1" appears to DQ0, the protect setting is completed. "0" will appear to DQ0 if it is not protected. Please apply write pulse agian. Same command sequence could be used for the above method because other then the Hidden ROM mode, it is same as the sector group protect in the past. Please refer "Function Explanation Secor Group Protection" for details of sector group protect setting 25 MBM29LV652UE-90/12 Once it is protected, protection can not be cancelled, so please pay closest attention. Write Operation Status Detailed in Table 8 are all the status flags that can be used to check the status of the device for current mode operation. During sector erase, the part provides the status flags automatically to the I/O ports. The information on DQ2 is address sensitive. This means that if an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows the user to determine which sectors are erasing and which are not. Once erase suspend is entered, address sensitivity still applies. If the address of a non-erasing sector (that is, one available for read) is provided, then stored data can be read from the device. If the address of an erasing sector (that is, one unavailable for read) is applied, the device will output its status bits. Table 8 Hardware Sequence Flags DQ7 DQ6 DQ5 DQ3 DQ2 DQ7 Toggle 0 0 1 0 Toggle 0 1 Toggle* 1 1 0 0 Toggle Data Data Data Data Data DQ7 Toggle 0 0 1* Embedded Program Algorithm DQ7 Toggle 1 0 1 Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode 0 Toggle 1 1 N/A DQ7 Toggle 1 0 N/A Status Embedded Program Algorithm Embedded Erase Algorithm In Progress Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) *: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit. Notes: 1. DQ0 and DQ1 are reserve pins for future use. 2. DQ4 is Fujitsu internal use only. DQ7 Data Polling The MBM29LV652UE devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 20. For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. 26 MBM29LV652UE-90/12 For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the MBM29LV652UE data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See Table 8.) See Figure 9 for the Data Polling timing specifications and diagram. DQ6 Toggle Bit I The MBM29LV652UE also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause the DQ6 to toggle. See Figure 10 for the Toggle Bit I timing specifications and diagram. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the devices under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in Table 2. The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the DQ5 bit will indicate a “1”. Please note that this is not a device failure condition since the devices were incorrectly used. If this occurs, reset the device with command sequence. 27 MBM29LV652UE-90/12 DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See Table 8 : Hardware Sequence Flags. DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows: For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also Table 9 and Figure 11. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. Table 9 Toggle Bit Status DQ7 DQ6 DQ2 DQ7 Toggle 1 Erase 0 Toggle Toggle * Erase-Suspend Read (Erase-Suspended Sector) 1 1 Toggle DQ7 Toggle 1* Mode Program Erase-Suspend Program *: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit. 28 MBM29LV652UE-90/12 RY/BY Ready/Busy The MBM29LV652UE provide a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase commands. If the MBM29LV652UE is placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to Figures 12 and 13 for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC. Data Protection The MBM29LV652UE is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the devices automatically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (min). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (Min.). If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used. Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must be a logical zero while OE is a logical one. Power-up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power-up. 29 MBM29LV652UE-90/12 ■ ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Unit Min. Max. Tstg –55 +125 °C TA –40 +85° °C VIN, VOUT –0.5 VCC +0.5 V Power Supply Voltage (Note 1) VCC –0.5 +4.0 V A9, OE, ACC, and RESET (Note 2) VIN –0.5 +13.0 V VCCq –0.2 +7.0 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All Pins Except A9, OE, ACC and RESET (Note 1) Power Supply Voltage Notes: 1. Minimum DC voltage on input or l/O pins is −0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns. 2. Minimum DC input voltage on A9, OE, ACC and RESET pins is −0.5 V. During voltage transitions, A9, OE, ACC, and RESET pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN−VCC) does not exceed 9.0 V. Maximum DC input voltage on A9, OE, ACC, and RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Ambient Temperature (-90/-12) Power Supply Voltage (VCC) (-90) Power Supply Voltage (VCCq) Note: (-12) (-90/-12) TA VCC VCCq Value Unit Min. Max. –40 +85 °C +3.0 +3.6 V +2.7 +3.6 V +2.7 +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 30 MBM29LV652UE-90/12 ■ MAXIMUM OVERSHOOT/UNDERSHOOT 20 ns 20 ns +0.6 V –0.5 V –2.0 V 20 ns Figure 1 Maximum Undershoot Waveform 20 ns VCC +2.0 V VCC +0.5 V +2.0 V 20 ns 20 ns Figure 2 Maximum Overshoot Waveform 1 20 ns +14.0 V +13.0 V VCC +0.5 V 20 ns 20 ns Note: This waveform is applied for A9, OE, ACC, and RESET. Figure 3 Maximum Overshoot Waveform 2 31 MBM29LV652UE-90/12 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Symbol Parameter Description Test Conditions Max. Unit ILI Input Leakage Current VIN = VSS to VCC, VCC = VCC Max., VCCq = VCCq Max. –1.0 +1.0 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max., VCCq = VCCq Max. –1.0 +1.0 µA ILIT A9, OE, RESET Inputs Leakage Current VCC = VCC Max., A9, OE, RESET = 12.5 V — 35 µA IACC ACC Accelerated Program Current VCC = VCC Max., ACC = VACC Max. — 20 mA CE = VIL, OE = VIH, VCC = VCC Max., VCCq = VCCq Max., f = 5 MHz — 16 mA CE = VIL, OE = VIH, VCC = VCC Max., VCCq = VCCq Max., f = 1 MHz — 7 mA ICC1 VCC Active Current (Note 1) ICC2 VCC Active Current (Note 2) CE = VIL, OE = VIH, VCC = VCC Max., VCCq = VCCq Max. — 40 mA ICC3 VCC Current (Standby) VCC = VCC Max., VCCq = VCCq Max., CE = VCC ±0.3 V, RESET = VCC ±0.3 V — 5 µA ICC4 VCC Current (Standby, RESET) VCC = VCC Max., VCCq = VCCq Max., RESET = VSS ±0.3 V — 5 µA ICC5 VCC Current (Automatic Sleep Mode) (Note 3) VCC = VCC Max., VCCq = VCCq Max., CE = VSS ±0.3 V, RESET = VCC ±0.3 V, VIN = VCC ±0.3 V or VSS ±0.3 V — 5 µA VIL Input Low Level — –0.5 0.6 V VIH Input High Level — 2.0 VCC + 0.5 V Voltage for Program Acceleration — 11.5 12.5 V VID Voltage for Autoselect, Sector Protection (A9, OE, RESET) (Note 4) — 11.5 12.5 V VOL Output Low Voltage Level IOL = 4.0 mA, VCC = VCC Min., VCCq = VCCq Min. — 0.45 V IOH = –2.0 mA, VCC = VCC Min., VCCq = VCCq Min. 2.4 — V VCCq – 0.4 — V 2.3 2.5 V VACC VOH1 Output High Voltage Level IOH = –100 µA, VCC Min., VCCq = VCCq Min. VOH2 VLKO Notes: 1. 2. 3. 4. 32 Min. Low VCC Lock-Out Voltage — The lCC current listed includes both the DC operating current and the frequency dependent component. lCC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when address remain stable for 150 ns. Applicable for only VCC applying. MBM29LV652UE-90/12 2. AC Characteristics • Read Only Operations Characteristics Parameter Symbols Description JEDEC Standard tAVAV tRC Read Cycle Time tAVQV tACC tELQV Test Setup 90 (Note) 12 (Note) Unit — Min. 90 120 ns Address to Output Delay CE = VIL OE = VIL Max. 90 120 ns tCE Chip Enable to Output Delay OE = VIL Max. 90 120 ns tGLQV tOE Output Enable to Output Delay — Max. 35 50 ns tEHQZ tDF Chip Enable to Output HIGH-Z — Max. 30 30 ns tGHQZ tDF Output Enable to Output HIGH-Z — Max. 30 30 ns tAXQX tOH Output Hold Time From Address, CE or OE, Whichever Occurs First — Min. 0 0 ns — tREADY RESET Pin Low to Read Mode — Max. 20 20 µs Note: Test Conditions: Output Load: 1 TTL gate and 30 pF (MBM29LV652UE-90) 1 TTL gate and 100 pF (MBM29LV652UE-12) Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V 3.3 V IN3064 or Equivalent 2.7 kΩ Device Under Test 6.2 kΩ CL Diodes = IN3064 or Equivalent Figure 4 Test Conditions 33 MBM29LV652UE-90/12 • Write (Erase/Program) Operations Parameter Symbols Description 90 12 Unit Min. 90 120 ns Address Setup Time Min. 0 0 ns tAH Address Hold Time Min. 45 50 ns tDVWH tDS Data Setup Time Min. 35 50 ns tWHDX tDH Data Hold Time Min. 0 0 ns — tOES Output Enable Setup Time Min. 0 0 ns Read Min. 0 0 ns — tOEH Output Enable Hold Time Toggle and Data Polling Min. 10 10 ns JEDEC Standard tAVAV tWC Write Cycle Time tAVWL tAS tWLAX tGHWL tGHWL Read Recover Time Before Write Min. 0 0 ns tGHEL tGHEL Read Recover Time Before Write Min. 0 0 ns tELWL tCS CE Setup Time Min. 0 0 ns tWLEL tWS WE Setup Time Min. 0 0 ns tWHEH tCH CE Hold Time Min. 0 0 ns tEHWH tWH WE Hold Time Min. 0 0 ns tWLWH tWP Write Pulse Width Min. 35 50 ns tELEH tCP CE Pulse Width Min. 35 50 ns tWHWL tWPH Write Pulse Width High Min. 30 30 ns tEHEL tCPH CE Pulse Width High Min. 30 30 ns tWHWH1 tWHWH1 Word Programming Operation Typ. 16 16 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 1) Typ. 1 1 s — tVCS VCC Setup Time Min. 50 50 µs — tVIDR Rise Time to VID (Note 2) Min. 500 500 ns — tVACCR Rise Time to VACC (Note 3) Min. 500 500 ns — tVLHT Voltage Transition Time (Note 2) Min. 4 4 µs — tWPP Write Pulse Width (Note 2) Min. 100 100 µs — tOESP OE Setup Time to WE Active (Note 2) Min. 4 4 µs — tCSP CE Setup Time to WE Active (Note 2) Min. 4 4 µs — tRB Recover Time From RY/BY Min. 0 0 ns — tRP RESET Pulse Width Min. 500 500 ns (Continued) 34 MBM29LV652UE-90/12 (Continued) Parameter Symbols Description JEDEC Standard — tRH — 90 12 Unit RESET Hold Time Before Read Min. 200 200 ns tBOSY Program/Erase Valid to RY/BY Delay Max. 90 90 ns — tEOE Delay Time from Embedded Output Enable Max. 90 120 ns — tTOW Erase Time-out Time Min. 50 50 µs — tSPD Erase Suspend Transition Time Max. 20 20 µs Notes: 1. This does not include the preprogramming time. 2. This timing is for Sector Group Protection operation. 3. This timing is for Accelerated Program operation. 35 MBM29LV652UE-90/12 ■ ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Unit Comments 10 s Excludes programming time prior to erasure 16 360 µs Excludes system-level overhead — — 200 s Excludes system-level overhead 100,000 — — cycle Min. Typ. Max. Sector Erase Time — 1 Programming Time — Chip Programming Time Erase/Program Cycle — ■ PIN CAPACITANCE Parameter Symbol Parameter Description Typ. Max. Unit 6 7.5 pF 8.5 12 pF CIN Input Capacitance VIN = 0 COUT Output Capacitance VOUT = 0 CIN2 Control Pin Capacitance VIN = 0 8 10 pF CIN3 ACC Pin Capacitance VIN = 0 15 20 pF Note: Test conditions TA = 25°C, f = 1.0 MHz 36 Test Setup MBM29LV652UE-90/12 ■ TIMING DIAGRAM • Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Must Be Steady Will Be Steady May Change from H to L Will Be Changing from H to L May Change from L to H Will Be Changing from L to H “H” or “L” Any Change Permitted Changing State Unknown Does Not Apply Center Line is HighImpedance “Off” State tRC Addresses Addresses Stable tACC CE tOE tDF OE tOEH WE tCE Outputs High-Z Figure 5.1 tOH Output Valid High-Z Read Operation Timing Diagram 37 MBM29LV652UE-90/12 tRC Addresses Addresses Stable tACC CE tRH tRP tRH tCE RESET tOH High-Z Outputs Figure 5.2 38 Output Valid Hardware Reset/Read Operation Timing Diagram MBM29LV652UE-90/12 Data Polling 3rd Bus Cycle Addresses XXXh tWC PA tAS PA tRC tAH CE tCH tCS tCE OE tGHWL tWP tWPH tOE tWHWH1 WE tDF tDS tOH tDH A0h Data Notes: 1. 2. 3. 4. 5. PD DQ7 DOUT DOUT PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. Figure 6 Alternate WE Controlled Program Operation Timing Diagram 39 MBM29LV652UE-90/12 3rd Bus Cycle Addresses Data Polling PA XXXh tWC tAS PA tAH WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS tDH Data Notes: 1. 2. 3. 4. 5. PD DQ7 D OUT PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. Figure 7 40 A0h Alternate CE Controlled Program Operation Timing Diagram MBM29LV652UE-90/12 Addresses XXXh XXXh tWC tAS XXXh XXXh XXXh SA * tAH CE tCS tCH OE tGHWL tWP tWPH WE tDS AAh Data tDH 55h 80h AAh 55h 10h/ 30h tVCS V CC * : SA is the sector address for Sector Erase. Addresses = XXXh for Chip Erase. Figure 8 Chip/Sector Erase Operation Timing Diagram 41 MBM29LV652UE-90/12 CE t CH t OE t DF OE t OEH WE t CE * Data DQ7 DQ7 = Valid Data DQ7 High-Z t WHWH1 or 2 Data DQ0 to DQ6 DQ0 to DQ6 = Output Flag t BUSY DQ0 to DQ6 Valid Data High-Z t EOE RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation.) Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram CE tOEH WE tOES OE * tDH DQ6 Data (DQ0 to DQ7) DQ6 = Toggle DQ6 = Toggle DQ6 = Stop Toggling DQ0 to DQ7 Data Valid tOE * : DQ6 = Stops toggling. (The device has completed the Embedded operation.) Figure 10 42 Toggle Bit I during Embedded Algorithm Operation Timing Diagram MBM29LV652UE-90/12 Enter Embedded Erasing Erase Suspend WE Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Toggle DQ2 and DQ6 with OE or CE Note: DQ2 is read from the erase-suspended sector. Figure 11 DQ2 vs. DQ6 CE The rising edge of the last write pulse WE Entire programming or erase operations RY/BY t BUSY Figure 12 RY/BY Timing Diagram during Program/Erase Operation Timing Diagram WE RESET tRP t RB RY/BY tREADY Figure 13 RESET,RY/BY Timing Diagram 43 MBM29LV652UE-90/12 A21, A20, A19 A18, A17 SGAX SGAY A0 A1 A6 VID 3V A9 tVLHT VID 3V OE tVLHT tVLHT tVLHT tWPP WE tOESP tCSP CE Data 01h tVCS tOE VCC SGAX = Sector Group Address for initial sector SGAY = Sector Group Address for next sector Figure 14 44 Sector Group Protection Timing Diagram MBM29LV652UE-90/12 VCC tVIDR tVCS tVLHT VID 3V 3V RESET CE WE tVLHT Program or Erase Command Sequence tVLHT RY/BY Unprotection period Figure 15 Temporary Sector Group Unprotection Timing Diagram 45 MBM29LV652UE-90/12 VCC tVCS tVLHT RESET tVIDR tWC Add tWC SGAX SGAX SGAY A0 A1 A6 CE OE TIME-OUT tWP WE Data 60h 60h 40h 01h tOE SGAX: Sector Group Address to be protected SGAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 µs (Min.) Figure 16 46 Extended Sector Group Protection Timing Diagram 60h MBM29LV652UE-90/12 VCC tVACCR tVCS tVLHT VACC 3V 3V ACC CE WE tVLHT Program or Erase Command Sequence tVLHT Acceleration period Figure 17 Accelerated Program Timing Diagram 47 MBM29LV652UE-90/12 ■ FLOW CHART EMBEDDED ALGORITHMS Start Write Program Command Sequence (See below) Data Polling No Verify Data ? Embeded Program Algorithm in progress Yes Increment Address No Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): XXXh/AAh XXXh/55h XXXh/A0h Program Address/Program Data Figure 18 48 Embedded ProgramTM Algorithm MBM29LV652UE-90/12 EMBEDDED ALGORITHMS Start Write Erase Command Sequence (See below) Data Polling Embeded Program Algorithm in progress No Data = FFh ? Yes Erasure Completed Chip Erase Command Sequence (Address/Command): Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): XXXh/AAh XXXh/AAh XXXh/55h XXXh/55h XXXh/80h XXXh/80h XXXh/AAh XXXh/AAh XXXh/55h XXXh/55h XXXh/10h Sector Address/30h Sector Address/30h Additional sector erase commands are optional. Sector Address/30h Figure 19 Embedded EraseTM Algorithm 49 MBM29LV652UE-90/12 Start Read Byte (DQ 7 to DQ0) Addr. = VA DQ7 = Data? VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = Any of the sector addresses within the sector not being protected during chip erase Yes No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? Yes No Fail Pass Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 20 50 Data Polling Algorithm MBM29LV652UE-90/12 Start Read DQ7 to DQ0 *1 Read DQ7 to DQ0 Toggle Bit = Toggle? No Yes No DQ5 = 1? Yes *1,*2 Read (DQ7 to DQ0) Twice Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete *1: Reset toggle bit twice to determine whether or not it is toggle. *2: Recheck toggle bit because it may stop toggle as DQ5 changes to “1”. Figure 21 Toggle Bit Algorithm 51 MBM29LV652UE-90/12 Start Setup Sector Group Addr. (A21, A20, A19, A18, A17) PLSCNT = 1 OE = VID, A9 = VID, A6 = CE = VIL, RESET = VIH A0 = VIL, A1 = VIH Activate WE Pulse Time out 100 µs Increment PLSCNT WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Group (Addr. = SGA, A0 = VIL, A1 = VIH, A6 = VIL) No No PLSCNT = 25? Yes Data = 01h? Yes Yes Remove VID from A9 Write Reset Command Protect Another Sector Group ? No Device Failed Remove VID from A9 Write Reset Command Sector Group Protection Completed Figure 22 52 Sector Group Protection Algorithm MBM29LV652UE-90/12 Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Group Unprotection Completed *2 *1: All protected sector groups are unprotected. *2: All previously protected sector groups are protected once again. Figure 23 Temporary Sector Group Unprotection Algorithm 53 MBM29LV652UE-90/12 Start RESET = VID Wait to 4 µs Device is Operating in Temporary Sector Group Unprotection Mode No Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h PLSCNT = 1 To Sector Group Protection Write SGA/60h (A0 = VIL, A1 = VIH, A6 = VIL) Time Out 250 µs Increment PLSCNT To Verify Sector Group Protection Write SGA/40h (A0 = VIL, A1 = VIH, A6 = VIL) Setup Next Sector Group Address Read from Sector Group Address (A0 = VIL, A1 = VIH, A6 = VIL) No No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Data = 01h? Yes Yes Protection Other Sector Group? No Device Failed Remove VID from RESET Write Reset Command Sector Group Protection Completed Figure 24 54 Extended Sector Group Protection Algorithm MBM29LV652UE-90/12 FAST MODE ALGORITHM Start XXXh/AAh Set Fast Mode XXXh/55h XXXh/20h XXXh/A0h Program Address/Program Data Data Polling Device Verify Data? No In Fast Program Yes Increment Address No Last Address ? Yes Programming Completed XXXh/90h Reset Fast Mode XXXh/F0h Figure 25 Embedded ProgramTM Algorithm for Fast Mode 55 MBM29LV652UE-90/12 ■ ORDERING INFORMATION Standard Products Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM29LV652U E 90 TN PACKAGE TYPE PBT=63ball Fine pitch Ball Gind Array Package (FBGA) Standard Pinout SPEED OPTION See Product Selector Guide DEVICE REVISION DEVICE NUMBER/DESCRIPTION MBM29LV652U 64 Mega-bit (4M × 16-Bit) CMOS Flash Memory 3.0 V-only Read, Program, and Erase 56 MBM29LV652UE-90/12 ■ PACKAGE DIMENSIONS 63-pin plastic FBGA (I) (BGA-63P-M02) +0.15 11.00±0.10(.433±.004) 1.05 –0.10 (8.80(.346)) +.006 .041 –.004 (Mounting height) 0.38±0.10 (.015±.004) (Stand off) (7.20(.283)) (5.60(.220)) 0.80(.031)TYP 8 7 6 10.00±0.10 (.394±.004) 5 (4.00(.157)) (5.60(.220)) 4 3 2 1 M INDEX AREA L K J H G F E D C B A INDEX BALL 63-Ø0.45±0.05 (63-Ø0.18±.002) 0.08(.003) M 0.10(.004) C 1999 FUJITSU LIMITED B63002S-1C-1 Dimensions in mm (inches) 57 MBM29LV652UE-90/12 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0012 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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