SN74LVC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES224C – APRIL 1999 – REVISED FEBRUARY 2000 D D D D EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Ioff Feature Supports Partial-Power-Down Mode Operation Supports 5-V VCC Operation Package Options Include Plastic Small-Outline Transistor (DBV, DCK) Packages DBV OR DCK PACKAGE (TOP VIEW) OE A GND 1 5 VCC 4 Y 2 3 description This single bus buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G126 is a single bus driver/line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74LVC1G126 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS OE A OUTPUT Y H H H H L L L X Z logic symbol† OE A 1 EN 2 4 Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1 OE A 2 4 Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PRODUCT PREVIEW To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. SN74LVC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES224C – APRIL 1999 – REVISED FEBRUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C PRODUCT PREVIEW † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) VCC VIH Supply voltage High level input voltage High-level Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 1.5 UNIT V 0.65 × VCC 1.7 V 2 0.7 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 0.7 VIL Low level input voltage Low-level VI VO Input voltage 0 5.5 V Output voltage 0 VCC –4 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 1.65 V VCC = 2.3 V IOH High-level output current VCC = 3 V VCC = 4.5 V VCC = 1.65 V VCC = 2.3 V IOL ∆t/∆v Low-level output current Input transition rise or fall rate VCC = 3 V 0.8 V 0.3 × VCC –8 –16 mA –24 –32 4 8 16 mA 24 VCC = 4.5 V VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 32 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 10 20 ns/V 5 TA Operating free-air temperature –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES224C – APRIL 1999 – REVISED FEBRUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS IOH = –100 mA IOH = –4 mA VCC MIN 1.65 V to 5.5 V 1.65 V VCC–0.1 1.2 2.3 V 1.9 IOH = –8 mA IOH = –16 mA VOH 3.8 0.1 1.65 V 0.45 2.3 V 0.3 IOL = 16 mA 0.4 3V IOL = 24 mA 0.55 ±5 mA 0 ±10 mA 3.6 V 10 mA 1.65 V to 5.5 V 10 mA 3 V to 5.5 V 500 mA VI = 5.5 V or GND 0 to 5.5 V Ioff IOZ VI or VO = 5.5 V VO = 0 to 5.5 V ICC ∆ICC VI = 5.5 V or GND, One input at VCC – 0.6 V, Ci VI = VCC or GND IO = 0 Other inputs at VCC or GND V 0.55 4.5 V IOL = 32 mA A or OE inputs V 1.65 V to 5.5 V IOL = 4 mA IOL = 8 mA UNIT 2.3 4.5 V IOH = –32 mA IOL = 100 mA II MAX 2.4 3V IOH = –24 mA VOL TYP† 3.3 V pF switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 4) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V FROM (INPUT) TO (OUTPUT) tpd A Y ns ten OE Y ns tdis OE Y ns PARAMETER MIN MAX MIN MAX MIN MAX MIN UNIT MAX operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V TYP VCC = 2.5 V TYP f = 10 MHz POST OFFICE BOX 655303 VCC = 3.3 V TYP VCC = 5 V TYP UNIT pF • DALLAS, TEXAS 75265 3 PRODUCT PREVIEW PARAMETER SN74LVC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES224C – APRIL 1999 – REVISED FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 VCC/2 0V VCC/2 VCC/2 0V tPLH tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC/2 tPZL VCC Input VCC Output Control VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output VCC/2 0V 0V tsu PRODUCT PREVIEW VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES224C – APRIL 1999 – REVISED FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC VCC/2 VCC/2 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th VCC/2 VCC/2 0V VCC/2 VCC/2 0V tPLH tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC/2 tPZL VCC Input VCC Output Control VOLTAGE WAVEFORMS SETUP AND HOLD TIMES PRODUCT PREVIEW VCC Data Input Output VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74LVC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES224C – APRIL 1999 – REVISED FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V From Output Under Test 6V Open S1 500 Ω GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 3V 3V Timing Input Input 1.5 V 0V 1.5 V 0V tsu PRODUCT PREVIEW 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input 1.5 V 1.5 V 3V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control 1.5 V 0V tPLZ tPZL 3V Input 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH VOH Output 3V Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V 1.5 V VOH – 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES224C – APRIL 1999 – REVISED FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 5 V ± 0.5 V S1 500 Ω From Output Under Test 11 V Open GND CL = 50 pF (see Note A) 500 Ω LOAD CIRCUIT TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 11 V GND VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 0V VCC Data Input VCC/2 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL tPHL VCC/2 VCC Output Control Output Waveform 1 S1 at 11 V (see Note B) tPLH VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 0V tPLZ tPZL 5.5 V VCC/2 Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH VOH Output VCC/2 PRODUCT PREVIEW VCC/2 Input th VCC/2 VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 4. 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