TI SN74AVC126

SN74AVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES255B – APRIL 1999 – REVISED DECEMBER 2005
FEATURES
•
•
•
•
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC™ (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without Speed
Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of ±24 mA
at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
•
•
A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows
typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At
the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a
high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family
Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry
Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
- Output Voltage - V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
V
V
OL
- Output Voltage - V
2.8
0.4
VCC = 3.3 V
VCC = 2.5 V
0.4
0
17
34
51
68 85 102 119
IOL - Output Current - mA
136
153
170
VCC = 1.8 V
-160 -144 -128 -112
-96
-80
-64 -48
-32
-16
0
IOH - Output Current - mA
Figure 1. Output Voltage vs Output Current
This quadruple bus buffer gate is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
The SN74AVC126 features independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC126 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC, DOC are trademarks of Texas Instruments.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 1999–2005, Texas Instruments Incorporated
PRODUCT PREVIEW
DESCRIPTION
SN74AVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES255B – APRIL 1999 – REVISED DECEMBER 2005
TERMINAL ASSIGNMENTS
D, DGV, OR PW PACKAGE
(TOP VIEW)
1OE
1A
1Y
2OE
2A
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4OE
4A
4Y
3OE
3A
3Y
FUNCTION TABLE
(EACH BUFFER)
INPUTS
PRODUCT PREVIEW
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
LOGIC SYMBOL(1)
1OE
1A
2OE
2A
3OE
3A
4OE
4A
(1)
1
EN
1
3
2
4
6
5
10
8
9
13
11
12
1Y
2Y
3Y
4Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1A
2OE
2A
2
1
2
3OE
3
1Y
4
5
3A
4OE
6
2Y
4A
10
9
8
3Y
13
12
11
4Y
SN74AVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES255B – APRIL 1999 – REVISED DECEMBER 2005
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range
–0.5
4.6
V
–0.5
4.6
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
D package
Tstg
(1)
(2)
(3)
(4)
Package thermal impedance (4)
Storage temperature range
86
DGV package
127
PW package
113
–65
150
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
The package thermal impedance is calculated in accordance with JESD 51.
PRODUCT PREVIEW
θJA
V
3
SN74AVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES255B – APRIL 1999 – REVISED DECEMBER 2005
Recommended Operating Conditions (1)
VCC
Supply voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VIH
High-level input voltage
0.65 × VCC
VCC = 1.65 V to 1.95 V
0.65 × VCC
VCC = 3 V to 3.6 V
Low-level input voltage
2
GND
VCC = 1.4 V to 1.6 V
0.35 × VCC
VCC = 1.65 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
Input voltage
VO
Output voltage
PRODUCT PREVIEW
IOHS
Static high-level output current (2)
0.8
0
3.6
Active state
0
VCC
3-state
0
3.6
VCC = 1.4 V to 1.6 V
–2
VCC = 1.65 V to 1.95 V
–4
VCC = 2.3 V to 2.7 V
–8
VCC = 3 V to 3.6 V
Static low-level output current (2)
IOLS
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
(2)
4
V
V
mA
–12
VCC = 1.4 V to 1.6 V
2
VCC = 1.65 V to 1.95 V
4
VCC = 2.3 V to 2.7 V
8
VCC = 3 V to 3.6 V
∆t/∆v
V
0.7
VCC = 3 V to 3.6 V
VI
V
1.7
VCC = 1.2 V
VIL
V
VCC
VCC = 1.4 V to 1.6 V
VCC = 2.3 V to 2.7 V
UNIT
mA
12
VCC = 1.4 V to 3.6 V
–40
5
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH
vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006,
and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009.
SN74AVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES255B – APRIL 1999 – REVISED DECEMBER 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
1.4 V to 3.6 V
IOHS = –2 mA,
VIH = 0.91 V
1.4 V
IOHS = –4 mA,
VIH = 1.07 V
1.65 V
1.2
IOHS = –8 mA,
VIH = 1.7 V
2.3 V
1.75
IOHS = –12 mA,
VIH = 2 V
3V
2.3
IOLS = 100 µA
MAX
UNIT
VCC – 0.2
1.05
V
1.4 V to 3.6 V
0.2
IOLS = 2 mA,
VIL = 0.49 V
1.4 V
0.4
IOLS = 4 mA,
VIL = 0.57 V
1.65 V
0.45
IOLS = 8 mA,
VIL = 0.7 V
2.3 V
0.55
IOLS = 12 mA,
VIL = 0.8 V
3V
0.7
VI = VCC or GND
3.6 V
±2.5
µA
Ioff
VI or VO = 3.6 V
0
±10
µA
IOZ
VO = VCC or GND
3.6 V
±12.5
µA
ICC
VI = VCC or GND,
3.6 V
40
µA
VOL
II
Control inputs
IO = 0
2.5 V
Control inputs
Ci
3.3 V
VI = VCC or GND
(1)
pF
2.5 V
Data inputs
Co
V
PRODUCT PREVIEW
VOH
MIN TYP (1)
VCC
3.3 V
Outputs
2.5 V
VO = VCC or GND
pF
3.3 V
Typical values are measured at TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 5)
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ns
ten
OE
Y
ns
tdis
OE
Y
ns
PARAMETER
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance per buffer
TEST CONDITIONS
CL = 0,
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
UNIT
pF
5
SN74AVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES255B – APRIL 1999 – REVISED DECEMBER 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 15 pF
(see Note A)
2 kΩ
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC
VCC/2
VCC/2
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
PRODUCT PREVIEW
Data
Input
VCC/2
VCC/2
0V
VCC/2
VCC/2
0V
tPLH
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC/2
tPZL
VCC
Input
VCC
Output
Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VOH
VCC/2
VOH − 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
6
SN74AVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES255B – APRIL 1999 – REVISED DECEMBER 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC/2
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VCC/2
VCC/2
0V
tPLH
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC/2
tPZL
VCC
Input
VCC
Output
Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
VCC/2
PRODUCT PREVIEW
Timing
Input
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
7
SN74AVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES255B – APRIL 1999 – REVISED DECEMBER 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC
VCC/2
VCC/2
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
PRODUCT PREVIEW
0V
VCC/2
VCC/2
0V
tPLH
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC/2
tPZL
VCC
Input
VCC
Output
Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
8
SN74AVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES255B – APRIL 1999 – REVISED DECEMBER 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
GND
CL = 30 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
500 Ω
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
Input
VCC/2
VCC/2
0V
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
VCC/2
VCC
VCC/2
0V
Output
Control
VCC/2
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
VOL + 0.3 V
VOL
tPZH
VOH
Output
PRODUCT PREVIEW
Data
Input
Output
Waveform 2
S1 at GND
(see Note B)
tPHZ
VOH
VCC/2
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
9
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN74AVC126D
PREVIEW
SOIC
D
14
50
TBD
Call TI
Call TI
SN74AVC126DGV
PREVIEW
TVSOP
DGV
14
125
TBD
Call TI
Call TI
SN74AVC126DGVR
PREVIEW
TVSOP
DGV
14
2000
TBD
Call TI
Call TI
SN74AVC126DR
PREVIEW
SOIC
D
14
2500
TBD
Call TI
Call TI
SN74AVC126PW
PREVIEW
TSSOP
PW
14
90
TBD
Call TI
Call TI
SN74AVC126PWR
PREVIEW
TSSOP
PW
14
2000
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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Amplifiers
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amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
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Digital Control
Medical
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Wireless
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www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
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www.ti.com/opticalnetwork
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www.ti.com/video
www.ti.com/wireless
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