ADS1158 AD S1 158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 16-Channel, 16-Bit Analog-to-Digital Converter FEATURES DESCRIPTION • • • • • • • • • The ADS1158 is a 16-channel (multiplexed), low-noise, 16-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC) that provides single-cycle settled data at channel scan rates from 1.8k to 23.7k samples per second (SPS) per channel. A flexible input multiplexer accepts combinations of eight differential or 16 single-ended inputs with a full-scale differential range of 5V or true bipolar range of ±2.5V when operating with a 5V reference. The fourth-order delta-sigma modulator is followed by a fifth-order sinc digital filter optimized for low-noise performance. 1 23 • • • • • • • • 16 Bits, No Missing Codes Fixed-Channel or Automatic Channel Scan Fixed-Channel Data Rate: 125kSPS Auto-Scan Data Rate: 23.7kSPS/Channel Single-Conversion Settled Data 16 Single-Ended or 8 Differential Inputs Unipolar (+5V) or Bipolar (±2.5V) Operation 0.3LSB (INL) DC Stability: 0.02µV/°C Offset Drift, 0.4ppm/°C Gain Drift Open-Sensor Detection Conversion Control Pin Multiplexer Output for External Signal Conditioning On-Chip Temperature, Reference, Offset, Gain, and Supply Voltage Readback 42mW Power Dissipation Standby, Sleep, and Power-Down Modes Eight General-Purpose Inputs/Outputs (GPIO) 32.768kHz Crystal Oscillator or External Clock APPLICATIONS • • • • • The differential output of the multiplexer is accessible to allow signal conditioning before the input of the ADC. Internal system monitor registers provide supply voltage, temperature, reference voltage, gain, and offset data. An onboard PLL generates the system clock from a 32.768kHz crystal, or can be overridden by an external clock source. A buffered system clock output (15.7MHz) is provided to drive a microcontroller or additional converters. Serial digital communication is handled via an SPI™-compatible interface. A simple command word structure controls channel configuration, data rates, digital I/O, monitor functions, etc. Programmable sensor bias current sources can be used to bias sensors or verify sensor integrity. Medical, Avionics, and Process Control Machine and System Monitoring Fast Scan Multi-Channel Instrumentation Industrial Systems Test and Measurement Systems The ADS1158 operates from a unipolar +5V or bipolar ±2.5V analog supply and a digital supply compatible with interfaces ranging from 2.7V to 5.25V. The ADS1158 is available in a QFN-48 package. AVDD DVDD VREF Internal Monitoring GPIO[7:0] ADS1158 GPIO Digital Filter SPI Interface CS DRDY SCLK DIN DOUT Oscillator Control START RESET PWDN Analog Inputs ¼ 1 16-Bit ADC 16:1 Analog Input MUX 16 AINCOM AVSS MUX OUT ADC IN Ext CLK In/Out 32.768kHz DGND 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range, unless otherwise noted. (1) ADS1158 UNIT AVDD to AVSS –0.3 to +5.5 V AVSS to DGND –2.8 to +0.3 V DVDD to DGND –0.3 to +5.5 V 100, momentary mA 10, continuous mA AVSS – 0.3 to AVDD + 0.3 V Input current Input current Analog input voltage Digital input voltage to DGND –0.3 to DVDD + 0.3 V +150 °C Operating temperature range –40 to +105 °C Storage temperature range –60 to +150 °C Maximum junction temperature (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 ELECTRICAL CHARACTERISTICS All specifications at TA = –40°C to +105°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREF = +4.096V, and VREFN = –2.5V, unless otherwise noted. ADS1158 PARAMETER CONDITIONS MIN TYP MAX UNIT AVDD + 100mV V Analog Multiplexer Inputs Absolute input voltage AIN0–AIN15, AINCOM with respect to DGND AVSS – 100mV 80 Ω fIN = 1kHz –110 dB SBCS[1:0] = 01 1.5 SBCS[1:0] = 11 24 On-channel resistance Crosstalk Sensor bias (current source) 1.5µA:24µA ratio error µA 1 % ADC Input Full-scale input voltage (VIN = ADCINP – ADCINN) Absolute input voltage (ADCINP, ADCINN) ±1.06VREF AVSS – 100mV Differential input impedance V AVDD + 100mV 65 V kΩ System Performance Resolution No missing codes 16 Data rate, fixed-channel mode Data rate, auto-scan mode 125 1.805 Integral nonlinearity (INL) (1) Offset error Bits 1.953 Differential input Chopping on Offset drift Shorted inputs –1 Shorted inputs kSPS 23.739 kSPS 0.3 1 LSB (2) –0.5 (3) 0 LSB µV/°C 1 Gain error 0.1 Gain drift 2 ppm/°C 0.6 LSB (PP) 100 dB Noise Common-mode rejection Power-supply rejection fCM = 60Hz AVDD, AVSS DVDD 0.5 85 fPS = 60Hz % dB 95 Voltage Reference Input Reference input voltage AVDD – AVSS V Negative reference input (VREFN) (VREF = VREFP – VREFN) AVSS – 0.1V 0.5 VREFP – 0.5 V Positive reference input (VREFP) VREFN + 0.5 AVDD + 0.1V Reference input impedance 4.096 40 V kΩ System Parameters External reference reading error 1 3 Analog supply reading error 1 5 Temperature sensor reading (1) (2) (3) Voltage TA = +25°C Coefficient % % 168 mV 394 µV/°C Best straight line fit method. FSR = Full-scale range = 2.13VREF. Systematic –0.5LSB in reading code. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 3 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –40°C to +105°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREF = +4.096V, and VREFN = –2.5V, unless otherwise noted. ADS1158 PARAMETER CONDITIONS MIN TYP MAX UNIT 0.7DVDD DVDD V Digital Input/Output VIH Logic levels VIL DGND 0.3DVDD V VOH IOH = 2mA 0.8DVDD DVDD V VOL IOL = 2mA DGND 0.2DVDD V 10 µA MHz Input leakage Master clock input (CLKIO) Crystal oscillator (see Crystal Oscillator section) VIN = DVDD, GND Frequency 0.1 16 Duty cycle 40 60 % Crystal frequency 32.768 kHz Clock output frequency 15.729 MHz Start-up time (clock output valid) 150 Clock output duty cycle ms 40 60 % DVDD 2.7 5.25 V AVSS –2.6 0 V AVDD AVSS + 4.75 AVSS + 5.25 V 0.6 mA Power Supply DVDD supply current AVDD, AVSS supply current Power dissipation (4) (5) 4 External clock operation 0.25 Internal oscillator operation, clock output disabled 0.04 mA Internal oscillator operation, clock output enabled (4) 1.4 mA Power-down (5) 1 25 µA Converting 8.2 12 mA Standby 5.6 mA Sleep 2.1 Power-down 2 200 mA µA Converting 42 62 mW Standby 29 mW Sleep 11 mW Power-down 14 µW CLKIO load = 20pF. No clock applied to CLKIO. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 PIN CONFIGURATION AIN4 AIN5 AIN6 AIN7 MUXOUTP MUXOUTN ADCINP ADCINN AIN8 AIN9 AIN10 AIN11 QFN PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 AIN3 1 36 AIN12 AIN2 2 35 AIN13 AIN1 3 34 AIN14 AIN0 4 33 AIN15 AVSS 5 32 AINCOM AVDD 6 31 VREFP ADS1158 PWDN 10 27 CS RESET 11 26 START CLKSEL 12 25 DRDY 13 14 15 16 17 18 19 20 21 22 23 24 DOUT DVDD DIN 28 SCLK 9 GPIO7 XTAL2 GPIO6 DGND GPIO5 29 GPIO4 8 GPIO3 XTAL1 GPIO2 VREFN GPIO1 30 GPIO0 7 CLKIO PLLCAP PIN ASSIGNMENTS PIN # NAME ANALOG/DIGITAL INPUT/OUTPUT 1 AIN3 Analog input Analog input 3: single-ended channel 3, differential channel 1 (–) 2 AIN2 Analog input Analog input 2: single-ended channel 2, differential channel 1 (+) 3 AIN1 Analog input Analog input 1: single-ended channel 1, differential channel 0 (–) 4 AIN0 Analog input Analog input 0: single-ended channel 0, differential channel 0 (+) 5 AVSS Analog Negative analog power supply: 0V for unipolar operation, –2.5V for bipolar operation. (Internally connected to exposed thermal pad of QFN package.) 6 AVDD Analog Positive analog power supply: +5V for unipolar operation, +2.5V for bipolar operation. 7 PLLCAP Analog PLL bypass capacitor: connect 22nF capacitor to AVSS when using crystal oscillator. 8 XTAL1 Analog 32.768kHz crystal oscillator input 1; see Crystal Oscillator section. 9 XTAL2 Analog 32.768kHz crystal oscillator input 2; see Crystal Oscillator section. 10 PWDN Digital input Power-down input: hold low for minimum of two fCLK cycles to engage low-power mode. 11 RESET Digital input Reset input: hold low for minimum of two fCLK cycles to reset the device. 12 CLKSEL Digital input Clock select input: Low = activates crystal oscillator, fCLK output on CLKIO. High = disables crystal oscillator, apply fCLK to CLKIO. 13 CLKIO Digital I/O System clock input/output (see CLKSEL pin) 14 GPIO0 Digital I/O General-purpose digital input/output 0 15 GPIO1 Digital I/O General-purpose digital input/output 1 16 GPIO2 Digital I/O General-purpose digital input/output 2 17 GPIO3 Digital I/O General-purpose digital input/output 3 18 GPIO4 Digital I/O General-purpose digital input/output 4 19 GPIO5 Digital I/O General-purpose digital input/output 5 20 GPIO6 Digital I/O General-purpose digital input/output 6 DESCRIPTION Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 5 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com PIN ASSIGNMENTS (continued) 6 PIN # NAME ANALOG/DIGITAL INPUT/OUTPUT 21 GPIO7 Digital I/O 22 SCLK Digital input SPI interface clock input: data clocked in on rising edge, clocked out on falling edge. 23 DIN Digital input SPI interface data input: data are input to the device. 24 DOUT Digital output SPI interface data output: data are output from the device. 25 DRDY Digital output Data ready output: active low. 26 START Digital input Start conversion input: active high. 27 CS Digital input SPI interface chip select input: active low. 28 DVDD Digital Digital power supply: 2.7V to 5.25V 29 DGND Digital Digital ground 30 VREFN Analog input Reference input negative 31 VREFP Analog input Reference input positive 32 AINCOM Analog input Analog input common: common input pin to all single-ended inputs. 33 AIN15 Analog input Analog input 15: single-ended channel 15, differential channel 7 (–) 34 AIN14 Analog input Analog input 14: single-ended channel 14, differential channel 7 (+) 35 AIN13 Analog input Analog input 13: single-ended channel 13, differential channel 6 (–) 36 AIN12 Analog input Analog input 12: single-ended channel 12, differential channel 6 (+) 37 AIN11 Analog input Analog input 11: single-ended channel 11, differential channel 5 (–) 38 AIN10 Analog input Analog input 10: single-ended channel 10, differential channel 5 (+) 39 AIN9 Analog input Analog input 9: single-ended channel 9, differential channel 4 (–) 40 AIN8 Analog input Analog input 8: single-ended channel 8, differential channel 4 (+) 41 ADCINN Analog input ADC differential input (–) 42 ADCINP Analog input ADC differential input (+) 43 MUXOUTN Analog output Multiplexer differential output (–) 44 MUXOUTP Analog output Multiplexer differential output (+) 45 AIN7 Analog input Analog input 7: single-ended channel 7, differential channel 3 (–) 46 AIN6 Analog input Analog input 6 : single-ended channel 6, differential channel 3 (+) 47 AIN5 Analog input Analog input 5: single-ended channel 5, differential channel 2 (–) 48 AIN4 Analog input Analog input 4: single-ended channel 4, differential channel 2 (+) DESCRIPTION General-purpose digital input/output 7 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 PARAMETER MEASUREMENT INFORMATION CS(1) tCSPW tCSSC tSCLK tSPW SCLK tSPW tDIST DIN tDIHD Hi-Z tDOPD Hi-Z DOUT tCSDO tDOHD (1) CS can be tied low. Figure 1. Serial Interface Timing SERIAL INTERFACE TIMING CHARACTERISTICS At TA= –40°C to +105°C and DVDD = 2.7V to 5.25V, unless otherwise noted. SYMBOL tSCLK (1) (2) (3) (4) DESCRIPTION MIN SCLK period MAX UNITS τCLK (1) 2 τCLK tSPW SCLK high or low pulse width (exceeding max resets SPI interface) 0.8 tCSSC CS low to first SCLK: setup time (3) 2.5 τCLK ns tDIST Valid DIN to SCLK rising edge: setup time 10 tDIHD Valid DIN to SCLK rising edge: hold time 5 tDOPD SCLK falling edge to valid new DOUT: propagation delay (4) tDOHD SCLK falling edge to old DOUT invalid: hold time tCSDO CS high to DOUT invalid (3-state) tCSPW CS pulse width high 4096 (2) ns 20 ns 5 τCLK 0 ns τCLK 2 τCLK = master clock period = 1/fCLK. Programmable to 256 τCLK. CS can be tied low. DOUT load = 20pF || 100kΩ to DGND. tDRDY DRDY tDDO DOUT Figure 2. DRDY Update Timing DRDY UPDATE TIMING CHARACTERISTICS SYMBOL DESCRIPTION tDRDY DRDY high pulse width without data read tDDO Valid DOUT to DRDY falling edge (CS = 0) TYP UNITS 1 τCLK 0.5 τCLK Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 7 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted. OFFSET WITH 0.5V REFERENCE, CHOPPING ON OFFSET WITH 4.096V REFERENCE, CHOPPING ON 6000 3500 25 Units, 254 Samples/Unit 25 Units, 256 Samples/Unit 3000 Number of Occurrences Number of Occurrences 5000 4000 3000 2000 2500 2000 1500 1000 1000 500 0 0 -4 -3 -2 1 0 -1 2 3 -2 1 0 -1 Output Code 2 Offset (Output Code) Figure 3. Figure 4. OFFSET vs TEMPERATURE GAIN ERROR HISTOGRAM 100 40 50 35 CHOP = 1 Number of Occurrences Normalized Offset (mV) 150 Units From Two Production Sets 0 -50 -100 CHOP = 0 -150 -200 30 25 20 15 10 5 -250 0 10 -15 35 60 85 110 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 -40 Temperature (°C) Absolute Gain Error (ppm) Figure 5. Figure 6. GAIN DRIFT HISTOGRAM GAIN ERROR vs TEMPERATURE 30 60 150 Units From Two Production Sets Normalized Gain Error (ppm) 40 Number of Occurrences 25 20 15 10 5 20 0 -20 -40 -60 -80 -100 -120 0 3.3 3.8 2.7 2.1 1.5 0.3 0.9 -0.9 -0.3 -1.5 -2.1 -2.7 -3.3 -3.8 -140 -40 -15 10 35 60 85 110 Temperature (°C) Gain Drift (ppm/°C) Figure 7. 8 Figure 8. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted. INTEGRAL NONLINEARITY vs VREF INTEGRAL NONLINEARITY vs INPUT LEVEL 10 8 9 6 4 Linearity Error (ppm) Linearity Error (ppm) 8 7 6 5 4 3 VREF = 4.096V 2 0 -2 -4 TA = -40°C TA = -10°C TA = +25°C 2 -6 1 -8 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -5 -4 -3 0 1 VIN (V) Figure 9. Figure 10. INL vs TEMPERATURE 2 3 4 5 OUTPUT SPECTRUM 0 f = 1kHz, -0.5dBFS DRATE[1:0] = 11 32768 Points -20 6 -40 5 -60 Level (dBFS) INL (ppm) -1 VREF (V) 7 4 3 -80 -100 -120 -140 2 -160 1 -180 0 -200 -40 -15 10 35 60 85 110 1 Temperature (°C) 10 100 1k 10k 100k Frequency (Hz) Figure 11. Figure 12. TEMPERATURE SENSOR VOLTAGE vs TEMPERATURE TEMPERATURE SENSOR READING HISTOGRAM 220 8 210 7 35 Units From Two Production Sets 200 Number of Occurrences 190 180 170 160 150 6 5 4 3 2 1 140 0 130 -40 -15 10 35 60 85 110 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Temperature Sensor Voltage (mV) -2 TA = +55°C TA = +85°C TA = +105°C Temperature (°C) Temperature Reading (°C) Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 9 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted. SENSOR BIAS CURRENT SOURCE RATIO vs TEMPERATURE SENSOR BIAS CURRENT SOURCE RATIO HISTOGRAM 14 17.5 17.0 10 Ratio (mA/mA) Number of Occurrences 12 18.0 25 Units From One Production Lot 8 6 4 16.5 16.0 15.5 15.0 2 14.5 0 14.0 1 2 3 4 5 6 9 8 7 10 11 -40 10 -15 35 Ratio (mA/mA) Figure 15. Figure 16. SUPPLY CURRENT vs TEMPERATURE 1.0 4 0.8 6 0.6 4 0.4 2 0.2 3 Current (mA) 8 DVDD Current (mA) AVDD/AVSS Current (mA) 110 Unipolar AVSS = 0V, AVDD = 5V AVDD/AVSS 2 1 AVSS/AVDD DVDD 0 0 0 -15 85 POWER-DOWN CURRENT vs TEMPERATURE 10 -40 60 Temperature (°C) 10 35 60 85 110 -40 10 -15 Temperature (°C) 35 60 85 110 Temperature (°C) Figure 17. Figure 18. POWER-DOWN CURRENT vs TEMPERATURE 140 Bipolar AVSS = -2.5V, AVDD = 2.5V 120 Current (mA) 100 AVSS 80 60 40 20 AVDD 0 -40 -15 10 35 60 85 110 Temperature (°C) Figure 19. 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 OVERVIEW The ADS1158 is a flexible, 16-bit, low-noise ADC optimized for fast multi-channel, high-resolution measurement systems. The converter provides a maximum channel scan rate of 23.7kSPS, giving a complete 16-channel scan in less than 700µs. The ADS1158 converter consists of a fourth-order, delta-sigma modulator followed by a programmable digital filter. The modulator measures the differential input signal, VIN = (ADCINP – ADCINN), against the differential reference input, VREF = (VREFP – VREFN). The digital filter receives the modulator signal and provides a low-noise digital output. The ADC channel block controls the multiplexer Auto-Scan feature. Channel Auto-Scan occurs at a maximum rate of 23.7kSPS. Slower scan rates can be used with corresponding increases in resolution. Figure 20 shows the block diagram of the ADS1158. The input multiplexer selects which analog input pins connect to the multiplexer output pins (MUXOUTP/MUXOUTN). External signal conditioning can be used between the multiplexer output pins and the ADC input pins (ADCINP/ADCINN) or the multiplexer output can be routed internally to the ADC inputs without external circuitry. Selectable current sources within the input multiplexer can be used to bias sensors or detect for a failed sensor. On-chip system function readings provide readback of temperature, supply voltage, gain, offset, and external reference. DVDD AVDD Communication is handled over an SPI-compatible serial interface with a set of simple commands to control the ADS1158. Onboard registers store the various settings for the input multiplexer, sensor detect bias, data rate selection, etc. Either an external 32.768kHz crystal, connected to pins XTAL1 and XTAL2, or an external clock applied to pin CLKIO can be used as the clock source. When using the external crystal oscillator, the system clock is available as an output for driving other devices or controllers. General-purpose digital I/Os (GPIO) provide input and output control of eight pins. GPIO[7:0] CLKIO CLKSEL PLLCAP XTAL2 XTAL1 Clock Control GPIO AIN0 Sensor Bias AIN1 CS AIN2 SPI Interface AIN3 AIN4 DOUT DRDY AIN6 AIN8 DIN Temperature Supply Monitor AIN5 AIN7 SCLK 16-Channel MUX Control Logic ADC Channel Control PWDN RESET START AIN9 AIN10 Internal Ref AIN11 AIN12 Ext Ref Monitor AIN13 Digital Filter ADC AIN14 AIN15 AINCOM AVSS MUXOUTP MUXOUTN ADCINP ADCINN VREFN VREFP GND Figure 20. ADS1158 Block Diagram Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 11 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com MULTIPLEXER INPUTS A simplified diagram of the input multiplexer is illustrated in Figure 22. The multiplexer connects one of 16 single-ended external inputs, one of eight differential external inputs, or one of the on-chip internal variables to the ADC inputs. The output of the channel multiplexer can be routed to external pins and then to the input of the ADC. This flexibility allows for use of external signal conditioning. See the External Multiplexer Loop section. Electrostatic discharge (ESD) diodes protect the analog inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below AVSS by more than 100mV, and likewise do not exceed AVDD by more than 100mV: AVSS – 100mV < (Analog Inputs) < AVDD + 100mV. The load presented by the switched capacitor can be modeled with an effective resistance (Reff) of 40kΩ for fCLK = 16MHz. Note that the effective impedance of the reference inputs loads an external reference with a non-zero source impedance. AVDD ESD Diodes VREFP 3pF VREFN ESD Diodes Overdriving the multiplexer inputs may affect the conversions of other channels. See the Input Overload Protection description in the Hardware Considerations segment of the Applications section. The converter supports two modes of channel access through the multiplexer: the Auto-Scan mode and the Fixed-Channel mode. These modes are selected by the MUXMOD bit of register CONFIG0. The Auto-Scan mode scans through the selected channels automatically, with break-before-make switching. The Fixed-Channel mode requires the user to set the channel address for each channel measured. VOLTAGE REFERENCE INPUTS (VREFP, VREFN) The voltage reference for the ADS1158 ADC is the differential voltage between VREFP and VREFN: VREF = VREFP – VREFN. The reference inputs use a structure similar to that of the analog inputs with the circuitry on the reference inputs shown in Figure 21. 12 Reff = 40kW (fCLK = 16MHz) AVSS Figure 21. Simplified Reference Input Circuit ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AVSS by more than 100mV, and likewise do not exceed AVDD by 100mV: AVSS - 100mV < (VREFP or VREFN) < AVDD + 100mV A high-quality reference voltage is essential to achieve the best performance from the ADS1158. Noise and drift on the reference degrade overall system performance. It is especially critical that special care be given to the circuitry that generates the reference voltages and the layout when operating in the low-noise settings (that is, with low data rates) to prevent the voltage reference from limiting performance. See the Reference Inputs description in the Hardware Considerations segment of the Applications section. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 VREFP VREFN Multiplexer Reference/Gain Monitor AIN0 AIN1 AIN2 Temperature Sensor Monitor AVDD AIN3 1x AIN4 2x AIN5 8x 1x AIN6 AVSS AIN7 Supply Monitor AIN8 AVDD AVSS AIN9 AIN10 AIN11 NOTE: ESD diodes not shown. Internal Reference AIN12 AVSS AIN13 AIN14 ADC AIN15 AINCOM ADCINN ADCINP Offset Monitor MUXOUTP Sensor Bias (AVDD - AVSS)/2 MUXOUTN AVSS AVDD Figure 22. Input Multiplexer Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 13 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com ADC INPUTS The ADS1158 ADC inputs (ADCINP, ADCINN) measure the input signal using internal capacitors that are continuously charged and discharged. The left side of Figure 24 shows a simplified schematic of the ADC input circuitry; the right side of Figure 24 shows the input circuitry with the capacitors and switches replaced by an equivalent circuit. Figure 23 shows the ON/OFF timings of the switches shown in Figure 24. S1 switches close during the input sampling phase. With S1 closed, CA1 charges to ADCINP, CA2 charges to ADCINN, and CB charges to (ADCINP – ADCINN). For the discharge phase, S1 opens first and then S2 closes. CA1 and CA2 discharge to approximately AVSS + 1.3V and CB discharges to 0V. This two-phase sample/discharge cycle repeats with a period of tSAMPLE = 2/fCLK. As with the multiplexer and reference inputs, ESD diodes protect the ADC inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below AVSS by more than 100mV, and likewise do not exceed AVDD by more than 100mV. tSAMPLE ON S1 OFF ON S2 OFF Figure 23. S1 and S2 Switch Timing for Figure 24 The charging of the input capacitors draws a transient current from the source driving the ADS1158 ADC inputs. The average value of this current can be used to calculate an effective impedance (Reff) where Reff = VIN/IAVERAGE. These impedances scale inversely with fCLK. For example, if fCLK is reduced by a factor of two, the impedances will double. AVSS + 1.3V AVSS + 1.3V S2 ReffA = 190kW CA1 = 0.65pF S1 Equivalent Circuit ADCINP ADCINP ReffB = 78kW CB = 1.6pF S1 (fCLK = 16MHz) ADCINN ADCINN ReffA = 190kW CA2 = 0.65pF S2 Reff = tSAMPLE/CX AVSS + 1.3V AVSS + 1.3V RAIN = ReffB || 2ReffA NOTE: ESD input diodes not shown. Figure 24. Simplified ADC Input Structure 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 MASTER CLOCK (fCLK) The ADS1158 oversamples the analog input at a high rate. This oversampling requires a high-frequency master clock to be supplied to the converter. As shown in Figure 25, the clock comes from either an internal oscillator (with external crystal), or an external clock source. 50W CLKSEL XTAL1 XTAL2 32.768kHz CLKIO Clock Output (15.729MHz) AVSS 0V to -2.5V PLLCAP (1) 22nF CLKENB Bit 4.7pF (1) Parallel resonant type. CL = 12.5pF, ESR = 35kΩ (max). Place the crystal and load capacitors as close as possible to the device pins. Internal Master Clock (fCLK) MUX 4.7pF Figure 26. Crystal Oscillator Connection CLKIO Table 1. System Clock Source Oscillator and PLL CLKSEL PIN CLKENB BIT CLOCK SOURCE CLKIO FUNCTION PLL 0 32.768kHz crystal oscillator Figure 25. Clock Generation Block Diagram 0 32.768kHz crystal oscillator 1 Output (15.729MHz) 1 External clock input X Input (16MHz) CLKSEL XTAL1 XTAL2 The CLKSEL pin determines the source of the system clock, as shown in Table 1. The CLKIO pin functions as an input or as an output. When the CLKSEL pin is set to '1', CLKIO is configured as an input to receive the master clock. When the CLKSEL pin is set to '0', the crystal oscillator generates the clock. The CLKIO pin can then be configured to output the master clock. When the clock output is not needed, it can be disabled to reduce device power consumption. Crystal Oscillator An on-chip oscillator and phase-locked loop (PLL) together with an external crystal can be used to generate the system clock. For this mode, tie the CLKSEL pin low. A 22nF PLL filter capacitor, connected from the PLLCAP pin to the AVSS pin, is required. The internal clock of the PLL can be output to the CLKIO to drive other converters or controllers. If not used, disable the clock output to reduce device power consumption; see Table 1 for settings. The clock output is enabled by a register bit setting (default is ON). Figure 26 shows the oscillator connections. Place these components as close to the pins as possible to avoid interference and coupling. Do not connect XTAL1 or XTAL2 to any other logic. The oscillator start-up time may vary, depending on the crystal and ambient temperature. The user should verify the oscillator start-up time. 0 Disabled (internally grounded) Table 2. Approved Crystal Vendors VENDOR Epson CRYSTAL PRODUCT C-001R External Clock Input When using an external clock to operate the device, apply the master clock to the CLKIO pin. For this mode, the CLKSEL pin is tied high. CLKIO then becomes an input, as shown in Figure 27. 50W CLKIO 2.7V to 5V Clock Input (16MHz) DVDD CLKSEL XTAL1 XTAL2 PLLCAP No Connection Figure 27. External Clock Connection Make sure to use a clock source clean from jitter or interference. Ringing or under/overshoot should be avoided. A 50Ω resistor in series with the CLKIO pin (placed close to the source) can often help. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 15 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com ADC The ADC block of the ADS1158 is composed of two blocks: a modulator and a digital filter. Modulator The modulator converts the analog input voltage into a pulse code modulated (PCM) data stream. When the level of differential analog input (ADCINP – ADCINN) is near the level of the reference voltage, the '1' density of the PCM data stream is at its highest. When the level of the differential analog input is near zero, the PCM '0' and '1' densities are nearly equal. The fourth-order modulator shifts the quantization noise to a high frequency (out of the passband) where the digital filter can easily remove it. The modulator continuously chops the input, resulting in excellent offset and offset drift performance. It is important to note that offset or offset drift that originates from the external circuitry is not removed by the modulator chopping. These errors can be effectively removed by using the external chopping feature of the ADS1158 (see the External Chopping section). Digital Filter Figure 28 shows the block diagram of the filter. Data are supplied to the filter from the analog modulator at a rate of fCLK/2. The fixed filter is a fifth-order sinc filter with a decimation value of 64 that outputs data at a rate of fCLK/128. The second stage of the filter is a programmable averager (first-order sinc filter) with the number of averages set by the DRATE[1:0] bits. The data rate depends upon the system clock frequency (fCLK) and the converter configuration. The data rate can be computed by Equation 1 or Equation 2: Data rate (Auto-Scan): fCLK 128(411b - DR + 4.26525 + TD) ´ 2CHOP (1) Data rate (Fixed-Channel mode): fCLK 128[411b - DR + CHOP(4.26525 + TD)] ´ 2CHOP (2) Where: DR = DRATE[1:0] register bits (binary). CHOP = Chop register bit. TD = time delay value given in Table 4 from the DLY[2:0] register bits (128/fCLK periods). The programmable low-pass digital filter receives the modulator output and produces a high-resolution digital output. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate—filter more for higher resolution, filter less for higher data rate. The filter consists of two sections, a fixed filter followed by a programmable filter. Modulator Rate = fCLK/2 Analog Modulator Data Rate = fCLK/128 5 sinc Filter Data Rate (1) = fCLK/(128 ´ Num_Ave) Programmable Averager Num_Ave (1) Data rate for Fixed-Channel mode, Chop = 0, Delay = 0. Figure 28. Block Diagram of Digital Filter 16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 Table 3 shows a listing of the averaging and data rates for each of the four DRATE[1:0] register settings for the Auto-Scan and Fixed-Channel modes, with CHOP, DLY = 0. Note that the data rate scales directly with fCLK. For example, reducing fCLK by 2x reduces the maximum data rate by 2x. Figure 30 shows the response with averaging set to 4 (DRATE[1:0] = 10). 4-reading, post-averaging produces three equally-spaced notches between each main notch of the sinc5 filter. The frequency response of DRATE[1:0] = 01 and 00 follows a similar pattern, but with 15 and 63 equally-spaced notches between the main sinc5 notches, respectively. FREQUENCY RESPONSE ½H(f)½ = ½Hsinc5(f)½ ´ ½HAverager(f)½ = 0 Data Rate Auto-Scan Mode (23.739kSPS) -20 -40 Gain (dB) The low-pass digital filter sets the overall frequency response for the ADS1158. The filter response is the product of the responses of the fixed and programmable filter sections and is given by Equation 3: Data Rate Fixed-Channel Mode (125kSPS) -60 -80 5 sin 128p ´ f fCLK sin 128p ´ Num_Ave ´ f fCLK -100 -120 ´ 64 ´ sin 2p ´ f fCLK 128p ´ f Num_Ave ´ sin fCLK -140 0 125 250 With programmable averaging, the wide notches produced by the sinc5 filter remain, but a number of narrow notches are superimposed in the response. The number of the superimposed notches is determined by the number of readings averaged (minus one). 625 Figure 29. Frequency Response, DRATE[1:0] = 11 0 Data Rate Auto-Scan Mode (15.123kSPS) -20 -40 Gain (dB) The low-pass filter has notches (or zeros) at the data output rate and multiples thereof. The sinc5 part of the filter produces wide notches at fCLK/128 and multiples thereof. At these frequencies, the filter has zero gain. Figure 29 shows the response with no post averaging. Note that in Auto-Scan mode, the data rate is reduced while retaining the same frequency response as in Fixed-Channel mode. 500 Frequency (kHz) (3) The digital filter attenuates noise on the modulator output, including noise from within the ADS1158 and external noise present within the ADS1158 input signal. Adjusting the filtering by changing the number of averages used in the programmable filter changes the filter bandwidth. With a higher number of averages, the bandwidth is reduced and more noise is attenuated. 375 Data Rate Fixed-Channel Mode (31.25kSPS) -60 -80 -100 -120 -140 0 125 250 375 500 625 Frequency (kHz) Figure 30. Frequency Response, DRATE[1:0] = 10 Table 3. Data Rates (1) (1) (2) (3) DRATE[1:0] Num_Ave (2) DATA RATE AUTO-SCAN MODE (SPS) (3) DATA RATE FIXED-CHANNEL MODE (SPS) –3dB BANDWIDTH (Hz) 11 1 23739 125000 25390 10 4 15123 31250 12402 01 16 6168 7813 3418 00 64 1831 1953 869 fCLK = 16MHz, Chop = 0, and Delay = 0. Num_Ave is the number of averages performed by the digital filter second stage. In Auto-Scan mode, the data rate listed is for a single channel; the effective data rate for multiple channels (on a per-channel basis) is the value shown in Figure 29 and Figure 30 divided by the number of active channels in a scan loop. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 17 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com ALIASING The digital filter low-pass characteristic repeats at multiples of the modulator rate of fCLK/2. Figure 31 shows the response plotted out to 16MHz at the data rate of 125kSPS (Fixed-Channel mode). Notice how the responses near dc, 8MHz, and 16MHz are the same. The digital filter attenuates high-frequency noise on the ADS1158 inputs up to the frequency where the response repeats. However, noise or frequency components present on the analog input where the response repeats alias into the passband. For most applications, an anti-alias filter is recommended to remove this noise. A simple first-order input filter with a pole at 200kHz provides –34dB rejection at the first image frequency. the first converter output is fully settled. When applying asynchronous step inputs, the settling time is somewhat different. The step-input settling time diagrams (Figure 32 and Figure 33) show the converter step response with an asynchronous step input. For most modes of operation, the analog input must be stable for one complete conversion cycle to provide settled data. In Fixed-Channel mode (DRATE[1:0] = 11), the input must be stable for five complete conversion cycles. Data Not Settled Settled Data 1 DRDY 2 Step Input 0 DRATE[1:0] = 11 125kSPS Fixed-Channel Mode -20 Figure 32. Asynchronous Step-Input Settling Time (DRATE[1:0] = 10, 01, 00) Gain (dB) -40 -60 Data Not Settled Settled Data -80 1 DRDY 2 6 -100 -120 Step Input -140 0 4 8 12 16 Figure 33. Asynchronous Step-Input Settling Time (Fixed-Channel Mode, DRATE[1:0] = 11) Frequency (MHz) Figure 31. Frequency Response Out to 16MHz Referring to Figure 29 and Figure 30, frequencies present on the analog input above the Nyquist rate (sample rate/2) are first attenuated by the digital filter and then aliased into the passband. SETTLING TIME The design of the ADS1158 provides fully-settled data when scanning through the input channels in Auto-Scan mode. The DRDY flag asserts low when the data for each channel are ready. It may be necessary to use the automatic switch time delay feature to provide time for settling of the external buffer and associated components after channel switching. When the converter is started (START pin transitions high or Start Command) with stable inputs, 18 Table 4. Effective Data Rates with Switch-Time Delay (Auto-Scan Mode) (1) DLY [2:0] TIME DELAY (128/fCLK periods) TIME DELAY (µS) DRATE [1:0] = 11 DRATE [1:0] = 10 DRATE [1:0] = 01 DRATE [1:0] = 00 000 0 0 23739 15123 6168 1831 001 1 8 19950 13491 5878 1805 010 2 16 17204 12177 5614 1779 011 4 32 13491 10191 5151 1730 100 8 64 9423 7685 4422 1639 101 16 128 5878 5151 3447 1483 110 32 256 3354 3104 2392 1247 111 48 384 2347 2222 1831 1075 (1) Time delay and data rates scale with fCLK. If Chop = 1, the data rates are half those shown. fCLK = 16MHz, Auto-Scan mode. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 EXTERNAL MULTIPLEXER LOOP The external multiplexer loop consists of two differential multiplexer output pins and two differential ADC input pins. The user may use external components (buffering/filtering, single-ended to differential conversion, etc.) to form a signal conditioning loop. For best performance, the ADC input should be buffered and driven differentially. To bypass the external multiplexer loop, connect the ADC input pins directly to the multiplexer output pins, or select internal bypass connection (BYPASS = 0 of CONFIG0). Note that the multiplexer output pins are active regardless of the bypass setting. Use of the switch time delay register reduces the effective channel data rate. Table 4 shows the actual data rates derived from Equation 1, when using the switch time delay feature. When pulse converting, where one channel is converted with each START pin pulse or each pulse command, the application software may provide the required time delay between pulses. However, with Chop = 1, the switch time delay feature may continue to be necessary to allow for settling. In estimating the time delay that may be required, Table 5 lists the time delay-to-time constant ratio (t/τ) and the corresponding final settled data in % and number of bits. SWITCH TIME DELAY When using the ADS1158 in the Auto-Scan mode, where the converter automatically switches from one channel to the next, the settling time of the external signal conditioning circuit becomes important. If the channel does not fully settle after the multiplexer channel is switched, the data may not be correct. The ADS1158 provides a switch time delay feature which automatically provides a delay after channel switching to allow the channel to settle before taking a reading. The amount of time delay required depends primarily on the settling time of the external signal conditioning. Additional consideration may be needed to account for the settling of the input source arising from the transient generated from channel switching. Table 5. Settling Time t/τ(1) FINAL SETTLING (%) FINAL SETTLING (Bits) 1 63 2 3 95 5 5 99.3 7 7 99.9 10 10 99.995 14 15 99.998 16 (1) Multiple time (τ12 + τ22+…)＝. constants can be approximated Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 by: 19 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com SENSOR BIAS An integrated current source provides a means to bias an external sensor (for example, a diode junction); or, it verifies the integrity of a sensor or sensor connection. When the sensor fails to an open condition, the current sources drive the inputs of the converter to positive full-scale. The biasing is in the form of differential currents (programmable 1.5µA or 24µA), connected to the output of the multiplexer. Figure 34 shows a simplified diagram of ADS1158 input structure with the external sensor modeled as a resistance RS between two input pins. The two 80Ω series resistors, RMUX, model the ADS1158 internal resistances. RL represents the effective input resistance of the ADC input or external buffer. When the sensor bias is enabled, they source ISDC to one selected input pin (connected to the MUXOUTP channel) and sink ISDC from the other selected input pin (connected to the MUXOUTN channel). The signal measured with the biasing enabled equals the total IR drop: ISDC[(2RMUX + RS) ׀׀RL]. Note that when the sensor is a direct short (that is, RS = 0), there continues to be a small signal measured by the ADS1158 when the biasing is enabled: ISDC[2RMUX ׀׀ RL]. AVDD ISDC 80W MUXOUTP RS ADCINP The time to charge the external capacitance is given in Equation 4: ISDC dV = dt C (4) It is also important to note that the low impedance (65kΩ) of the direct ADC inputs or the impedance of the external signal conditioning loads the current sources. This low impedance limits the ability of the current source to pull the inputs to positive full-scale for open-channel detection. OPEN-SENSOR DETECTION For open-sensor detection, set the biasing to either 1.5µA or 24µA. Then select the channel and read the output code. When a sensor opens, the positive input is pulled to AVDD and the negative input is pulled to AVSS. Because of this configuration, the output code trends toward positive full-scale. Note that the interaction of the multiplexer resistance with the current source may lead to degradation in converter linearity. It is recommended to enable the current source only periodically to check for open inputs and discard the associated data. RL 80W MUXOUTN ADCINN EXTERNAL DIODE BIASING The current source can be used to bias external diodes for temperature sensing. Scan the appropriate channels with the current source set to 24µA. Re-scan the same channels with the current source set to 1.5µA. The difference in diode voltage readings resulting from the two bias currents is directly proportional to temperature. ISDC AVSS Figure 34. Sensor Bias Structure 20 The current source is connected to the output of the multiplexer. For unselected channels, the current source is not connected. This configuration means that when a new channel is selected, the current source charges stray sensor capacitance, which may slow the rise of the sensor voltage. The automatic switch time delay feature can be used to apply an appropriate time delay before a conversion is started to provide fully settled data (see the Switch Time Delay section). Note that errors in current ratio, diode and cable resistance, or the non-ideality factor of the diode can lead to errors in temperature readings. These effects can be compensated by characterization or by calibrating the diode at known temperatures. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 EXTERNAL CHOPPING GPIO DIGITAL PORT (GPIOx) The modulator of the ADS1158 incorporates a chopping front-end that removes offset errors to provide excellent offset and offset drift performance. However, offset and offset drift that originate from external signal conditioning are not removed by the modulator. The ADS1158 has an additional chopping feature that removes external offset errors (CHOP = 1). The ADS1158 has eight dedicated general-purpose digital input/output (GPIO) pins. The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC (GPIO-Configure) register. The GPIOD (GPIO-Data) register controls the level of the pins. When reading the GPIOD register, the data returned are the level of the pins, whether they are programmed as inputs or outputs. As inputs, a write to the GPIOD has no effect. As outputs, a write to the GPIOD sets the output value. With external chopping enabled, the converter takes two readings in succession on the same channel. The first reading is taken with one polarity and the second reading is taken with the opposite polarity. The converter averages the two readings and cancels the offset, as shown in Figure 35. With chopping enabled, the effective reading reduces to half of the nominal reading rate. During Standby and Power-Down modes, the GPIO remains active. If configured as inputs, these pins must be driven (do not float). If configured as outputs, the pins are driven. The GPIO pins are set as inputs after power-on or after a reset. Figure 36 shows the GPIO port structure. Multiplexer (chopping) MUXOUTP AINn GPIO Data (read) ADCINP Optional Signal Conditioning GPIO Pin ADC GPIO Data (write) AINn MUXOUTN ADCINN Figure 35. External Chopping GPIO Control Note that because the inputs are reversed under control of the ADS1158, a delay time may be necessary to provide time for external signal conditioning to fully settle before the second phase of the reading sequence starts (see the Switch Time Delay section). External chopping can be used to reduce total offset errors and offset drift over temperature. Note that chopping must be disabled (CHOP = 0) in order to take the internal monitor readings. Figure 36. GPIO Port Pin POWER-DOWN INPUT (PWDN) The PWDN pin controls the power-down mode of the converter. In power-down mode, all internal circuitry is deactivated including the oscillator and the clock output. Hold PWDN low for at least two fCLK cycles to engage power-down. The register settings are retained during power-down. When the pin is returned high, the converter requires a wake-up time before readings can be taken, as shown in the Power-Up Timing section. Note that in power-down mode, the inputs of the ADS1158 must continue to be driven and the device continues to drive the outputs. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 21 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com Table 6. Wake-Up Times POWER-UP TIMING When powering up the device or taking the PWDN pin high to wake the device, a wake-up time is required before readings can be taken. When using the internal oscillator, the wake-up time is composed of the oscillator start-up time and the PLL lock time, and if the supplies are also being powered, there is a reset interval time of 218 fCLK cycles. Note that CLKIO is not valid during the wake-up period, as shown in Figure 37. CONDITION tWAKE INTERNAL OSCILLATOR(1) tWAKE EXTERNAL CLOCK PWDN or CLKSEL tOSC 2/fCLK AVDD – AVSS tOSC + 218/fCLK 218/fCLK (1) Wake-up times for the internal oscillator operation are typical and may vary depending on crystal characteristics and layout capacitance. The user should verify the oscillator start-up times (tOSC = oscillator start-up time). POWER-UP SEQUENCE tWAKE CLKIO The analog and digital supplies should be applied before any analog or digital input is driven. The power supplies may be sequenced in any order. The internal master reset signal is generated from the analog power supply (AVDD – AVSS), when the level reaches approximately 3.2V. The power-up master reset signal is functionally the same as the Reset Command and the RESET input pin. PWDN or CLKSEL or Reset Input (RESET) AVDD - AVSS (1) Device Ready 3.2V, typical (1) Shown with DVDD stable. Figure 37. Device Wake Time with Internal Oscillator When using the device with an external clock, the wake-up time is 2/fCLK periods when waking up with the PWDN pin and 218/fCLK periods when powering the supplies, all after a valid CLKIO is applied, as shown in Figure 38. This pin selects the source of the system clock: the crystal oscillator or an external clock. Tie CLKSEL low to select the crystal oscillator. When using an external clock (applied to the CLKIO pin), tie CLKSEL high. This pin serves either as a clock output or clock input, depending on the state of the CLKSEL pin. When using an external clock, apply the clock to this pin and set the CLKSEL pin high. When using the internal oscillator, this pin has the option of providing a clock output. The CLKENB bit of register CONFIG0 enables the clock output (default is enabled). CLKIO PWDN, CLKSEL or (1) 3.2V, typical Device Ready (1) Shown with DVDD stable. Figure 38. Device Wake Time with External Clock Table 6 summarizes the wake-up times using the internal oscillator and the external clock operations. 22 Clock Select Input (CLKSEL) Clock Input/Output (CLKIO) tWAKE AVDD - AVSS When RESET is held low for at least two fCLK cycles, all registers are reset to their default values and the digital filter is cleared. When RESET is released high, the device is ready to convert data. Start Input (START) The START pin is an input that controls the ADC process. When the START pin is taken high, the converter starts converting the selected input channels. When the START pin is taken low, the conversion in progress runs to completion and the converter is stopped. The device then enters one of the two idle modes (see the Idle Modes section for more details). See the Conversion Control section for details of using the START pin. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 Data Ready Output (DRDY) The DRDY pin is an output that asserts low to indicate when new channel data are available to read (the previous conversion data are lost). DRDY returns high after the first falling edge of SCLK during a data read operation. If the data are not read (no SCLK pulses), DRDY remains low until new channel data are available once again. DRDY then pulses high, then low to indicate new data are available; see Figure 39. DRDY SCLK DRDY is usually connected to an interrupt of a controller, DSP, or connected to a controller port pin for polling in a software loop. Channel data can be read without the use of DRDY. Read the data using the register format read and check the Status Byte when the NEW bit = 1, which indicates new channel data. Output Data Scaling and Over-Range The ADS1158 is scaled such that the output data code resulting from an input voltage equal to ±VREF has a margin of 6.6% before clipping. This architecture allows operation of applied input signals at or near full-scale without overloading the converter. Specifically, the device is calibrated so that: 1LSB = VREF/7800h, DRDY with SCLK and the output clips when: tDRDYPLS DRDY |VIN| ≥ 1.06 × VREF. Table 7 summarizes the ideal output codes versus input signals. SCLK DRDY without SCLK tDRDYPLS = 1 fCLK Figure 39. DRDY Timing (See Figure 2 for the DRDY Pulse) Table 7. Ideal Output Code versus Input Signal INPUT SIGNAL VIN (ADCINP – ADCINN) IDEAL OUTPUT CODE (1) ≥ +1.06 VREF 7FFFh Maximum positive full-scale before output clipping +VREF 7800h VIN = +VREF +1.06 VREF/(215 – 1) 0001h +1LSB 0 0000h Bipolar Zero –1.06 VREF/(215 – 1) FFFFh –1LSB –VREF 87FFh VIN = –VREF 8000h Maximum negative full-scale before output clipping 15 15 ≤ –1.06 VREF × (2 /2 (1) DESCRIPTION – 1) Ideal output code –0.5LSB excludes effects of noise, linearity, offset, and gain errors. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 23 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com INTERNAL SYSTEM READINGS Analog Power-Supply Reading (VCC) The analog power-supply voltage of the ADS1158 can be monitored by reading the VCC register. The supply voltage is routed internal to the ADS1158 and is measured and scaled using an internal reference. The supply readback channel outputs the difference between AVDD and AVSS (AVDD – AVSS), for both single and dual configurations. Note that it is required to disable chopping (CHOP = 0) before taking this reading. The scale factor of Equation 5 converts the code value to volts: Code Total Analog Supply Voltage (V) = 12 (0Ch) (5) When the power supply falls below the minimum specified operating voltage, the full operation of the ADS1158 cannot be ensured. Note that when the total analog supply voltage falls to below approximately 4.3V, the returned data are set to zero. The SUPPLY bit in the status byte is then set. The bit clears when the total supply voltage rises approximately 50mV higher than the lower trip point. The digital supply (DVDD) may be monitored by looping-back the supply voltage to an input channel. A resistor divider may be required for bipolar supply operation to reduce the DVDD level to within the range of the analog supply. Gain Reading (GAIN) In this configuration, the external reference is connected both to the analog input and to the reference input of the ADC. The data from this register indicate the gain of the device. The following scale factor (Equation 6) converts the code value to device gain: Code Device Gain (V/V) = 120 (78h) (6) To correct the device gain error, the user software can divide each converter data value by the device gain. Note that this corrects only for gain errors originating within the ADC; system gain errors that occur because of an external gain stage error or because of reference errors are not compensated. Note that it is also required to disable chopping (CHOP = 0) before taking this reading. Reference Reading (REF) In this configuration, the external reference is connected to the analog input and an internal reference is connected to the reference of the ADC. The data from this register indicate the magnitude of the external reference voltage. 24 The scale factor of Equation 7 converts the code value to external reference voltage: Code External Reference (V) = 12 (0Ch) (7) This readback function can be used to check for missing or an out-of-range reference. If the reference input pins are floating (not connected), internal biasing pulls them to the AVSS supply. This pull causes the output code to tend toward '0'. Bypass capacitors connected to the external reference pins may slow the response of the pins when open. When reading this register immediately after power-on, verify that the reference has settled to ensure an accurate reading. Note that it is required to disable chopping (CHOP = 0) before taking this reading. Temperature Reading (TEMP) The ADS1158 contains an on-chip temperature sensor. This sensor uses two internal diodes with one diode having a current density of 16x of the other. The difference in current densities of the diodes yields a difference voltage that is proportional to absolute temperature. As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device temperature tracks the PCB temperature closely. Note also that self-heating of the ADS1158 causes a higher reading than the temperature of the surrounding PCB. Note that it is required to disable chopping (CHOP = 0) before taking this reading. The scale factor of Equation 8 converts the temperature reading to °C. Before using the equation, the temperature reading code must first be scaled to microvolts. Temperature (°C) = Temp Reading(mV) - 168,000mV 394mV/°C (8) Offset Reading (OFFSET) The differential output of the multiplexer is shorted together and set to a common-mode voltage of (AVDD – AVSS)/2. Ideally, the code from this register function is 0h, but varies because of the noise of the ADC and offsets stemming from the ADC and external signal conditioning. This register can be used to calibrate or track the offset of the ADS1158 and external signal conditioning. The chop feature of the ADC can automatically remove offset and offset drift from the external signal conditioning; see the External Chopping section. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 CONVERSION CONTROL Pulse Convert Command The conversions of the ADS1158 are controlled by the START pin. Conversions begin when the START pin is taken high and conversions are stopped when the START pin is taken low. For continuous conversions, tie the START pin high. The START pin can also be tied low and the conversions controlled by the PULSE convert command. The PULSE convert command converts one channel (only) for each command sent. In this way, channel conversions can be stepped without the need to toggle the START pin. Figure 41 also shows the start of conversions with the rising edge of the START pin. If the START pin is taken high, and then low before completion of the conversion cycle (8 τCLK before DRDY asserts low), only the current channel is converted and the device enters the standby or sleep modes and waits for a new start condition. Figure 42 shows the START pin to DRDY timing. The same function of conversion control is possible using the Pulse Convert command (with the START pin low). In this operation, the data from one channel are converted with each Pulse Convert command. The Pulse convert command takes effect when the command byte is completely shifted in (eighth falling edge of SCLK). After conversion, if more than one channel is enabled (Auto-Scan mode), the converter indexes to the next selected channel after completing the conversion. START Pin As shown in Figure 40, when the START pin is taken high, conversions start beginning with the current channel. The device continues to convert all of the programmed channels, in a continuous loop, until the START pin is taken low. When this occurs, the conversion in process completes, and the device enters the standby or sleep mode and waits for a new start condition. When DRDY asserts low, the conversion data are ready. Figure 42 shows the START pin to DRDY timing. The order in which channel data are converted is described in Table 9. When the last selected channel in the program list has been converted, the device continues conversions starting with the highest priority channel. If there is only one channel selected in the Auto-Scan mode, the converter remains fixed on one channel. A write operation to any of the multiplexer channel select registers sets the channel pointer to the highest priority channel (see Table 10). In Fixed-Channel mode, the channel pointer remains fixed. Data Ready, Index to Next Channel Converting Idle Converting DRDY START Pin or Pulse Convert Command Figure 41. Pulse Conversion, Auto-Scan Mode DRDY tSDSU tDRHD START Pin Data Ready, Index to Next Channel SYMBOL Idle Mode Converting Idle DESCRIPTION DRDY tSDSU START to DRDY Setup Time to Halt Further Conversions START Pin tDRHD DRDY to START Hold Time to Complete Current Conversion Figure 40. Conversion Control, Auto-Scan Mode MIN UNIT 8 tCLK 8 tCLK Figure 42. START Pin and DRDY Timing Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 25 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com GPIO Linked START Pin Control The START pin can be controlled directly by software by connecting externally a GPIO port pin to the START pin. (Note that an external pull-down resistor is recommended to keep the GPIO from floating until the GPIO is configured as an output). For this mode of control, the START pin is effectively controlled by writing to the GPIO Data Register (GPIOD), with the write operation setting or resetting the appropriate bit. The data takes effect on the eighth falling edge of the data byte write. The START pin can then be controlled by the serial interface. Initial Delay As seen in Figure 43, when a start convert condition occurs, the first reading from ADS1158 is delayed for a number of clock cycles. This delay allows fully settled data to occur at the first data read. Data reads thereafter are available at the full data rate. The number of clock cycles delayed before the first reading is valid depends on the data rate setting, and whether exiting the Standby or Sleep mode. Table 8 lists the delayed clock cycles versus data rate. Fully-Settled Data Power-Down mode. In Converting mode, the device is actively converting channel data. The device power dissipation is the highest in this mode. This mode is divided into two sub-modes: Auto-Scan and Fixed-Channel. The next mode is the Idle mode. In this mode, the device is not converting channel data. The device remains active, waiting for input to start conversions. The power consumption is reduced from that of the Converting mode. This mode also has two sub-modes: Standby and Sleep. The last mode is Power-Down mode. In this mode, all functions of the converter are disabled to reduce power consumption to a minimum. CONVERTING MODES The ADS1158 has two converting modes: Auto-Scan and Fixed-Channel. In Auto-Scan mode, the channels to be measured are pre-selected in the address register settings. When a convert condition is present, the converter automatically measures and sequences through the channels either in a continuous loop or pulse-step fashion, depending on the trigger condition. In Fixed-Channel mode, the channel address is selected in the address register settings before acquiring channel data. When a convert condition is present, the device converts a single channel, either continuously or in pulse-step fashion, depending on the trigger condition. The data rate in this mode is higher than in Auto-Scan mode because the input channels are not indexed for each reading. DRDY Initial Delay Start Condition Figure 43. Start Condition to First Data The selection of converting modes is set with bit MUXMOD of register CONFIG0. OPERATING MODES The operating modes of the ADS1158 are defined in three basic states: Converting mode, Idle mode, and Table 8. Start Condition to DRDY Delay, Chop = 0, DLY[2:0] = 000 INITIAL DELAY (Standby Mode) (fCLK cycles) 26 INITIAL DELAY (Sleep Mode) (fCLK cycles) DRATE[1:0] Fixed-Channel Auto-Scan Fixed-Channel 11 802 708 866 772 10 1186 1092 1250 1156 01 2722 2628 2786 2692 00 8866 8772 8930 8836 Submit Documentation Feedback Auto-Scan Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 Auto-Scan Mode The ADS1158 provides 16 analog inputs that can be configured in combinations of eight differential inputs or 16 single-ended inputs. The device also provides an additional five internal system measurements. Taken together, the device allows a total of 29 possible channel measurements. The converter automatically scans and measures the selected channels, either in a continuous loop or pulse-step fashion, under the control of the START pin or Start command software. The channels are selected for measurement in registers MUXDIF, MUXSG0, MUXSG1, and SYSRED. When any of these registers are written, the internal channel pointer is set to the channel address with the highest priority (see Table 10). DRDY asserts low when the channel data are ready; see Figure 41 and Figure 40. At the same time, the converter indexes to the next selected channel and, if the START pin is high, starts a new channel conversion. Otherwise, if pulse converting, the device enters the Idle mode. For example, if channels 3, 4, 7, and 8 are selected for measurement in the list, the ADS1158 converts the channels in that order, skipping all other channels. After channel 8 is converted, the device starts over, beginning at the top of the channel list, channel 3. The following guidelines can be used when selecting input channels for Auto-Scan measurement: 1. For differential measurements, adjacent input pins (AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, etc.) are pre-set as differential pairs. Even number channels from each pair represent the positive input to the ADC and odd number channels within a pair represent the negative input (for example, AIN0/AIN1: AIN0 is the positive channel, AIN1 is the negative channel.) 2. For single-ended measurements, use AIN0 through AIN15 as single-ended inputs; AINCOM is the shared common input among them. Note: AINCOM does not need to be at ground potential. For example, AINCOM can be tied to VREFP or VREFN; or any potential between (AVSS – 100mV) and (AVDD + 100mV). 3. Combinations of differential, single-ended inputs, and internal system registers can be used in a scan. Fixed-Channel Mode In this mode, any of the 16 analog input channels (AIN0–AIN15) can be selected for the positive ADC input and any analog input channels can be selected for the negative ADC input. New channel configurations must be selected by the MUXSCH register before converting a different channel. Note that the AINCOM input and the internal system registers cannot be referenced in this mode. Idle Modes When the START pin is taken low, the device completes the conversion of the current channel and then enters one of the Idle modes, Standby or Sleep. In the Standby mode, the internal biasing of the converter is reduced. This state provides the fastest wake-up response when re-entering the run state. In Sleep mode, the internal biasing is reduced further to provide lower power consumption than the Standby mode. This mode has a slower wake-up response when re-entering the Converting mode (see Table 8). Selection of these modes is set under bit IDLMOD of register CONFIG1. POWER-DOWN MODE In power-down mode, both the analog and digital circuitry are completely disabled. SERIAL INTERFACE The ADS1158 is operated via an SPI-compatible serial interface by writing data to the configuration registers, using commands to control the converter and finally reading back the channel data. The interface consists of four signals: CS, SCLK, DIN, and DOUT. Chip Select (CS) CS is an input that selects the device for serial communication. CS is active low. When CS is high, read or write commands in progress are aborted and the serial interface is reset. Additionally, DOUT goes to a 3-state condition and inputs on DIN are ignored. DRDY indicates when data are ready, independent of CS. The converter may be operated using CS to actively select and deselect the device, or with CS tied low (always selected). CS must stay low for the entire read or write operation. When operating with CS tied low, the number of SCLK pulses must be carefully controlled to avoid false command transmission. Serial Clock (SCLK) Operation The serial clock (SCLK) is an input that is used to clock data into (DIN) and out of (DOUT) the ADS1158. This input is a Schmitt-trigger input that has a high degree of noise immunity. However, it is recommended to keep SCLK as clean as possible to prevent glitches from inadvertently shifting the data. Data are shifted into DIN on the rising edge of SCLK and data are shifted out of DOUT on the falling edge of SCLK. If SCLK is held inactive for 4096 or 256 fCLK Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 27 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com cycles (SPIRST bit of register CONFIG0), read or write operations in progress terminate and the SPI interface resets. This timeout feature can be used to recover lost communication when a serial interface transmission is interrupted or inadvertently glitched. Data Input (DIN) and Data Output (DOUT) Operation The data input pin (DIN) is used to input data to the ADS1158. The data output pin (DOUT) is used to output data from the ADS1158. Data on DIN is shifted into the converter on the rising edge of SCLK while data are shifted out on DOUT on the falling edge of SCLK. DOUT 3-states when CS is high to allow multiple devices to share the line. Reading DATA DRDY goes low to indicate that new conversion data are ready. The data may be read via a direct data read (Channel Data Read Direct) or in a register format (Channel Data Read Register). A direct data read requires the data to be read before the next occurrence of DRDY or the data are corrupted. This type of data read requires synchronization with DRDY to avoid this conflict. When reading data in the register format, the data may be read at any time without concern to DRDY. The NEW bit of the STATUS byte indicates that the data register has been refreshed with new converter data since the last read operation. The data are shifted out MSB first after the STATUS byte. The ADS1158 can be connected to a shared SPI bus. DOUT 3-states when CS is deselected (high). When the ADS1158 is connected to a shared bus, data can be read only by the Channel Data Read command format. It should be noted that on system power-up, if the ADS1158 interface signals are floating or undefined, the interface could wake in an unknown state. This condition is remedied by resetting the interface in three ways: toggle the RESET pin low then high; toggle the CS pin high then low; or hold SCLK inactive for 218 + 4096 fCLK cycles. COMMUNICATION PROTOCOL Channel Data Read Direct Communicating with the ADS1158 involves shifting data into the device (via the DIN pin) or shifting data out of the device (via the DOUT pin) under control of the SCLK input. Channel data can be accessed from the ADS1158 in two ways: Direct data read or data read with register format. With Direct read, the DIN input pin is held inactive (high or low) for at least the first three SCLK transitions. When the first three bits are 000 or 111, the device detects a direct data read and channel data are output. After the device detects this read format, commands are ignored until either CS is toggled, an SPI timeout occurs or the device is reset. The Channel Data Read command does not have this requirement. SPI Bus Sharing 28 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 Channel Data Read Command Concurrent with the first SCLK transition, channel data are output on the DOUT output pin. A total of 16 or 24 SCLK transitions complete the data read operation. The number of shifts depend on whether the status byte is enabled. The data must be completely shifted out before the next occurrence of DRDY or the remaining data are corrupted. It is recommended to monitor DRDY to synchronize the start of the read operation to avoid data corruption. Before DRDY asserts low, the MSB of the Status byte or the MSB of the data are output on DOUT (CS = '0'), as shown in Figure 44. In this format, reading the data a second time within the same DRDY frame returns data = 0. To read channel data in this mode (register format), the first three bits of the command byte to be shifted into the device are 001. The MUL bit must be set because this command is a multiple byte read. The remaining bits are don’t care but must be clocked to the device. During this time, ignore any data that appear on DOUT until the command completes. These data should be ignored. Beginning with the eighth SCLK falling edge (command byte completed), the MSB of the channel data are restarted on DOUT. The user clocks the data on the following rising edge of SCLK. A total of 32 SCLK transitions complete the data read operation. Unlike the direct read mode, the channel data can be read during a DRDY transition without data corruption. This mode is recommended when DRDY is not used and the data are polled to detect for the occurrence of new data or when CS is tied low to avoid the necessity for an SPI timeout that otherwise occurs when reading data directly. This option avoids conflicts with DRDY, as shown in Figure 45. COMMAND DESCRIPTION Commands may be sent to the ADS1158 with CS tied low. However, after the Channel Data Read Direct operation, it is necessary to toggle CS or an SPI timeout must occur to reset the interface before sending a command. DRDY CS (1) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SCLK (2) DOUT Data Byte 1 (MSB) Status Byte Data Byte 2 (LSB) DIN (hold inactive) (3) (1) No SCLK activity. (2) Optional for Auto-Scan mode, disabled for Fixed-Channel mode. See Table 12, Status Byte. (3) After the channel data read operation, CS must be toggled or an SPI timeout must occur before sending commands. Figure 44. Channel Data Read Direct (No Command) CS 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SCLK DIN DOUT Command Byte 1 Don't Care Don't Care Data (2) Don't Care Data (1) (2) (1) After the prescribed number of registers are read, then one or more additional commands can be issued in succession. (2) Four bytes for channel data register read. See Table 12, Status Byte. One or more bytes for register read, depending on MUL bit. Figure 45. Register and Channel Data (Register Format) Read Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 29 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com Register Read Command Beginning with the eighth SCLK rising edge (command byte completed), the MSB of the data are shifted in. The remaining seven SCLK rising edges complete the write to a single register. If MUL = '1', the data to the next register can be written by supplying additional SCLKs. The operation terminates when the last register is accessed (address = 09h), as shown in Figure 46. To read register data, the first three bits of the command byte to be shifted into the device are 010. These bits are followed by the multiple register read bit (MUL). If MUL = '1', then multiple registers can be read in sequence beyond the desired register. If MUL = '0', only data from the addressed register can be read. The last four bits of the command word are the beginning register address bits. During this time, the invalid data may appear on DOUT until the command is completed. These data should be ignored. Beginning with the eighth falling edge of SCLK (command byte completed), the MSB of the register data are output on DOUT. The remaining eight SCLK transitions complete the read of a single register. If MUL = '1', the data from the next register can be read in sequence by supplying additional SCLKs. The operation terminates when the last register is accessed (address = 09h); see Figure 45. CONTROL COMMANDS Pulse Convert Command See Conversion Control section. Reset Command The Reset command resets the ADC. All registers are reset to their default values. A conversion in process continues but will be invalid when completed (DRDY low). This conversion data should be discarded. Note that the SPI interface may require reset for this command, or any command, to function. To ensure device reset under a possible locked SPI interface condition, do one of the following: 1) toggle CS high then low and send the reset command; or 2) hold SCLK inactive for 256/fCLK or 4096/fCLK and send the reset command. The control commands are illustrated in Figure 47. Register Write Command To write register data, the first three bits of the command byte to be shifted into the device are 011. These bits are followed by the multiple register read bit (MUL). If MUL = '1', then multiple registers can be written in sequence beyond the desired register. If MUL = '0', only data to the addressed register can be written. The remaining four bits of the command word are the beginning register address bits. During this time, the invalid data may appear on DOUT until the command is completed. These data should be ignored. CS 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SCLK Command Byte DIN Register Data (1) Register Data (1)(2) (1) One or more bytes, depending on MUL bit. (2) After the prescribed number of registers are read, then one or more additional commands can be issued in succession. Figure 46. Register Write Operation CS 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SCLK DIN Command 1 Command 2 (1) Command 3 (1) (1) One or more additional commands can be issued in succession. Figure 47. Control Command Operation 30 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 CHANNEL DATA The data read operation outputs either three bytes (one byte for status and two bytes for data), or two bytes for data only. The selection of the 3-byte or 2-byte data read is set by the bit STAT in register CONFIG0 (see Table 12, Status Byte, for options). In the 3-byte read, the first byte is the status byte and the following two bytes are the data bytes. The MSB (Data15) of the data are shifted out first. Table 9. CHANNEL DATA FORMAT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1 BYTE STATUS NEW OVF SUPPLY CHID4 CHID3 CHID2 CHID1 CHID0 2 MSB Data15 Data14 Data13 Data12 Data11 Data10 Data9 Data8 3 LSB Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data0 STATUS BYTE BIT STATUS.7, NEW The NEW bit is set when the results of a Channel Data Read Command returns new channel data. The bit remains set indefinitely until the channel data are read. When the channel data are read again before the converter updates with new data, the previous data are output and the NEW bit is cleared. If the channel data are not read before the next conversion update, the data from the previous conversion is lost. As shown in Figure 48, the NEW bit emulates the operation of the DRDY output pin. To emulate the function of the DRDY output pin in software, the user reads data at a rate faster than the converter data rate. The user then polls the NEW bit to detect for new channel data. 0 = Channel data have not been updated since the last read operation. 1 = Channel data have been updated since the last read operation. DRDY NEW Bit Data Reads (register format) Figure 48. NEW Bit Operation BIT STATUS.6, OVF When this bit is set, it indicates that the differential voltage applied to the ADC inputs have exceeded the range of the converter |VIN| > 1.06VREF. During over-range, the output code of the converter clips to either positive FS (VIN ≥ 1.06 × VREF) or negative FS (VIN ≤ –1.06 × VREF). This bit, with the MSB of the data, can be used to detect positive or negative over-range conditions. Note that because of averaging incorporated within the digital filter, the absence of this bit does not assure that the modulator of the ADC has not saturated as a result of possible transient input overload conditions. BIT STATUS.5, SUPPLY This bit indicates that the analog power-supply voltage (AVDD – AVSS) is below a preset limit. The SUPPLY bit is set when the value falls below 4.3V (typically) and is reset when the value rises 50mV higher (typically) than the lower trip point. The output data of the ADC may not be valid under low power-supply conditions. BITS CHID[4:0] CHANNEL ID BITS The Channel ID bits indicate the measurement channel of the acquired data. Note that for Fixed-Channel mode, the Channel ID bits are undefined. See Table 10 for the channel ID, the measurement priority, and the channel description for Auto-Scan Mode. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 31 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com BITS DATA[15:0] OF DATA BYTES The ADC output data are 16 bits wide (DATA[15:0]). DATA15 is the most significant bit (MSB) and DATA0 is the least significant bit (LSB). The data are coded in binary twos complement (BTC) format. Table 10. Channel ID and Measurement Order (Auto-Scan Mode) 32 BITS CHID[4:0] PRIORITY CHANNEL DESCRIPTION 00h 1 (highest) DIFF0 (AIN0–AIN1) Differential 0 01h 2 DIFF1 (AIN2–AIN3) Differential 1 02h 3 DIFF2 (AIN4–AIN5) Differential 2 03h 4 DIFF3 (AIN6–AIN7) Differential 3 04h 5 DIFF4 (AIN8– AIN9) Differential 4 05h 6 DIFF5 (AIN10–AIN11) Differential 5 06h 7 DIFF6 (AIN12–AIN13) Differential 6 07h 8 DIFF7 (AIN14–AIN15) Differential 7 08h 9 AIN0 Single-ended 0 09h 10 AIN1 Single-ended 1 0Ah 11 AIN2 Single-ended 2 0Bh 12 AIN3 Single-ended 3 0Ch 13 AIN4 Single-ended 4 0Dh 14 AIN5 Single-ended 5 0Eh 15 AIN6 Single-ended 6 0Fh 16 AIN7 Single-ended 7 10h 17 AIN8 Single-ended 8 11h 18 AIN9 Single-ended 9 12h 19 AIN10 Single-ended 10 13h 20 AIN11 Single-ended 11 14h 21 AIN12 Single-ended 12 15h 22 AIN13 Single-ended 13 16h 23 AIN14 Single-ended 14 17h 24 AIN15 Single-ended 15 18h 25 OFFSET OFFSET 1Ah 26 VCC AVDD – AVSS supplies 1Bh 27 TEMP Temperature 1Ch 28 GAIN Gain 1Dh 29 (lowest) REF External reference Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 COMMAND AND REGISTER DEFINITIONS Commands are used to read channel data, access the configuration registers, and control the conversion process. If the command is a register read or write operation, one or more data bytes follow the command byte. If bit MUL = 1 in the command byte, then multiple registers can be read or written in one command operation (see the MUL bit). Commands can be sent back-to-back without toggling CS; however, after a channel Data Read Direct operation, CS must be toggled or an SPI timeout must occur before sending a command. The data read by command does not require CS to be toggled. The command byte consists of three fields: the Command Bits(C[2:0]), multiple register access bit (MUL), and the Register Address Bits (A[3:0]); see the Command Byte register. Command Byte 7 6 5 4 3 2 1 0 C2 C1 C0 MUL A3 A2 A1 A0 Bits C[2:0]—Command Bits These bits code the command within the command byte. C[2:0] DESCRIPTION COMMENTS 000 Channel data read direct (no command) 001 Channel data read command (register format) 010 Register read command 011 Register write command 100 Pulse convert command 101 Reserved 110 Reset command 111 Channel data read direct (no command) Toggle CS or allow SPI timeout before sending command Set MUL = 1; status byte always included in data MUL, A[3:0] are don't care MUL, A[3:0] don't care Toggle CS or allow SPI timeout before sending command Bit 4 MUL: Multiple Register Access 0 = Disable Multiple Register Access 1 = Enable Multiple Register Access This bit enables the multiple register access. This option allows writing or reading more than one register in a single command operation. If only one register is to be read or written, set MUL = '0'. For multiple register access, set MUL = '1'. The read or write operation begins at the addressed register. The ADS1158 automatically increments the register address for each register data byte subsequently read or written. The multiple register read or write operations complete after register address = 09h (device ID register) has been accessed. The multiple register access is terminated in one of three ways: 1. The user takes CS high. This action resets the SPI interface. 2. The user holds SCLK inactive for 4096 fCLK cycles. This action resets the SPI interface. 3. Register address = 09h has been accessed. This completes the command and the ADS1158 is then ready for a new command. Note for the Channel Data Read command, this bit must be set to read the three data bytes (one status byte and two data bytes). A[3:0] Register Address Bits These bits are the register addresses for a register read or write operation; see Table 11. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 33 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com REGISTERS Table 11. Register Map ADDRESS Bits A[3:0] REGISTER NAME DEFAULT VALUE 00h CONFIG0 01h CONFIG1 02h 03h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0Ah 0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0 83h IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0 MUXSCH 00h AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0 MUXDIF 00h DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0 04h MUXSG0 FFh AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 05h MUXSG1 FFh AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 06h SYSRED 00h 0 0 REF GAIN TEMP VCC 0 OFFSET 07h GPIOC FFh CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0 08h GPIOD 00h DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 09h ID 8Bh ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 CONFIG0: CONFIGURATION REGISTER 0 (Address = 00h) 7 6 5 4 3 2 1 0 0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0 Default = 0Ah. Bit 7 Must be 0 (default) Bit 6 SPIRST SPI Interface Reset Timer This bit sets the number of fCLK cycles in which SCLK is inactive until the SPI interface resets. This bit places a lower limit on the frequency of SCLK in which to read or write data to the device. The SPI interface only is reset and not the device itself. When the SPI interface is reset, it is ready for a new command. 0 = Reset when SCLK inactive for 4096fCLK cycles (256µs, fCLK = 16MHz) (default). 1 = Reset when SCLK inactive for 256fCLK cycles (16µs, fCLK = 16MHz). Bit 5 MUXMOD This bit sets either the Auto-Scan or Fixed-Channel mode of operation. 0 = Auto-Scan mode (default) In Auto-Scan mode, the input channel selections are eight differential channels (DIFF0–DIFF7) and 16 single-ended channels (AIN0–AIN15). Additionally, five internal monitor readings can be selected. These selections are made in registers MUXDIF, MUXSG0, MUXSG1, and SYSRED. In this mode, settings in register MUXSCH have no effect. See the Auto-Scan Mode section for more details. 1 = Fixed-Channel mode In Fixed-Channel mode, any of the analog input channels may be selected for the positive measurement and the negative measurement channels. The inputs are selected in register MUXSCH. In this mode, registers MUXDIF, MUXSG0, MUXSG1, and SYSRED have no effect. Note that it is not possible to select the internal monitor readings in this mode. Bit 4 BYPAS This bit selects either the internal or external connection from the multiplexer output to the ADC input. 0 = ADC inputs use internal multiplexer connection (default). 1 = ADC inputs use external ADC inputs (ADCINP and ADCINN). Note that the Temperature, VCC, Gain, and Reference internal monitor readings automatically use the internal connection, regardless of the BYPAS setting. The Offset reading uses the setting of BYPAS. 34 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 Bit 3 CLKENB This bit enables the clock output on pin CLKIO. The clock output originates from the device crystal oscillator and PLL circuit. 0 = Clock output on CLKIO disabled. 1 = Clock output on CLKIO enabled (default). Note: If the CLKSEL pin is set to '1', the CLKIO pin is a clock input only. In this case, setting this bit has no effect. Bit 2 CHOP This bit enables the chopping feature on the external multiplexer loop. 0 = Chopping disabled (default) 1 = Chopping enabled The chopping feature corrects for offset originating from components used in the external multiplexer loop; see the External Chopping section. Note that for Internal System readings (Temperature, VCC, Gain, and Reference), the CHOP bit must be 0. Bit 1 STAT Status Byte Enable When reading channel data from the ADS1158, a status byte is normally included with the conversion data. However, in some ADS1158 operating modes, the status byte can be disabled. Table 12, Status Byte, shows the modes of operation and the data read formats in which the status byte can be disabled. 0 = Status byte disabled 1 = Status byte enabled (default) Table 12. Status Byte CHANNEL DATA READ COMMAND CHANNEL DATA READ DIRECT Auto-Scan Always enabled Enabled/disabled by STAT bit Fixed-Channel Always enabled (byte is undefined) Always disabled MODE Bit 0 Must be 0 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 35 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com CONFIG1: CONFIGURATION REGISTER 1 (Address = 01h) 7 6 5 4 3 2 1 0 IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0 Default = 83h. Bit 7 IDLMOD This bit selects the Idle mode when the device is not converting, Standby or Sleep. The Sleep mode offers lower power consumption but has a longer wake-up time to re-enter the run mode; see the Idle Modes section. 0 = Select standby mode 1 = Select sleep mode (default) Bits 6–4 DLY[2:0] These bits set the amount of time the converter delays after indexing to a new channel but before starting a new conversion. This value should be set large enough to allow for the full settling of external filtering or buffering circuits used between the MUXOUTP, MUXOUTN, and ADCINP, ADCINN pins; see the Switch Time Delay section. (default = 000) Bits 3–2 SBCS[1:0] These bits set the sensor bias current source. 0 = Sensor bias current source off (default) 1 = 1.5µA source 3 = 24µA source Bits 1–0 DRATE[1:0] These bits set the data rate of the converter. Slower reading rates yield increased resolution. The actual data rates shown in the table can be slower, depending on the use of Switch Time Delay or the Chop feature. See the Switch Time Delay section. The reading rate scales with the master clock frequency. DRATE[1:0] DATA RATE AUTO-SCAN MODE (SPS) DATA RATE FIXED-CHANNEL MODE (SPS) 11 23739 125000 10 15123 31250 01 6168 7813 00 1831 1953 fCLK = 16MHz, Chop = 0, Delay = 0. 36 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 MUXSCH: MULTIPLEXER FIXED-CHANNEL REGISTER (Address = 02h) 7 6 5 4 3 2 1 0 AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0 Default = 00h. This register selects the input channels of the multiplexer to be used for the Fixed-Channel mode. The MUXMOD bit in register CONFIG0 must be set to '1'. In this mode, bits AINN[3:0] select the analog input channel for the negative ADC input, and bits AINP[3:0] select the analog input channel for the positive ADC input. See the Fixed-Channel Mode section. MUXDIF: MULTIPLEXER DIFFERENTIAL INPUT SELECT REGISTER (Address = 03h) 7 6 5 4 3 2 1 0 DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0 Default = 00h. MUXSG0: MULTIPLEXER SINGLE-ENDED INPUT SELECT REGISTER 0 (Address = 04h) 7 6 5 4 3 2 1 0 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 Default = FFh. MUXSG1: MULTIPLEXER SINGLE-ENDED INPUT SELECT REGISTER 1 (Address = 05h) 7 6 5 4 3 2 1 0 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 Default = FFh. SYSRED: SYSTEM READING SELECT REGISTER (Address = 06h) 7 6 5 4 3 2 1 0 0 0 REF GAIN TEMP VCC 0 OFFSET Default = 00h. These four registers select the input channels and the internal readings for measurement in Auto-Scan mode. For differential channel selections (DIFF0…DIFF7), adjacent input pins (AIN0/AIN1, AIN2/AIN3, etc.) are pre-set as differential inputs. All single-ended inputs are measured with respect to the AINCOM input. AINCOM may be set to any level within ±100mV of the analog supply range. Channels not selected are skipped in the measurement sequence. Writing to any of these four registers resets the internal channel pointer to the channel with the highest priority (see Table 10). Note that the bits indicated as '0' must be set to 0. 0 = Channel not selected within a reading sequence. 1 = Channel selected within a reading sequence. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 37 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com GPIOC: GPIO CONFIGURATION REGISTER (Address = 07h) 7 6 5 4 3 2 1 0 CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0 Default = FFh. This register configures the GPIO pins as inputs or as outputs. Note that the default configurations of the port pins are inputs and as such they should not be left floating. See the GPIO Digital Port section. 0 = GPIO is an output; 1 = GPIO is an input (default). CIO[7:0] GPIO Configuration bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 CIO7, CIO6, CIO5, CIO4, CIO3, CIO2, CIO1, CIO0, digital digital digital digital digital digital digital digital I/O I/O I/O I/O I/O I/O I/O I/O configuration bit configuration bit configuration bit configuration bit configuration bit configuration bit configuration bit configuration bit for for for for for for for for pin GPIO7 pin GPIO6 pin GPIO5 pin GPIO4 pin GPIO3 pin GPIO2 pin GPIO1 pin GPIO0 GPIOD: GPIO DATA REGISTER (Address = 08h) 7 6 5 4 3 2 1 0 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 Default = 00h. This register is used to read and write data to the GPIO port pins. When reading this register, the data returned corresponds to the state of the GPIO external pins, whether they are programmed as inputs or as outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the GPIOD has no effect. See the GPIO Digital Port section. 0 = GPIO is logic low (default); 1 = GPIO is logic high. DIO[7:0] GPIO Data bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 DIO7, DIO6, DIO5, DIO4, DIO3, DIO2, DIO1, DIO0, digital digital digital digital digital digital digital digital I/O I/O I/O I/O I/O I/O I/O I/O data bit data bit data bit data bit data bit data bit data bit data bit for pin for pin for pin for pin for pin for pin for pin for pin GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 ID: DEVICE ID REGISTER (Address = 09h) 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Default = 8Bh. ID[7:0] ID bits Factory-programmed ID bits. Read-only. 38 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 APPLICATION INFORMATION HARDWARE CONSIDERATIONS The following summarizes the design and layout considerations when using the ADS1158: a. Power Supplies: The converter accepts a single +5V supply (AVDD = +5V and AVSS = AGND) or dual, bipolar supplies (typically AVDD = +2.5V, AVSS = –2.5V). Dual supply operation accommodates true bipolar input signals, within a ±2.5V range. Note that the maximum negative input voltage to the multiplexer is limited to AVSS – 100mV, and the maximum positive input voltage is limited to AVDD + 100mV. The range for the digital power supply (DVDD) is 2.7V to 5.25V. For all supplies, use a 10µF tantalum capacitor, bypassed with a 0.1µF ceramic capacitor, placed close to the device pins. Alternatively, a single 10µF ceramic capacitor can be used. The supplies should be relatively free from noise and should not be shared with devices that produce voltage spikes (such as relays, LED display drivers, etc.). If a switching power supply is used, the voltage ripple should be low (< 2mV). The analog and digital power supplies may be sequenced in any order. b. Analog (Multiplexer) Inputs: The 16-channel analog input multiplexer can accommodate 16 single-ended inputs, eight differential input pairs, or combinations of either. These options permit freedom in choosing the input channels. The channels do not have to be used consecutively. Unassigned channels are skipped by the device. In the Fixed-Channel mode, any of the analog inputs (AIN0 to AIN15) can be addressed for the positive input and for the negative input. The full-scale range of the device is 2.13VREF, but the absolute analog input voltage is limited to 100mV beyond the analog supply rails. Input signals exceeding the analog supply rails (for example, ±10V) must be divided prior to the multiplexer inputs. c. Input Overload Protection: Overdriving the multiplexer inputs may affect the conversions of other channels. In the case of input overload, external Schottky diode clamps and series resistor are recommended, as shown in Figure 49. AVDD BAT54SWTI 10kW Input AINx typ. AVSS Figure 49. Input Overload Protection d. ADC Inputs: The external multiplexer loop of the ADS1158 allows for the inclusion of signal conditioning between the output of the multiplexer and the input of the ADC. Typically, an amplifier provides gain, buffering, and/or filtering to the input signal. For best performance, the ADC inputs should be driven differentially. A differential in/differential out or a single-ended-to-differential driver is recommended. If the driver uses higher supply voltages than the device itself (for example, ±15V), attention should be paid to power-supply sequencing and potential over-voltage fault conditions. Protection resistors and/or external clamp diodes may be used to protect the ADC inputs. A 1nF or higher capacitor should be used directly across the ADC inputs. e. Reference Inputs: It is recommended to use a 10µF tantalum capacitor with a 0.1µF ceramic capacitor directly across the reference pins, VREFP and VREFN. The reference inputs should be driven by a low-impedance source. For rated performance, the reference should have less than 3µVRMS broadband noise. For references with higher noise, external filtering may be necessary. Note that when exiting the sleep mode, the device begins to draw a small current through the reference pins. Under this condition, the transient response of the reference driver should be fast enough to settle completely before the first reading is taken, or simply discard the first several readings. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 39 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com f. Clock Source: The ADS1158 requires a clock signal for operation. The clock can originate from either the crystal oscillator or from an external clock source. The internal oscillator uses a PLL circuit and an external 32.768kHz crystal to generate a 15.7MHz master clock. The PLL requires a 22nF capacitor from the PLLCAP pin to AVSS. The crystal and load capacitors should be placed close to the pins as possible and kept away from other traces with ac components. A buffered output of the 15.7MHz clock can be used to drive other converters or controllers. An external clock source can be used up to 16MHz. For best performance, the clock of the SPI interface controller and the converter itself should be on the same domain. This configuration requires that the ratio of the SCLK to device clock must be limited to 1,1/2,1/4, 1/8, etc. g. Digital Inputs: It is recommended to source terminate the digital inputs and outputs of the device with a 50Ω (typical) series resistor. The resistors should be placed close to the driving end of the source (output pins, oscillator, logic gates, DSP, etc). This placement helps to reduce the ringing and overshoot on the digital lines. h. Hardware Pins: START, DRDY, RESET, and PWDN. These pins allow direct pin control of the ADS1158. The equivalent of the START and DRDY pins is provided via commands through the SPI interface; these pins may be left unused. The device also has a RESET command. The PWDN pin places the ADC into very low-power state where the device is inactive. i. SPI Interface: The ADS1158 has an SPI-compatible interface. This interface consists of four signal lines: SCLK, DIN, DOUT, and CS. When CS is high, the DIN input is ignored and the DOUT output 3-states. See Chip Select (CS) for more details. The SPI interface can be operated in a minimum configuration without the use of CS (tie CS low; see the Serial Interface and Communication Protocol sections). j. GPIO: The ADS1158 has eight, userprogrammable digital I/O pins. These pins are controlled by register settings. The register setting is default to inputs. If these pins are not used, tie them high or low (do not float input pins) or configure them as outputs. k. QFN Package: See Application Note SLUA271, 40 QFN/SON PCB Attachment for PCB layout recommendations, available for download at www.ti.com. The exposed thermal pad of the ADS1158 should be connected electrically to AVSS. CONFIGURATION GUIDE Configuration of the ADS1158 involves setting the configuration registers via the SPI interface. After the device is configured for operation, channel data are read from the device through the same SPI interface. The following procedure is recommended to configure the device: 1. Reset the SPI Interface: Before using the SPI interface, it may be necessary to recover the SPI interface. To reset the interface, set CS high or disable SCLK for 4096 (256) fCLK cycles. 2. Stop the Converter: Set the START pin low to stop the converter. Although not necessary for configuration, this command stops the channel scanning sequence which then points to the first channel after configuration. 3. Reset the Converter: The reset pin can be pulsed low or a Reset command can be sent. Although not necessary for configuration, reset re-initializes the device into a known state. 4. Configure the Registers: The registers are configured by writing to them either sequentially or as a group. The user may configure the software in either mode. Any write to the Auto-Scan channel-select registers resets the channel pointer to the channel of highest priority. 5. Verify Register Data: The register data may be read back for verification of device communications. 6. Start the Converter: The converter can be started with the START pin or with a Pulse Convert command sent through the interface. 7. Read Channel Data: The DRDY asserts low when data are ready. The channel data can be read at that time. If DRDY is not used, the updated channel data can be checked by reading the NEW bit in the status byte. The status byte also indicates the origin of the channel data. If the data for a given channel is not read before DRDY asserts low again, the data for that channel is lost and replaced with new channel data. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 DIGITAL INTERFACE CONNECTIONS The ADS1158 SPI-compatible interface easily connects to a wide variety of microcontrollers and DSPs. Figure 50 shows the basic connection to TI's MSP430 family of low-power microcontrollers. Figure 51 shows the connection to microcontrollers with an SPI interface such as the 68HC11 family, or TI's MSC12xx family. Note that the MSC12xx includes a high-resolution ADC; the ADS1158 can be used to provide additional channels of measurement or add higher-speed connections. Finally, Figure 52 shows how to connect the ADS1158 to a TMS320x DSP. TMS320R2811 ADS1158 DIN SPISIMO DOUT SPISOMI DRDY XINT1 SCLK SPICLK (1) SPISTA CS (1) CS may be tied low. Figure 52. Connection to TMS320R2811 DSP ADS1158 MSP430 GPIO Connections DIN P1.3 DOUT P1.2 DRDY P1.0 SCLK P1.6 (1) P1.4 CS The ADS1158 has eight GPIO pins. Each pin can be configured as an input or an output. Note that pins configured as inputs should not float. The pins can be used to read key pads, drive LED indicator, etc., by reading and writing the GPIO data register (GPIOD). See Figure 53. 3.3V (1) CS may be tied low. 10kW Figure 50. Connection to MSP430 Microcontroller MSC12xx or 68HC11 ADS1158 DIN MOSI DOUT MISO DRDY INT SCLK SCK (1) CS GPIOx (Input) Key Pad 3.3V LED Indicator ADS1158 470 GPIOx (Output) 4.7kW IO Figure 53. GPIO Connections (1) CS may be tied low. Figure 51. Connection to Microcontrollers with an SPI Interface Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 41 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com ANALOG INPUT CONNECTIONS Figure 54 shows the ADS1158 interfacing to high-level ±10V inputs, commonly used in industrial environments. In this case, bipolar power supplies are used to avoid the need for input signal level-shifting that is otherwise required with a single supply. The input resistors serve both to reduce the level of the 10V input signal to within the ADC range and also protect the inputs from inadvertent signal over-voltage up to 30V. The external amplifiers convert the single-ended inputs to a fully differential output to drive the ADC inputs. Driving the inputs differentially maintains good linearity performance. The 2.2nF capacitor at the ADC inputs is required to bypass the ADC sampling currents. The 2.5V reference, REF3125, is filtered and buffered to provide a low-noise reference input to the ADC. The chop feature of the ADC can be used to reduce offset and offset drift of the amplifiers. For ±1V input signals, the input resistor divider can be removed and replaced with a series protection resistor. For 20mA input signals, the input resistor divider is replaced by a 50Ω resistor, connected from each input to AINCOM. + 10mF Figure 55 illustrates the ADS1158 interfacing to multiple pressure sensors that have a resistor bridge output. Each sensor is excited by the +5V single supply that also powers the ADS1158, and likewise is used as the ADS1158 reference input; the 6% input overrange capability accommodates input levels at or above VREF. The ratiometric connection provides cancellation of excitation voltage drift and noise. For best performance, the +5V supply should be free from glitches or transients. The 5V supply input amplifiers (two OPA365s) form a differential input/differential output buffer with the gain set to 10. The chop feature of the ADS1158 is used to reduce offset and offset drift to very low levels. The 2.2nF capacitor at the ADC inputs is required to bypass the ADC sampling currents. The 47Ω resistors isolate the operational amplifier outputs from the filter capacitor. +2.5V -2.5V 0.1mF When using Auto-Scan mode to sequence through the channels, the switch time delay feature (programmable by registers) can be used to provide additional settling time of the external components. + 10mF 0.1mF +2.5V +2.5V AVSS AVDD 9.09kW OPA350 AIN0 10mF + -2.5V 0.47mF 100mF 0.1mF ADCINN AINCOM + REFN ADCINP 1kW MUXOUTN AIN15 10kW REF5040 0.1mF ADS1158 9.09kW ±10V 100W REFP ¼ ¼ 1kW MUXOUTP ±10V -2.5V 2.2nF 47W +2.5V 10kW 20mA Input AINx 10kW OPA365 +2.5V 50W 47W OPA365 -2.5V -2.5V NOTE: 0.1µF capacitors not shown. Figure 54. Multichannel, ±10V Single-Ended Input, Bipolar Supply Operation 42 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 ADS1158 www.ti.com ............................................................................................................................................................. SBAS429A – JUNE 2008 – REVISED JUNE 2008 +5V RFI 0.1mF 10mF + 2kW RFI AVSS AIN0 AVDD 2kW RFI REFP AIN1 ¼ ¼ ADS1158 0.1mF +5V ADCINN AINCOM RFI ADCINP AIN15 MUXOUTP 2kW RFI 10mF REFN AIN14 MUXOUTN ¼ 2kW RFI + 2.2nF 47W OPA365 R2 10kW R1 2.2kW R2 10kW 47W OPA365 NOTE: G = 1 + 2R2/R1. 0.1µF supply bypass capacitor not shown. Figure 55. Bridge Input, Single-Supply Operation Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 43 ADS1158 SBAS429A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (June 2008) to Revision A ......................................................................................................... Page • • • • • • • 44 Corrected typical specification value for offset error in Electrical Characteristics table from 0.5LSB to –0.5LSB ................ 3 Changed offset drift specification parameters in Electrical Characteristics table; combined chopping on and chopping off specifications. Changed typical value from 0.5µV/°C to 1µV/°C....................................................................... 3 Corrected typical specification value for gain drift in Electrical Characteristics table from 0.4ppm/°C to 2ppm/°C .............. 3 Changed typical noise specification in Electrical Characteristics table from 0.4LSB(PP) to 0.6LSB(PP) .................................. 3 Corrected maximum value for AVDD, AVSS supply current under power-down conditions in Electrical Characteristics table from 85µA to 200µA ............................................................................................................................. 4 Added Figure 18, Power-Down Current vs Temperature (Unipolar) ................................................................................... 10 Added Figure 19, Power-Down Current vs Temperature (Bipolar)...................................................................................... 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS1158 PACKAGE OPTION ADDENDUM www.ti.com 11-Jul-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS1158IRTCR ACTIVE QFN RTC 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1158IRTCRG4 ACTIVE QFN RTC 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1158IRTCT ACTIVE QFN RTC 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1158IRTCTG4 ACTIVE QFN RTC 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1158IRTCR QFN RTC 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS1158IRTCT QFN RTC 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1158IRTCR QFN RTC 48 2500 333.2 345.9 28.6 ADS1158IRTCT QFN RTC 48 250 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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