HD64645/HD64646 LCTC (LCD Timing Controller) ADE-207-276(Z) '99.9 Rev. 0.0 Description The HD64645/HD64646 LCTC is a control LSI for large size dot matrix liquid crystal displays. The LCTC is software compatible with the HD6845 CRTC, since its programming method of internal registers and memory addresses is based on the CRTC. A display system can be easily converted from a CRT to an LCD. The HD64646 LCTC is a modified version of the HD64645 LCTC with different LCD interface timing. The LCTC offers a variety of functions and performance features such as vertical and horizontal scrolling, and various types of character attribute functions such as reverse video, blinking, nondisplay (white or black), and an OR function for simple superimposition of character and graphic displays. The LCTC also provides DRAM refresh address output. A compact LCD system with a large screen can be configured by connecting the LCTC with the HD66110ST (column driver) and the HD66113T (common driver) by utilizing 4-bit × 2 data outputs. Power dissipation has been lowered by adopting the CMOS process. Features • Software compatible with the HD6845 CRTC • Programmable screen size Up to 1024 dots (height) Up to 4096 dots (width) • High-speed data transfer Up to 20 Mbits/s in character mode Up to 40 Mbits/s in graphic mode • Selectable single or dual screen configuration • Programmable multiplexing duty ratio: static to 1/512 duty cycle • Programmable character font 1-32 dots (height) 8 dots (width) 1 HD64645/64646 • • • • • • • • • • • Versatile character attributes: reverse video, blinking, nondisplay (white), nondisplay (black) OR function: superimposing characters and graphics display Cursor with programmable height, blink rate, display position, and on/off switch Vertical Smooth Scrolling and horizontal scrolling by the character Versatile display modes programmable by mode register or external pins: display on/off, graphic or character, normal or wide, attributes, and blink enable Refresh address output for dynamic RAM 4- or 8-bit parallel data transfer between LCTC and LCD driver Recommended LCD driver HD66110ST and HD66120 (segment) HD66113T and HD66115T (common) CPU interface 80 family CMOS process Single +5 V ±10% Ordering Information Type No. Package HD64645F 80-pin plastic QFP (FP-80) HD64646FS 80-pin plastic QFP (FP-80B) 2 HD64645/64646 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 Pin Arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RA0 RA1 RA2 RA3 RA4 GND1 G/C AT LS D/S WIDE ON/OFF MODE BLE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RD WR 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 LU0 M FLM CL1 CL2 SK0 SK1 VCC2 DCLK MCLK DISPTMG CUDISP GND2 RES CS RS MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 VCC1 LD3 LD2 LD1 LD0 LU3 LU2 LU1 (Top view) 3 HD64645/64646 Pin Description Symbol Pin Number I/O Name VCC1, VCC2 17, 32 — VCC GND1, GND2 37, 59 — Ground LU0–LU3 22–25 O LCD up panel data 0–3 LD0–LD3 18–21 O LCD down panel data 0–3 CL1 28 O Clock one CL2 29 O Clock two FLM 27 O First line marker M 26 O M MA0–MA15 65–80 O Memory address 0–15 RA0–RA4 60–64 O Raster address 0–4 MD0–MD7 1–8 I Memory Data 0–7 MD8–MD15 9–16 I Memory Data 8–15 DB0–DB7 43–50 I/O Data bus 0–7 CS 39 I Chip select WR 41 I Write RD 42 I Read RS 40 I Register select RES 38 I Reset DCLK 33 I D clock MCLK 34 O M clock DISPTMG 35 O Display timing CUDISP 36 O Cursor display SK0 30 I Skew 0 SK1 31 I Skew 1 ON/OFF 53 I On/off BLE 51 I Blink enable AT 57 I Attribute G/C 58 I Graphic/character WIDE 54 I Wide LS 56 I Large screen D/S 55 I Dual/single MODE 52 I Mode 4 HD64645/64646 Pin Functions Power Supply (VCC 1, VCC2, GND) Power Supply Pin (+5 V): Connect V CC1 and V CC2 with +5V power supply circuit. Ground Pin (0 V): Connect GND1 and GND2 with 0V. LCD Interface LCD Up Panel Data (LU0–LU3), LCD Down Panel Data (LD0–LD3): LU0–LU3 and LD0–LD3 output LCD data as shown in Table 1. Clock One (CL1): CL1 supplies timing clocks for display data latch. Clock Two (CL2): CL2 supplies timing clock for display data shift. First Line Marker (FLM): FLM supplies first line marker. M (M): M converts liquid crystal drive output to AC. Memory Interface Memory Address (MA0–MA15): MA0–MA15 supply the display memory address. Raster Address (RA0–RA4): RA0–RA4 supply the raster address. Memory Data (MD0–MD7): MD0–MD7 receive the character dot data or bit-mapped data. Memory Data (MD8–MD15): MD8–MD15 receive attribute code data or bit-mapped data. MPU Interface Data Bus (DB0–DB7): DB0–DB7 send/receive data as a three-state I/O common bus. Chip Select (CS): CS selects a chip. Low level enables MPU read/write of the LCTC internal registers. Write (WR): WR receives MPU write strobe. Read (RD): RD receives MPU read strobe. Register Select (RS): RS selects registers. (Refer to Table 4.) Reset (RES): RES performs external reset of the LCTC. Low level of RES stops and zero-clears the LCTC internal counter. No register contents are affected. 5 HD64645/64646 Timing Signal D Clock (DCLK): DCLK inputs the system clock. M Clock (MCLK): MCLK indicates memory cycle; DCLK is divided by four. Display Timing (DISPTMG): DISPTMG high indicates that the LCTC is reading display data. Cursor Display (CUDISP): CUDISP supplies cursor display timing; connect with MD12 in character mode. Skew 0 (SK0)/Skew 1 (SK1): SK0 and SK1 control skew timing. Refer to Table 2. Mode Select The mode select pins ON/OFF, BLE, AT, G/C, and WIDE are ORed with the mode register (R22) to determine the mode. On/Off (ON/OFF): ON/OFF switches display on and off (high = display on). Blink Enable (BLE): BLE high level enables attribute code “blinking” (MD13) and provides normal/blank blinking of specified characters for 32 frames each. Attribute (AT): AT controls character attribute functions. Graphic/Character (G/C): G/C switches between graphic and character display mode (graphic display when high). Wide (WIDE): WIDE switches between normal and wide display mode (high = wide display, low = normal display). Large Screen (LS): LS controls a large screen. LS high provides a data transfer rate of 40 Mbits/s for a graphic display. Also used to specify 8-bit LCD interface mode. For more details, refer to Table 10. Dual/Single (D/S): D/S switches between single and dual screen display (dual screen display when high). Mode (MODE): MODE controls easy mode. MODE high sets duty ratio, maximum number of rasters, cursor start/end rasters, etc. (Refer to Table 8.) Table 1 LCD Up Panel Data and LCD Down Panel Data Single Screen Pin Name 4-Bit Data 8-Bit Data Dual Screen LU0–LU3 Data output Data output Data output for upper screen LD0–LD3 Disconnected Data output Data output for lower screen 6 HD64645/64646 Table 2 Skew Signals SK0 SK1 Skew Function 0 0 No skew 1 0 1-character time skew 0 1 2-character time skew 1 1 Prohibited combination Function Overview Main Features of HD64645/HD64646 Main features of the LCTC are: • High-resolution liquid crystal display screen control (up to 720 × 512 dots) • Software compatible with HD6845 (CRTC) • Built-in character attribute control circuit Table 3 shows how the LCTC can be used. 7 HD64645/64646 Table 3 Functions, Application, and Configuration Classification Item Description Functions Screen format • Programmable horizontal scanning cycle by the character clock period • Programmable multiplexing duty ratio from static up to 1/512 • Programmable number of vertical displayed characters • Programmable number of rasters per character row (number of vertical dots within a character row + space between character rows) • Programmable cursor display position, corresponding to RAM address • Programmable cursor height by setting display start/end rasters • Programmable blink rate, 1/32 or 1/64 frame rate Memory rewriting • Time for rewriting memory set either by specifying number of horizontal total characters or by cycle steal utilizing MCLK Memory addressing • 16-bit memory address output, up to 64 kbytes × 2 memory accessible • DRAM refresh address output • Paging by updating start address • Horizontal scrolling by the character, by setting horizontal virtual screen width • Vertical smooth scrolling by updating display start raster Character attributes • Reverse video, blinking, nondisplay (white or black), display ON/OFF CRTC compatible • Facilitates system replacement of CRT display with LCD OR function • Enables superimposing display of character screen and graphic screen LCTC configuration • Single 5 V power supply • I/O TTL compatible except RES, MODE, SK0, SK1 • Bus connectable with 80 family • CMOS process • Internal logic fully static • 80-pin flat plastic package Cursor control Paging and scrolling Application Configuration 8 HD64645/64646 Differences between HD64645 and HD64646 Figure 1 and Figure 2 show the relation between display data transfer period, when display data shift clock CL2 changes, and display data latch clock CL1. Figure 1 shows the case without skew function and Figure 2 shows the case with skew function. In Figure 1, high period between CL2 and CL1 of HD64645 overlap. HD64646 has no overlap like HD64645, and except for this overlap, HD64646 is the same as HD64645 functionally. Also for the skew function, phase relation between CL1 and CL2 changes. As Figure 2 shows, data transfer period and CL1 high period of HD64646 never overlap with the skew function. MCLK 1 2 3 4 5 15 16 DISPTMG CL1 (HD64645) MCLK × 16 CL1 (HD64646) MCLK × 11 CL2 (fCL2 = fMCLK) CL2 (fCL2 = 2fMCLK) Notes: fMCLK = Output frequency of MCLK fCL2 = Output frequency of CL2 Figure 1 Differences between HD64645 and HD64646 (No Skew) 9 HD64645/64646 MCLK 1 2 3 4 5 15 16 DISPTMG CL1 (HD64645) MCLK × 16 CL1 (HD64646) MCLK × 11 CL2 (fCL2 = fMCLK) CL2 (fCL2 = 2fMCLK) 1 Character Skew MCLK 1 2 3 4 5 15 16 DISPTMG CL1 (HD64645) MCLK × 16 CL1 (HD64646) MCLK × 11 CL2 (fCL2 = fMCLK) CL2 (fCL2 = 2fMCLK) 2 Character Skew Figure 2 Differences between HD64645 and HD64646 (Skew) 10 HD64645/64646 Internal Block Diagram Figure 3 is a block diagram of the LCTC. DCLK MCLK WR RD DISPTMG RS CS DB0–DB7 Dot counter CPMA Character counter (8 bits) CLK Address register & R/W control Skew control MCLK CMP R0 Horizontal total register (W) CMP R1 Horizontal displayed register (W) R21 Display start raster register (W) CMP R9 Maximum raster address register (W) CMP R19 R20 Multiplexing duty ratio register (W) R12 R13 Start address register (R/W) R18 Horizontal virtual screen width register (R/W) R14 R15 Cursor address register (R/W) R10 Cursor start raster register (W) R11 Cursor end raster register (W) R22 Mode register (W) CL2 R Q S R Q R S Q S CL1 CLK CLK CLK Refresh address counter (8 bits) Upper panel raster counter (5 bits) MR Down panel raster counter (5 bits) CMP 16 Multiplexing duty CLK ratio counter (9 bits) FLM Counter 1/2 M Upper panel address CLK counter (16 bits) CLK Down panel address counter (16 bits) MPX Counter control Counter control CMP MA0–MA15 MPX CMP Mode control circuit RA0–RA4 Skew control LU0–LU3 8-bit/4-bit counter LD0–LD3 G/C AT LS D/S WIDE ON/OFF MODE BLE Data conversion control Attribute control Skew circuit Input register MD0–MD15 CUDISP SK0 SK1 Figure 3 LCTC Block Diagram 11 HD64645/64646 System Block Configuration Examples Figure 4 is a block diagram of a character/graphic display system. Figure 6 shows two examples using LCD drivers. HD64645/HD64646 MPU bus DCLK CPG WR, RD G/C AT LS MA0–MA15 D/S WIDE MODE ON/OFF MCLK BLE DISPTMG SK0 SK1 Dec. Address bus CS, RS Multiplexer Memory control 2 R/W, AD R/W, AD CS CS A-RAM V-RAM Display on/off Blink enable Reset RES 8 CGROM +5V Selector 8 Mode select CUDISP D MD8–MD15 Selector D ATT DEC. Data bus Control signal bus DB0–DB7 MD0– MD7 VCC GND LU0–LU3 LD0–LD3 CL2 CL1 M RA0–RA4 FLM Char./Graph. Figure 4 Character/Graphic Display System Example 12 LCD module HD64645/64646 Interface to MPU A0–A15 RS IOE Decoder CS RD RD HD64180 MPU WR WR HD64645 HD64646 LCTC DB0–DB7 D0–D7 RES RES RESET Note: In 80 family MPUs, I/O space is separate from memory space in software. Thus the LCTC, a part of I/O, needs the ORed signals of the interface signals and IOE. So IOE and RD, and IOE and WR should be ORed to satisfy tAS, the timing of CS, RD, and WR. Interface between HD64180, HD64645 and HD64646 Figure 5 Interfacep to MPU 13 HD64645/64646 Dual screen LU0– LU3 HD66110ST E (1) HD66110ST E (2) HD66110ST E (4) 160 160 160 4 FLM HD66113T (1) 120 HD66113T (4) 120 LCD panel 640 × 480 dots CL1 CL2 M LCTC LD0– LD3 1/240 duty ratio 4 160 160 160 HD66110ST E (5) HD66110ST E (6) HD66110ST E (8) HD66110ST E (1) HD66110ST E (2) HD66110ST E (4) 160 160 160 Single screen LU0– LU3 FLM 4 HD66113T (1) 120 CL1 CL2 M LCD panel 640 × 240 dots LCTC 1/240 duty ratio HD66113T (2) 120 Figure 6 LCD Driver Examples 14 HD64645/64646 Registers Table 4 shows the register mapping. Table 5 describes their function. Table 6 shows the differences between CRTC and LCTC registers. Table 4 Registers Mapping Address Register Reg. No. Register Name CS RS 4 3 2 1 0 1 — ————— 0 0 — — — — — AR 0 1 0 0 0 0 0 R0 0 1 0 0 0 0 1 0 1 0 1 0 Data Bit Program Unit Symbol R/W — — — Address Register — — W Horizontal total characters Character* 3 Nht W R1 Horizontal displayed char.s Character Nhd W 0 1 0 0 1 R9 Maximum raster address Raster Nr W 0 1 0 1 0 R10 Cursor start raster Raster* 4 Ncs W 1 0 1 0 1 1 R11 Cursor end raster Raster Nce W 0 1 0 1 1 0 0 R12 Start address (H) Memory address — R/W 0 1 0 1 1 0 1 R13 Start address (L) Memory address — R/W 0 1 0 1 1 1 0 R14 Cursor address (H) Memory address — R/W 0 1 0 1 1 1 1 R15 Cursor address (L) Memory address 0 1 1 0 0 1 0 R18 Horizontal virtual screen width Character 0 1 1 0 0 1 1 R19 Multiplexing duty ratio (H) 0 1 1 0 1 0 0 R20 Multiplexing duty ratio (L) 0 1 1 0 1 0 1 R21 Display start raster 0 1 1 0 1 1 0 R22 Mode register Invalid — R/W Nir W Raster* 3 Ndh W Raster* 3 Ndl W Raster Nsr W —* 5 — W 7 6 5 B P 4 3 2 1 0 ON/ G/C WIDE BLE AT OFF Notes: 1. : Invalid data bits 2. R/W indicates whether write access or read access is enabled to/from each register. W: Only write accessible R/W: Both read and write accessible 3. The “value to be specified minus 1” should be programmed in these registers: R0, R1 and R20. 4. Data bits 5 and 6 of cursor start register control the cursor status as shown below (for more details, refer to page 27). B P Cursor Blink Mode 0 0 1 1 0 1 0 1 Cursor on; without blinking Cursor off Blinking once every 32 frames Blinking once every 64 frames 5. The OR of mode pin status and mode register data determines the mode. 6. Registers R2–R8, R16, and R17 are not assigned for the LCTC. Programming to these registers will be ignored. 15 HD64645/64646 Table 5 Internal Register Description Reg. No. Register Name Size (Bits) Description AR Address register 5 Specifies the internal control registers (R0, R1, R9–R15, R18–R22) address to be accessed R0 Horizontal total characters 8 Specifies the horizontal scanning period R1 Horizontal displayed characters 8 Specifies the number of displayed characters per character row R9 Maximum raster address 5 Specifies the number of rasters per character row, including the space between character rows R10 Cursor start raster 5+2 Specifies the cursor start raster address and its blink mode R11 Cursor end raster 5 Specifies the cursor end raster address R12 R13 Start address (H) Start address (L) 16 Specify the display start address R14 R15 Cursor address (H) Cursor address (L) 16 Specify the cursor display address R18 Horizontal virtual screen width 8 Specifies the length of one row in memory space for horizontal scrolling R19 R20 Multiplexing duty ratio (H) Multiplexing duty ratio (L) 9 Specify the number of rasters for one screen R21 Display start raster 5 Specifies the display start raster within a character row for smooth scrolling R22 Mode register 5 Controls the display mode Note: For more details of registers, refer to “Internal Registers.” 16 HD64645/64646 Table 6 Internal Register Comparison between LCTC and CRTC Reg. No. LCTC HD64645/HD64646 Comparison CRTC HD6845 AR Address register Equivalent to CRTC Address register R0 Horizontal total characters Horizontal total characters R1 Horizontal displayed characters Horizontal displayed characters R2 — R3 Particular to CRTC; unnecessary for LCTC Horizontal sync position Sync width R4 Vertical total characters R5 Vertical total adjust R6 Vertical displayed characters R7 Vertical sync position R8 Interface and skew R9 Maximum raster address R10 Cursor start raster Cursor start raster R11 Cursor end raster Cursor end raster R12 Start address (H) Start address (H) R13 Start address (L) Start address (L) R14 Cursor address (H) Cursor (H) R15 Cursor address (L) Cursor (L) R16 Equivalent to CRTC Particular to CRTC; unnecessary for LCTC R17 R18 Horizontal virtual screen width R19 Multiplexing duty ratio (H) R20 Multiplexing duty ratio (L) R21 Display start raster R22 Mode register Maximum raster address Light pen (H) Light pen (L) Additional registers for LCTC 17 HD64645/64646 Functional Description Programmable Screen Format Figure 7 illustrates the relation between LCD display screen and registers. Figure 8 shows a timing chart of signals output from the LCTC in mode 5 as an example. Horizontal total characters (R0) (R21) Start raster Horizontal displayed characters (R1) CPU memory write time Display period Horizontal character pitch Display start raster address (R21) Maximum raster address (R9) (R19, R20) Multiplexing duty ratio (single) Multiplexing duty ratio × 2 (dual) Start address (R12) (1 character) Figure 7 Relation between Display Screen and Registers 18 HD64645/64646 MCLK DISPTMG CUDISP (Latch timing) MA0–MA15 0 1 2 3 4 5 Nhd-4 Nhd-3 Nhd-2 Nhd-1 Ref-1 Ref-2 Ref-3 Ref-4 Ref-14 Ref-15 Ref-16 Nht-2 Nht-1 Nht RA0–RA4 MCLK × 16 FLM M CL1 MCLK × 16 * CL2 00112233 4455 LU1 00112233 4455 LU2 00112233 4455 LU3 00112233 4455 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 Nhd-1 Nhd-2 Nhd-2 Nhd-3 Nhd-3 Nhd-4 LU0 Nhd-1 0 1 5 1 5 1 5 1 2 6 2 6 2 6 2 3 7 3 7 3 7 3 LD0 LD1 LD2 LD3 Note: * Relation between CL1 and CL2 in the case of HD64646 is difference from one shown in this chart. Refer to “Difference between HD64645 and HD64646.” Figure 8 LCTC Timing Chart (In Mode 5: Single Screen, 4-Bit Transfer, Normal Character Display) 19 HD64645/64646 Cursor Control The following cursor functions (Figure 9) can be controlled by programming specific registers. • Cursor display position • Cursor height • Cursor blink mode A cursor can be displayed only in character mode. Also, CUDISP pin must be connected to MD12 pin to display a cursor. Cursor start raster Cursor height Cursor end raster Figure 9 Cursor Display 20 HD64645/64646 Character Mode and Graphic Mode The LCTC supports two types of display modes; character mode and graphic mode. Graphic mode 2 is provided to utilize software for a system using the CRTC (HD6845). The display mode is controlled by an OR between the mode select pins (D/S, G/C, LS, WIDE, AT) and mode register (R22). Character Mode: character mode displays characters by using CG-ROM. The display data supplied from memory is accessed in 8-bit units. A variety of character attribute functions are provided, such as reverse video, blinking, nondisplay (white or black), by storing the attribute data in attribute RAM (A-RAM). Figure 10 illustrates the relation between character display screen and memory contents. Graphic Mode 1: Graphic mode 1 directly displays data stored in a graphic memory buffer. The display data supplied from memory is accessed in 16-bit units. Character attribute functions or wide mode are not provided. Figure 11 illustrates the relation between graphic display screen and memory contents. Graphic Mode 2: Graphic mode 2 utilizes software for a system using the CRTC (HD6845). The display data supplied from memory is accessed in 16-bit units. Character attribute functions or wide mode are not provided. The same memory addresses are output repeatedly the number of times specified by maximum raster register (R9). The raster address is output in the same way as in character mode. Reverse video 1st row VRAM (char. code) 8-bit 41 42 43 ARAM (Attr. code) 8-bit 08 20 00 2nd row 44 45 46 00 00 00 Blinking Start address 1st row 2nd row Reverse video Blinking Figure 10 Relation between Character Screen and Memory Contents 21 HD64645/64646 Horizontal Virtual Screen Width Horizontal virtual screen width can be specified by the character in addition to the number of horizontal displayed characters (Figure 12). The display screen can be scrolled in any direction by the character, by setting the horizontal virtual screen width and updating the start address. This function is enabled by programming the horizontal virtual screen width register (R18). Figure 13 shows an example. 1st line 2nd line M D VRAM 7 M MM D D ARAM D 8 0 15 1st line 2nd line VRAM 8-bit ARAM 8-bit FF 33 55 00 CC AA Display screen Figure 11 Relation between Graphic Screen and Memory Contents Display screen Horizontal displayed characters (R1) Horizontal virtual screen width (R18) Figure 12 Horizontal Virtual Screen Width 22 HD64645/64646 R18 R1 Example: R18 (horizontal virtual screen width) = 10 R1 (horizontal displayed characters) = 5 Start address 0 1 2 3 10 11 12 13 N e w L C T 4 5 6 7 8 9 C Displayed area Performing horizontal scroll by updating the start address 0 to 4 0 1 2 3 10 11 12 13 N e w L C T 4 5 6 7 8 9 C Figure 13 Example of Horizontal Scroll by Setting Horizontal Virtual Screen Width 23 HD64645/64646 Smooth Scroll Vertical smooth scrolling (Figure 14) is performed by updating the display start raster, as specified by the start raster register (R21). This function is offered only in character mode. Wide Display The character to be displayed can be doubled in width, by supplying the same data twice (Figure 15). This function is offered only in character mode, and controlled either by bit 2 of the mode register (R22) or by the WIDE pin. Raster 0 address 1 1 2 3 4 5 6 7 2 3 4 5 6 7 2 3 4 5 6 7 Display start raster address (R21) = 0 (R21) = 1 (R21) = 2 Figure 14 Example of Smooth Scroll by Setting Display Start Raster Address 1 2 3 4 5 6 WIDE = Low 7 8 1 1 2 2 3 3 4 5 5 WIDE = High Figure 15 Example of Wide Display 24 4 6 6 7 7 8 8 HD64645/64646 Attribute Functions A variety of character attribute functions such as reverse video, blinking, nondisplay (white) or nondisplay (black) can be implemented by storing the attribute data in A-RAM (attribute RAM). Figure 16 shows a display example using each attribute function. The attribute functions are offered only in character mode, and controlled either by bit 0 of the mode register (R22) or the AT pin. As shown in Figure 17, a character attribute can be specified by placing the character code on MD0–MD7, and the attribute code on MD11–MD15. MD8–MD10 are invalid. 1. Black 2. White 3. Blinking 4. Cursor 5. Reverse video Figure 16 Display Example Using Attribute Functions 25 HD64645/64646 MD Input 15 14 13 12 11 10–8 7–0 Function Nondisplay (black) Nondisplay (white) Blinking Cursor Reverse video *** Character code Note: *** Invalid Figure 17 Attribute Code OR Function — Superimposing Characters and Graphics The OR function (Figure 18) generates the OR of the data entered into MD0–MD7 (e.g. character data) and the data into MD8–MD15 (e.g. graphic data) in the LCTC and transfers this data as 1 byte. This function is offered only in character mode, and controlled by bit 0 of the mode register (R22) or by the AT pin. Any attribute functions are disabled when using the OR function. Graphic data (character data) MD15 MD14 MD9 Character data (graphic data) MD8 MD7 MD6 MD1 MD0 0 1 8-bit data 6 7 Figure 18 OR Function 26 HD64645/64646 DRAM Refresh Address Output Function The LCTC outputs the address for DRAM refresh while CL1 is high, as shown in Figure 19. The 16 refresh addresses per scanned line are output 16 times, from $00–$FF. Skew Function The LCTC can specify the skew (delay) for CUDISP, DISPTMG, CL2 outputs and MD inputs. If buffer memory and character generator ROM cannot be accessed within one horizontal character display period, the access is retarded to the next cycle by inserting a latch to memory address output and buffer memory output. The skew function retards the CUDISP, DISPTMG, CL2 outputs, and MD inputs in the LCTC to match phase with the display data signal. By utilizing this function, a low-speed memory can be used as a buffer RAM or a character generator ROM. This function is controlled by pins SK0 and SK1 as shown in Table 7. Table 7 Skew Function SK0 SK1 Skew Function 0 0 No skew 1 0 1 character time skew 0 1 2 character time skew 1 1 Inhibited combination DISPTMG CL1 MCLK 1 MA0–MA7 Display memory address 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DRAM refresh address Display memory address Figure 19 DRAM Refresh Address Output 27 HD64645/64646 Easy Mode This mode utilizes software for systems using the CRTC (HD6845). By setting MODE pin to high, the display mode and screen format are fixed as shown in Table 8. With this mode, software for a CRT screen can be utilized in a system using the LCTC, without changing the BIOS. Automatic Correction of Down Panel Raster Address When the LCTC mode is set for character display and dual screen, memory addresses (MA) and raster addresses (RA) are output in such a way as to keep continuity of a display spread over the two panels. Therefore users can use the LCTC without considering the multiplexing duty ratio (the number of vertical dots of a screen) or the character font. (See Figure 20.) Table 8 Fixed Values in Easy Mode Reg. No. Register Name Fixed Value (Decimal) R9 Maximum raster address 7 R10 Cursor start raster 6 R11 Cursor end raster 7 R18 Horizontal virtual screen width Same value as (R1) R19 Multiplexing duty ratio (H) 99 (in dual screen mode) R20 Multiplexing duty ratio (L) 199 (in single screen mode) R21 Display start raster 0 R22 Mode register 0 Up panel ABC Characters are continuous in spite of the break of a screen. Down panel Figure 20 Example of the Display in the Character Mode 28 HD64645/64646 System configuration and Mode Setting LCD System Configuration The screen configuration, single or dual, must be specified when using the LCD system (Figure 21). Using the single screen configuration, you can construct an LCD system with lower cost than a dual screen system, since the required number of column drivers is smaller and the manufacturing process for mounting them is simpler. However, there are some limitations, such as duty ratio, breakdown voltage of a driver, and display quality of the liquid crystal, in single screen configuration. Thus, a dual screen configuration may be more suitable to an application. The LCTC also offers an 8-bit LCD data transfer function to support an LCD screen with a smaller interval of signal input terminals. For a general size LCD screen, such as 640 × 200 single, or 640 × 400 dual, the usual 4-bit LCD data transfer is satisfactory. Hardware Configuration and Mode Setting The LCTC supports the following hardware configurations: • Single or dual screen configuration • 4-or 8-bit LCD data transfer and the following screen format: • Character, graphic 1, or graphic 2 display • Normal or wide display (only in character mode) • OR or attribute display (only in character mode) Also, the LCTC supports up to 40 Mbits/s of large screen mode (mode 13) for large screen display. This mode is provided only in graphic 1 mode. Table 9 shows the mode selection method according to hardware configuration and screen format. Table 10 shows how they are specified. 29 HD64645/64646 4 4 or 8 Data Column driver (upper panel) Row driver Row driver Data Column driver LCD upper panel LCD lower panel Single Screen Data 4 Column driver (lower panel) Dual Screen Figure 21 Hardware Configuration According to Screen Format Table 9 Mode Selection Hardware Configuration Screen Format LCD Data Transfer Screen Configuration Screen Size Character/ Graphic Normal/ Wide Attribute/ OR 4-bit Single Normal Character Normal Wide Dual 8-bit Single Normal Maximum Data Transfer Speed (Mbps) Mode No. AT OR 20 5 AT OR 10 6 Graphic 1 20 7 Graphic 2 20 8 Character Normal AT OR 20 1 Wide AT OR 10 2 Graphic 1 20 3 Graphic 2 20 4 Large Graphic 1 40 13 Normal Character Normal AT OR 20 9 Wide AT OR 10 10 Graphic 1 20 11 Graphic 2 20 12 Note: Maximum data transfer speed indicates amount of the data read out of a memory. Thus, the data transfer speed sent to the LCD driver in wide function is 20 Mbps. 30 HD64645/64646 Mode List Table 10 Mode List Pin Name No. Mode Name D/S G/C LS WIDE AT 1 1 0 0 0 0 1 0 0 0 1 2 Dual-screen character Dual-screen wide character 1 0 0 1 0 1 0 0 1 1 3 Dual-screen graphic 1 1 1 0 0 1 4 Dual-screen graphic 2 1 1 0 0 0 5 Single-screen character 0 0 0 0 0 0 0 0 0 1 6 0 0 0 1 0 0 0 0 1 1 7 Single-screen graphic 1 0 1 0 0 1 8 Single-screen graphic 2 0 1 0 0 0 9 8-bit character 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 10 Single-screen wide character 8-bit wide character 11 8-bit graphic 1 0 1 1 0 1 12 8-bit graphic 2 0 1 1 0 0 13 Large screen 1 1 1 0 1 Screen Config. Graphic/ Data Wide Character Transfer Display Dual screen Character 4-bit ×2 Normal Attribute OR AT Wide OR AT Single screen Graphic — — Character 4-bit Normal OR AT Wide OR AT Single screen Graphic — — Character 8-bit Normal OR AT Wide OR AT Graphic Dual screen — — 4-bit ×2 The LCTC display mode is determined by pins D/S (pin 55), G/C (pin 58), LS (pin 56), WIDE (pin 54), and AT (pin 57). As for G/C, WIDE, and AT, the OR is taken between data bits 0, 2, and 3 of the mode register (R22). The display mode can be controlled by either one of the external pins or the data bits of R22. Note: The above 5 pins have 32 status combinations (high and low). Any combinations other than the above are prohibited, because they may cause malfunctions. If you set an prohibited combination, set the right combination again. 31 HD64645/64646 Internal Registers The HD64645/HD64646 has one address register and fourteen data registers. In order to select one out of fourteen data registers, the address of the data register to be selected must be written into the address register. The MPU can transfer data to/from the data register corresponding to the written address. To be software compatible with the CRTC (HD6845), registers R2–R8, R16, and R17, which are not necessary for an LCD are defined as invalid for the LCTC. Address Register (AR) AR register (Figure 22) specifies one out of 14 data registers. Address data is written into the address register when RS is low. If no register corresponding to a specified address exists, the address data is invalid. Horizontal Total Characters Register (R0) R0 register (Figure 23) specifies a horizontal scanning period. The total number of horizontal characters less 1 must be programmed into this 8-bit register in character units. Nht indicates the horizontal scanning period including the period when the CPU occupies memory (total number of horizontal characters minus the number of horizontal displayed characters). Its units are, then, converted from time into the number of characters. This value should be specified according to the specification of the LCD system to be used. Note the following restrictions Nhd + 16 ≤ Nht + 1 m Mode No. m 5, 9 1 1, 6, 7, 8, 10, 11, 12, 13 2 2, 3, 4 4 Horizontal Displayed Characters Register (R1) R1 register (Figure 24) specifies the number of characters displayed per row. The horizontal character pitches are 8 bits for normal character display and 16 dots for wide character display and graphic display. Nhd must be less than the total number of horizontal characters. 32 HD64645/64646 Maximum Raster Address Register (R9) R9 register (Figure 25) specifies the number of rasters per row in characters mode, consisting of 5 bits. The programmable range is 0 (1 raster/row) to 31 (32 rasters/row). Data Bit 7 6 5 4 3 Program Unit R/W 2 1 0 — — — — Register address W Figure 22 Address Register Data Bit 7 6 5 4 3 Program Unit R/W 2 1 0 Character Nht (total characters – 1) W Figure 23 Horizontal Total Characters Register Data Bit 7 6 5 4 3 Program Unit R/W 2 1 0 Nhd (displayed characters) Character W Figure 24 Horizontal Displayed Characters Register Data Bit 7 6 5 — — — 4 3 Program Unit R/W 2 1 0 Nr Raster W Figure 25 Maximum Raster Address Register Cursor Start Raster Register (R10) R10 register (Figure 26) specifies the cursor start raster address and its blink mode. Refer to Table 11. A A 32- or 64-frame 33 HD64645/64646 Cursor End Raster Register (R11) R11 register (Figure 27) specifies the cursor end raster address. Start Address Register (H/L) (R12/R13) R12/R13 register (Figure 28) specifies a buffer memory read start address. Updating this register facilitates paging and scrolling. R14/R15 register can be read and written to/from the MPU. Cursor Address Register (H/L) (R14/R15) R14/R15 register (Figure 29) specifies a cursor display address. Cursor display requires setting R10 and R11, and CUDISP should be connected with MD12 (in character mode). This register can be read from and written to the MPU. Horizontal Virtual Screen Width Register (R18) R18 register (Figure 30) specifies the memory width to determine the start address of the next row. By using this register, memory width can be specified larger than the number of horizontal displayed characters. Updating the display start address facilitates scrolling in any direction within a memory space. The start address of the next row is that of the previous row plus Nir. If a larger memory width than display width is unnecessary, Nir should be set equal to the number of horizontal displayed characters. Table 11 Cursor Blink Mode B P Cursor Blink Mode 0 0 Cursor on; without blinking 0 1 Cursor off 1 0 Blinking once every 32 frames 1 1 Blinking once every 64 frames Data Bit 7 6 — B 5 4 3 Program Unit R/W 2 1 0 P Ncs (raster address) Raster W Figure 26 Cursor Start Raster Register 34 HD64645/64646 Data Bit 7 6 5 4 3 Program Unit R/W 2 1 0 — — — Nce (raster address) Raster W Figure 27 Cursor End Raster Register Data Bit 7 6 5 4 3 Program Unit R/W 2 1 0 Memory address (H) (R12) Memory address (L) (R13) Memory address R/W Figure 28 Start Address Register Data Bit 7 6 5 4 3 Program Unit R/W 2 1 0 Memory address (H) (R14) Memory address (L) (R15) Memory address R/W Figure 29 Cursor Address Register Multiplexing Duty Ratio Register (H/L) (R19/R20) R19/R20 register (Figure 31) specifies the number of vertical dots of the display screen. The programmed value differs according to the LCD screen configuration. In single screen configuration: (Programmed value) = (Number of vertical dots) – 1 In dual screen configuration: (Programmed value) = (Number of vertical dots) –1 2 Display Start Raster Register (R21) R21 register (Figure 32) specifies the start raster of the character row displayed on the top of the screen. The programmed value should be equal or less than the maximum raster address. Updating this register allows smooth scrolling in character mode. 35 HD64645/64646 Mode Register (R22) The Or of the data bits of R22 (Figure 33) register and the external terminals of the same name determines a particular mode (Figure 34). Data Bit 7 6 5 4 3 Program Unit R/W 2 1 0 Character Nir (No. of chars. of virtual width) W Figure 30 Horizontal Virtual Screen Width Register Data Bit 7 6 5 4 3 Program Unit R/W 2 1 0 — Raster — — — — — — (R19) Ndh* W Ndl (Number of rasters – 1) (R20) Note: * Number of rasters Figure 31 Multiplexing Duty Ratio Register Data Bit 7 6 5 — — — 4 3 Program Unit R/W 2 1 0 Raster Raster address W Figure 32 Display Start Raster Register Data Bit 7 6 5 — — — 4 3 ON/OFF G/C Program Unit R/W 2 1 0 WIDE BLE AT — Figure 33 Mode Register 36 W HD64645/64646 AT (data bit 0) BLE (data bit 1) WIDE (data bit 2) G/C (data bit 3) ON/OFF (data bit 4) Mode register (R22) ON/OFF (pin 53) G/C (pin 58) WIDE (pin 54) BLE (pin 51) AT (pin 57) Notes: 1. AT (valid only when G/C is low (character mode)) AT = High: Attribute functions enabled, OR function disabled. AT = Low: OR function enabled, attribute functions disabled. 2. BLE (valid only when G/C is low (character mode)) BLE = High: Blinking enable on the character specified by attribute RAM BLE = Low: No blinking 3. WIDE (valid only when G/C is low (character mode)) WIDE = High: Wide display enabled WIDE = Low: Normal display 4. G/C G/C = High: Graphic 1 display (when AT = low) or graphic 2 display (when AT = high) G/C = Low: Character display 5. ON/OFF ON/OFF = High: Display on state ON/OFF = Low: Display off state Figure 34 Correspondence between Mode Register and External Pins 37 HD64645/64646 Restrictions on Programming Internal Registers Note when programming that the values you can write into the internal registers are restricted as shown in Table 12. Table 12 Restrictions on Writing Values into the Internal Registers Function Restrictions Register Display format 1 < Nhd < Nht + 1 ≤ 256 16 ≤ Nht + 1 Nhd + m *1 R0, R1 (No. of vertical dots) × (No. of horizontal dots) × (frame frequency; fFRM) ≤ (data transfer speed; V) 1 *2 8 *3 × (Nd + 1) × Nhd × fFRM ≤ V 2 16 R1, R19, R20 Nhd ≤ Nir R1, R18 0 ≤ Ndi ≤ 511 R19, R20 0 ≤ Ncs ≤ Nce R10, R11 Nce ≤ Nr R10, R9 Smooth scroll Nsr ≤ Nr R21, R9 Memory width set 0 ≤ Nir ≤ 255 R18 Cursor control Notes: 1. m varies according to the modes. See the following table. Mode No. m 5, 9 1 1, 6, 7, 8, 10, 11, 12, 13 2 2, 3, 4 4 2. Set 1 when an LCD screen is a single screen, and set 2 when dual. Modes are classified as shown in the following table. Mode No. Value 5, 6, 7, 8, 9, 10, 11, 12 1 1, 2, 3, 4, 13 2 3. Set 8 when a character is constructed with 8 dots, and set 16 when with 16 dots. Modes are classified as shown in the following table. 38 Mode No. Value 1, 5, 9 8 2, 3, 4, 6, 7, 8, 10, 11, 12, 13 16 HD64645/64646 Reset RES pin determines the internal state of LSI counters and the like. This pin does not affect register contents nor does it basically control output terminals. Reset is defined as follows (Figure 35): • • • • At reset: the time when RES goes low During reset: the period while RES remains low After reset: the period on and after the RES transition from low to high Make sure to hold the reset signal low for at least 1 µs RES pin should be pulled high by users during operation. Reset State of Pins RES pin does not basically control output pins, and operates regardless of other input pins. 1. Preserve states before reset LU0–LU3, LD0–LD3, FLM, CL1, RA0–RA4 2. Fixed at high level MLCK 3. Preserve states before reset or fixed at low level according to the timing when the reset signal is input DISPTMG, CUDISP, MA0–MA15 4. Fixed at high or low according to mode CL2 5. Unaffected DB0–DB7 Reset State of Registers RES pin does not affect register contents. Therefore, registers can be read or written even during a reset state; their contents will be preserved regardless of reset until they are rewritten to. Notes for HD64645/HD64646 1. The HD64645/HD64646 are CMOS LSIs, and it should be noted that input pins must not be left disconnected, etc. 2. At power-on, the state of internal registers becomes undefined. The LSI operation is undefined until all internal registers have been programmed. 39 HD64645/64646 RES VCC – 0.5V 0.8V 1 µs min During reset At reset Figure 35 Reset Definition 40 After reset HD64645/64646 Absolute Maximum Ratings Item Symbol Value Note Supply voltage VCC –0.3 to +7.0V 2 Terminal voltage Vin –0.3 to VCC + 0.3V 2 Operating temperature Topr –20°C to +75°C Storage temperature Tstg –55°C to +125°C Notes: 1. Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions (VCC = 5.0V ± 10%, GND = 0V, Ta = –20°C to +75°C). If these conditions are exceeded, it could affect reliability of LSI. 2. With respect to ground (GND = 0V) 41 HD64645/64646 Electrical Characteristics DC Characteristics (VCC = 5.0V ±10%, GND = 0V, Ta = –20°C to +75°C, unless otherwise noted) Item Input high voltage Symbol Min VIH VCC – 0.5 VCC + 0.3 V DCLK, ON/OFF 2.2 VCC + 0.3 V All others 2.0 VCC + 0.3 V VIL –0.3 0.8 VOH 2.4 V I OH = –400 µA VCC – 0.8 V I OH = –400 µA 0.4 V I OL = 1.6 mA 0.8 V I OL = 400 µA RES, MODE, SK0, SK1 Input low voltage All others Output high voltage TTL interface* 1 Output low voltage TTL interface Input leakage current All inputs except DB0–DB7 CMOS interface* 1 VOL CMOS interface Typ Max Unit Test Condition V I IL –2.5 +2.5 µA Three state DB0–DB7 (off-state) leakage current I TSL –10 +10 µA Current dissipation*2 I CC 10 mA Notes: 1. TTL Interface; MA0–MA15, RA0–RA4, DISPTMG, CUDISP, DB0–DB7, MCLK C-MOS Interface; LU0–LU3, LD0–LD3, CL1, CL2, M, FLM 2. Input/output current is excluded. When input is at the intermediate level with CMOS, excessive current flows through the input circuit to power supply. Input level must be fixed at high or low to avoid this condition. 3. If the capacitive loads of LU0–LU3 and LD0–LD3 exceed the rating, noise over 0.8 V may be produced on CUDISP, DISPTMG, MCLK, FLM and M. In case the loads of LU0–LU3 and LD0– LD3 are larger than the ratings, supply signals to the LCD module through buffers. 42 HD64645/64646 AC Characteristics CPU Interface (VCC = 5.0V ± 10%, GND = 0V, Ta = –20°C to +75°C, unless otherwise noted) Item Symbol Min RD high level width t WRDH RD low level width Unit Figure 190 ns 36 t WRDL 190 ns WR high level width t WWRH 190 ns WR low level width t WWRL 190 ns CS, RS setup time t AS 0 ns CS, RS hold time t AH 0 ns DB0–DB7 setup time t DSW 100 ns DB0–DB7 hold time t DHW 0 ns DB0–DB7 output delay time t DDR DB0–DB7 output hold time t DHR CS RS Max 150 ns 20 ns 2.0V 0.8V tAS RD Typ tWRDL tAH tAH tAS 2.0V 0.8V tWRDH tWWRH tWWRL 2.0V 0.8V WR tDDR 2.4V DB0–DB7 0.4V tDHR Output tDSW 2.0V tDHW Input 0.8V Figure 36 CPU Interface 43 HD64645/64646 Memory Interface (VCC = 5.0V ± 10%, GND = 0V, Ta = –20°C to +75°C, unless otherwise noted) Item Symbol Min Typ Max Unit Figure DCLK cycle time t CYCD 100 — — ns 37 DCLK high level width t WDH 30 — — ns DCLK low level width t WDL 30 — — ns DCLK rise time t Dr — — 20 ns DCLK fall time t Df — — 20 ns MCLK delay time t DMD — — 60 ns MCLK rise time t Mr — — 30 ns MCLK fall time t Mf — — 30 ns MA0–MA15 delay time t MAD — — 150 ns MA0–MA15 hold time t MAH 10 — — ns RA0–RA4 delay time t RAD — — 150 ns RA0–RA4 hold time t RAH 10 — — ns DISPTMG delay time t DTD — — 150 ns DISPTMG hold time t DTH 10 — — ns CUDISP delay time t CDD — — 150 ns CUDISP hold time t CDH 10 — — ns CL1 delay time t CL1D — — 150 ns CL1 hold time t CL1H 10 — — ns CL1 rise time t CL1r — — 50 ns CL1 fall time t CL1f — — 50 ns MD0–MD15 setup time t MDS 30 — — ns MD0–MD15 hold time t MDH 15 — — ns 44 HD64645/64646 tCYCD tWDH tDf DCLK tDr 2.2V 0.8V tWDL tDMD tDMD MCLK 2.4V 0.4V tMr tMf tMAH tMAD 2.4V MA0–MA15 0.4V tRAD tRAH 2.4V RA0–RA4 0.4V tDTH tDTD 2.4V DISPTMG 0.4V tCDH tCDD 2.4V CUDISP 0.4V tCL1D CL1 tCL1H VCC – 0.8V 0.8V tCL1r tCL1f tMDS tMDH 2.0V MD0–MD15 (input) 0.8V Figure 37 Memory Interface 45 HD64645/64646 LCD Interface 1 (HD64645) (VCC = 5.0V ± 10%, GND = 0V, Ta = –20°C to +75°C) Item Symbol Min Typ Max Unit Figure Display data setup time t LDS 50 — — ns 38 Display data hold time t LDH 100 — — ns CL2 high level width t WCL2H 100 — — ns CL2 low level width t WCL2L 100 — — ns FLM setup time t FS 500 — — ns FLM hold time t FH 300 — — ns CL1 rise time t CL1r — — 50 ns CL1 fall time t CL1f — — 50 ns CL2 rise time t CL2r — — 50 ns CL2 fall time t CL2f — — 50 ns Note: At f CL2 = 3 MHz VCC – 0.8V LU0–LU3 LD0–LD3 0.8V tLDS tLDH CL2 VCC – 0.8V 0.8V tWCL2H tWCL2L tCL2f tCL2r VCC – 0.8V CL1 0.8V tFS tCLIr FLM tCLIf VCC – 0.8V 0.8V Figure 38 LCD Interface 46 tFH HD64645/64646 LCD Interface 2 (HD64646 at fCL2 = 3 MHz) (VCC = 5.0V ± 10%, GND = 0V, Ta = –20°C to +75°C) Item Symbol Min Typ Max Unit Figure FLM setup time t Fs 500 — — ns 39 FLM hold time t FH 300 — — ns M delay time t DM — — 200 ns CL1 high level width t CL1H 300 — — ns Clock setup time t SCL 500 — — ns Clock hold time t HCL 100 — — ns Phase difference 1 t PD1 100 — — ns Phase difference 2 t PD2 500 — — ns CL2 high level width t CL2H 100 — — ns CL2 low level width t CL2L 100 — — ns CL2 rise time t CL2r — — 50 ns CL2 fall time t CL2f — — 50 ns Display data setup time t LDS 80 — — ns Display data hold time t LDH 100 — — ns Display data delay time t LDD — — 30 ns LCD Interface 3 (HD64646 at fCL2 = 5 MHz) (VCC = 5.0V ± 10%, GND = 0V, Ta = –20°C to +75°C) Item Symbol Min Typ Max Unit Figure FLM setup time t Fs 500 — — ns 39 FLM hold time t FH 200 — — ns M delay time t DM — — 200 ns CL1 high level width t CL1H 300 — — ns Clock setup time t SCL 500 — — ns Clock hold time t HCL 100 — — ns Phase difference 1 t PD1 70 — — ns Phase difference 2 t PD2 500 — — ns CL2 high level width t CL2H 50 — — ns CL2 low level width t CL2L 50 — — ns CL2 rise time t CL2r — — 50 ns CL2 fall time t CL2f — — 50 ns Display data setup time t LDS 30 — — ns Display data hold time t LDH 30 — — ns Display data delay time t LDD — — 30 ns 47 HD64645/64646 VCC – 0.8V 0.8V FLM tFH tFS CL1 VCC – 0.8V 0.8V tDM VCC – 0.8V 0.8V M tPD1 tHCL tCL1H VCC – 0.8V 0.8V tSCL CL1 tPD2 tCL2f tCL2r CL2 tLDD LU0–LU4 LD0–LD4 tLDS tCL2L tLDH VCC – 0.8V 0.8V Figure 39 LCD Interface 48 tCL2H HD64645/64646 Load Circuit TTL Load Terminal RL R C Remarks DB0–DB7 2.4 kΩ 11 kΩ 130 pF tr, tf: Not specified MA0–MA15, RA0–RA4, DISPTMG, CUDISP 2.4 kΩ 11 kΩ 40 pF MCLK 2.4 kΩ 11 kΩ 30 pF tr, tf: Specified 5.0V RL All diodes: 1S2074 H R C Capacitive Load Terminal C Remarks CL2 150 pF tr, tf: Specified CL1 200 pF LU0–LU3, LD0–LD3, M 150 pF FLM 50 pF tr, tf: Not specified C Refer to user’s manual (No. 68-1-160) and application note (No. ADE-502-003) for detail of this product. 49 HD64645/64646 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 50