HITACHI HD66206TE

HD66206
(80-Channel Column/Common Driver for Middle- or Large-sized
Liquid Crystal Panel)
Rev 0.2
February 1996
Description
The HD66206 is an 80-channel LCD driver, which is used for liquid crystal dot matrix display. This
product can drive various types of liquid crystal displays, from small-sized to monochrome VGA-sized
displays. Since this product can function as a column and a common driver, an LCD panel can be
configured only with this product.
Features
•
•
•
•
•
•
•
•
•
•
Logic power supply voltage: 2.7 to 5.5V
Display duty: 1/16 (1/5 bias) to 1/240
80 liquid crystal display drive circuits
Liquid crystal display drive voltage: 6 to 28V
Data transfer speed
 8 MHz max (at 5-V operation)
 6.5 MHz max (at 3-V operation)
Chip enable signal automatic generation
Standby function
Controllers that can be used with
 HD64645/HD64646 (LCTC series)
 HD66841 (LVIC series)
Packages
 TFP-100B
 No package (bare chip)
CMOS process
146
HD66206
Ordering information
Type name
Package
HD66206TE
TFP-100B
HCD66206
Bare chip
147
HD66206
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Y52
Y51
Y50
Y49
Y48
Y47
Y46
Y45
Y44
Y43
Y42
Y41
Y40
Y39
Y38
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
HD66206TE
(TFP-100B)
(Top view)
Y78
Y79
Y80
E
V1
V2
V3
V4
VEE
M
CL1
GND
SHL
VCC
FCS
TEST
DISPOFF
D3
D2
D1R
D0L
CL2
CAR
Y1
Y2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Y53
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Y71
Y72
Y73
Y74
Y75
Y76
Y77
Figure 1 Pin Arrangement (HD66206TE)
148
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
Y19
Y18
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y8
Y7
Y6
Y5
Y4
Y3
HD66206
Block Diagram
Y80Y79Y78Y77Y76
V1
M
V2 V3
Liquid crystal display drive circuit
V4
80-bit latch circuit
CL1
D0L
D1R
D2
D3
Y1
Data
conversion
circuit
80-bit bi-directional shift register
(also used as a latch circuit)
Selector
FCS
Operating mode
switchin circuit
E
TEST
Counter
CAR
Test input
CL2
SHL
Figure 2 Block Diagram
149
HD66206
Block Functions
Liquid crystal display drive circuit
Generates one of four levels V1 to V4 to the output pin to drive the liquid crystal display according to the
combination of data of the 80-bit latch circuit and the M signal.
80-bit latch circuit
Latches data of the 80-bit bi-directional shift register (also used as a latch circuit) at the falling edge of
CL1, and transmits it to the liquid crystal display drive circuit.
80-bit bi-directional shift register (also used as a latch circuit)
When FCS is low, this register functions as an 80-bit shift register. At this time, D0L and D1R are used
as data input/output pins. When FCS is high, this register functions as a 20 × 4-bit unit latch circuit. At
this time, data that is input in parallel to data input pin D0L, D1R, D2 and D3 is converted to 4-bit data,
and then is latched to this register according to the latch signal generated by the selector.
Data conversion circuit
When FCS is low, D0L and D1R are used as data input/output pins. When FCS is high, D0L, D1R, D2,
and D3 are input data.
Selector
Decodes output data from the counter and generates a latch signal. Functions when latching data at
serial-latch operation (when FCS is high). At this time, after 80 bits of data Y1 to Y80 are completely
latched, the operation of the selector terminates. Even if input data changes, data in the latch circuit is
maintained.
Operating mode switching circuit
Switches common driver operation (when FCS is low) and column driver operation (when FCS is high).
150
HD66206
Pin Function
Table 1
Pin Functions
Classification
Symbol
Input/
Pin No. Pin Name Output Function
Power supply
VCC
GND
VEE
39
37
34
VCC
GND
VEE
—
V1
V2
V3
V4
30
31
32
33
V1
V2
V3
V4
Input
Power supply voltage for liquid crystal display
drive level.
See Figure 3.
CL1
36
Clock 1
Input
Column driver data latch signal. Data is
latched at the falling edge of this signal. Set
this signal low in common driver operation.
CL2
47
Clock 2
Input
In column driver operation, used as a display
data latch signal.
In common driver operation, used as a line
selection data shift signal.
In both operations, this signal is valid at its
falling edge.
M
35
M
Input
AC conversion signal for liquid crystal display
drive output.
SHL
38
Shift left
Input
Control signal for inverting data output
destination.
Control signal
VCC–GND: Logic power supply
VCC–VEE: Power supply for driving the liquid
crystal display.
1. In column driver operation
See Figure 4.
2. In common driver operation
SR1, SR2, SR3, ...., SR80 correspond to Y1,
Y2, Y3, ...., Y80 outputs.
When SHL is low, data is input to D0L pin and
output from D1R pin. D2 and D3 are set low.
When SHL is high, the relationships between
D0L and D1R are reverse.
See Table 2.
(
29
Enable
Input
When FCS is high, data latch starts by setting
the ( signal low.
When FCS is low, set the ( signal high.
The relationships between the ( signal, the
FCS signal, data latch operation, and driver
function are as show in Table 3
151
HD66206
Table 1
Pin Function (cont)
Classification Symbol
Control signal
Liquid crystal
display drive
output
152
Input/
Output Function
Pin No.
Pin Name
&$5
48
Carry
',632))
42
Display off Input
When this signal is low, liquid crystal display
drive output is set at V1 level and liquid
crystal display is turned off. At this time,
internal display data is not affected. When
this signal is high, the operation returns to
the normal status.
D0L
D1L
46
45
Data0 (L)
Data1 (R)
Input/
output
D2
D3
44
43
Data2
Data3
Input
In column driver operation, input display
data to D0L, D1R, D2, and D3 pins.
In common driver operation, when SHL is
high, D0L and D1R pins are display data
output and input pins, respectively, and vice
versa when SHL is low. At this time, set D2
and D3 low.
When display data is high, liquid crystal
display drive output is selection level and
the display is on, and when display data is
low, they are non-selection level and off,
respectively.
FCS
40
Function
select
Input
Control signal to select each operating
mode.
When the FCS pin is high, the operating
mode is column driver, and when it is low,
the operation mode is common driver.
TEST
41
TEST
Input
Test pin. Set this pin low.
Y1 to Y80
49 to 100
1 to 28
Y1 to Y80
Output
Liquid crystal display drive output.
One of four levels V1 to V4 is output
according to the combination of the M
signal and display data.
See Figures 5 and 6.
Output When FCS is high, a chip enable signal is
transferred to the next IC from this pin.
Connect this pin to ( of the next IC.
When FCS is low, open this pin.
HD66206
V1
V3
V4
V1 and V2: Selection level
V3 and V4: Non-selection level
V2
Figure 3 Liquid Crystal Display Drive Level
Y73
Y74
Y75
Y76
Y77
Y78
Y79
Y80
Input data and latch address
D3
D2
D1R
D0L
D3
D2
D1R
D0L
Last
2nd
D3
D2
D1R
D0L
D3
D2
D1R
D0L
1st
1st
D0L
D1R
D2
D3
Y73
Y74
Y75
Y76
Y77
Y78
Y79
Y80
Low
Last
D0L
D1R
D2
D3
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
High
2nd
D0L
D1R
D2
D3
D0L
D1R
D2
D3
D0L
D1R
D2
D3
D0L
D1R
D2
D3
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
SHL
Figure 4 Column Driver Operating Mode
Table 2
Common Driver Operation
SHL
Shift Register Shift Direction
Common Signal Scan Direction
Low
D0L
SR
1
SR .......... SR D1R
2
80
Y1
Y80
High
D1R
SR
80
SR .......... SR
79
1
Y80
Y1
Table 3
D0L
Relationship between FCS, (, Data Latch Operation, and Driver Function
FCS
(
Data Latch Operation
Driver Function
High
Low
Enabled
Column driver
High
Disabled
High
—
Low
Common driver
153
HD66206
M
Output level to be selected
0
1
1
Data
Output level
0
1
0
V1 V3 V2 V4
Figure 5 Liquid Crystal Display Drive Output in Column Driver Operation
M
Output level to be selected
0
1
Data
Output level
1
0
1
0
V2 V3 V1 V4
Figure 6 Liquid Crystal Display Drive Output in Common Driver Operation
154
FLM
CL1
M
DISPOFF
D0L, D1R, D2, D3
CL2
Controller
–
+
–
+
–
+
R1
R2
R1
VCC
D3
D2
CL1
CAR
D0L
VCC
DISPOFF
V1
HD66206
V4
V3
(3)
V2
CL2
M
FCS
TEST
GND
VCC
VEE
E
D1R
SHL
VEE
GND
VCC
E
SHL
80
Open
Open
Open
D3
D2
CL1
CAR
D0L
80
HD66206
(1)
Y80, Y79, …, Y2, Y1
80
com239
com240
com1
com2
com3
CAR
VCC
VEE
GND
VCC
E
SHL
HD66206
(2)
Y80, Y79, …, Y2, Y1
80
CAR
LCD panel
640 × 240
1/240 duty
VCC
VEE
GND
VCC
E
SHL
80
HD66206
(8)
Y80, Y79, …, Y2, Y1
CAR
seg638
seg639
seg640
Open
3. In this example, the Y1 pin is located to the right as viewed from the front of the panel.
.
2. To stabilize
the power supply, place two 0.1-µF capacitors near each LCD driver: one between VCC and GND, and the other between VCC and VEE.
Notes: 1. The resisances of R1 and R2 depend on the type of LCD panel used. For example, for an LCD panel with a 1/15 bias, R1 and R2 must be 3 kΩ and 33 kΩ, respectively.
That is, R1/(4•R1 + R2) should be 1/15.
VEE(-25V)
R1
–
+
R1
VCC(+3V)
GND(0V)
GND
VCC
VEE
E
D1R
SHL
DISPOFF
V1
HD66206
V4
V3
(1)
V2
CL2
M
FCS
TEST
seg1
seg2
seg3
V1
V3
V4
V2
CL1
CL2
M
D0L, D1R, D2, D3
DISPOFF
FCS
TEST
Y80, Y79, …, Y2, Y1
V1
V3
V4
V2
CL1
CL2
M
D0L, D1R, D2, D3
DISPOFF
FCS
TEST
Y80, Y79, … Y2, Y1
V1
V3
V4
V2
CL1
CL2
M
D0L, D1R, D2, D3
DISPOFF
FCS
TEST
VCC
HD66206
Application Examples
Figure 7 shows an example when configuring the 640 × 240-dot LCD panel using the HD66206.
Figure 7 Application Example
155
HD66206
1
2
3
4
19
CL2
20
21
22
156
23
----------
157
158
159
160
-----------------------
D0L
seg.4
seg.8
seg.12 seg.16
----------
seg.76 seg.80 seg.84 seg.88 seg.92
-----------------------
seg.624 seg.628 seg.632 seg.636 seg.640
D1R
seg.3
seg.7
seg.11 seg.15
----------
seg.75 seg.79 seg.83 seg.87 seg.91
-----------------------
seg.623 seg.627 seg.631 seg.635 seg.639
D2
seg.2
seg.6
seg.10 seg.14
----------
seg.74 seg.78 seg.82 seg.86 seg.90
-----------------------
seg.622 seg.626 seg.630 seg.634 seg.638
D3
seg.1
seg.5
seg.9
----------
seg.73 seg.77 seg.81 seg.85 seg.89
-----------------------
seg.621 seg.625 seg.629 seg.633 seg.637
seg.13
The next IC is activated.
CAR
(the first IC)
CL1
Y1
(the first IC)
Y80
(the first IC)
SEG.80
SEG.1
Figure 8 Timing Charts for Application Example in Column Driver Operation
237
4
3
2
1
CL1
238
239
240
1
3
2
237
4
238
239
240
-------------------
-------------------
FLM
M
Y80
(the first IC)
Y79
(the first IC)
V1
V3
V4
V4
V2
V4
V1
V3
V3
V2
V4
V4
Figure 9 Timing Charts for Application Example in Common Driver Operation
156
HD66206
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Note
Power supply Logic circuit
VCC
voltage
Liquid crystal
VEE
display drive circuit
–0.3 to +7.0
V
1
VCC – 30.0 to VCC + 0.3
V
Input voltage (1)
VT1
–0.3 to VCC + 0.3
V
1 and 2
Input voltage (2)
VT2
VEE – 0.3 to VCC + 0.3
V
1 and 3
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. Measured relative to GND (0V).
2. Applies to CL1, CL2, M, SHL, (, D0L, D1R, D2, D3, FCS, TEST, and ',632)) pins.
3. Applies to V1 to V4 pins.
4. If the LSI is used beyond its absolute maximum rating, it may be permanently damaged. It
should always be used within the limits of its electrical characteristics in order to prevent
malfunction or unreliability.
157
HD66206
Electrical Characteristics
DC Characteristics 1 (VCC = 5V ± 10%, GND = 0V, VCC – VEE = 6 to 28V, and Ta = –20 to 75 °C,
unless otherwise stated)
Item
Symbol
Applicable Pin
Min.
Input high
level voltage
VIH
CL1, CL2, M,
SHL, (, D0L,
D1R, D2,
D3, FCS, TEST,
and ',632))
0.7 × VCC —
VCC
0
0.3 × VCC V
Input low level VIL
voltage
Typ. Max.
—
Unit Conditions
V
Output high
level voltage
VOH
&$5, D0L, D1R
VCC – 0.4 —
—
V
IOH = –0.4 mA
Output low
level voltage
VOL
&$5, D0L, D1R
—
—
0.4
V
IOL = 0.4 mA
Vi-Yj on
resistance
RON1
—
—
2.0
kΩ
ION = 100 µA
VCC – VEE = 28V
—
—
4.0
kΩ
Y1 to Y80,
V1 to V4
RON2
1 and 5
1 and 4
Input leakage
current (1)
IIL1
CL1, CL2, M,
SHL, (, D0L,
D1R, D2, D3,
FCS, TEST,
and ',632))
–5
—
5
µA
VIN = VCC to GND
Input leakage
current (2)
IIL2
V1 to V4
–25
—
25
µA
VIN = VCC to VEE
Consumption
current (1)
IGND1
—
—
—
3.0
mA
Consumption
current (2)
IST
—
—
—
200
µA
Consumption
current (3)
IEE1
—
—
—
500
µA
fCL2 = 8.0 MHz
fCL1 = 50 kHz
fM = 2.3 kHz
VCC = 5V
VCC – VEE = 28V
Checker data
FCS = high
Consumption
current (4)
IGND2
—
—
—
100
µA
Consumption
current (5)
IEE2
—
—
—
500
µA
158
Note
fCL1 = 50 kHz
fM = 2.3 kHz
VCC = 5V
VCC – VEE = 28V
FCS = low
2 and 4
2 to 4
2 and 4
2 and 5
2 and 5
HD66206
DC Characteristics 2 (VCC = 2.7 to 4.5V, GND = 0V, VCC – VEE = 6 to 28V, and Ta = –20 to 75 °C,
unless otherwise stated)
Item
Symbol
Applicable pin Min.
Input high
level voltage
VIH
0.8 × VCC —
CL1, CL2, M,
SHL, (, D0L,
D1R, D2,
D3, FCS, TEST, 0
—
and ',632))
Input low level VIL
voltage
Output high
level voltage
VOH
Output low
level voltage
VOL
Vi-Yj on
resistance
RON1
Typ.
Max.
Unit
VCC
V
Conditions
Note
0.2 × VCC V
&$5, D0L, and
VCC– 0.4
—
—
V
IOH = –0.4 mA
&$5, D0L, and
—
—
0.4
V
IOL = 0.4 mA
—
—
2.0
kΩ
ION = 100 µA
VCC – VEE = 2 8V
—
—
4.0
kΩ
D1R
D1R
Y1 to Y80, and
V1 to V4
RON2
1 and 5
1 and 4
Input leakage IIL1
current (1)
CL1, CL2, M,
SHL, (, D0L,
D1R, D2, D3,
FCS, TEST,
and ',632))
–5
—
5
µA
VIN = VCC to GND
Input leakage IIL2
current (2)
V1 to V4
–25
—
25
µA
VIN = VCC to VEE
Consumption IGND1
current (1)
—
—
—
1.5
mA
2 and 4
Consumption IST
current (2)
—
—
—
100
µA
Consumption IEE1
current (3)
—
—
—
500
µA
fCL2 = 6.5 MHz
fCL1 = 40.6 kHz
fM = 1.8 kHz
VCC = 3.0V
VCC – VEE = 28V
Checker data
FCS = high
Consumption IGND2
current (4)
—
—
—
50
µA
2 and 5
Consumption IEE2
current (5)
—
—
—
500
µA
fCL1 = 40.6 kHz
fM = 1.8 kHz
VCC = 3.0V
VCC – VEE = 28V
FCS = low
2 to 4
2 and 4
2 and 5
Notes: 1. Indicates the resistance between one pin from Y1 to Y80 and another pin from the V pins V1 to
V4, when a load current is applied to the Y pin; defined under the following conditions:
In column driver operation
V1 and V3 = VCC – 2/10 (VCC – VEE)
V4 and V2 = VEE + 2/10 (VCC – VEE)
In common driver operation
V1 and V3 = VCC – 2/10 (VCC – VEE)
V4 and V2 = VEE + 2/10 (VCC – VEE)
V1 and V3 should be near the VCC level, and V4 and V2 should be near the VEE level. All these
voltage pairs should be separated by less than ∆ V, which is the range within which RON, the
LCD drive circuits’ output impedance, is stable. Note that ∆ V depends on power supply voltage
VCC – VEE. See Figure 10.
159
HD66206
2. Input and output currents are excluded. When a CMOS input is floating, excess current flows
from the power supply through to the input circuit. To avoid this, VIH and VIL must be held to
VCC and GND, respectively.
3. VCC – GND current at standby (( input = high)
4. Applies to column driver operation.
5. Applies to common driver operation.
V3
∆V (V)
∆V
V CC
V1
5.6
2.4
∆V
V4
V2
V EE
6
28
VCC–VEE (V)
Figure 10 Relationship between Driver Output Waveform and Level Voltages
160
HD66206
Pin Configuration
Each pin configuration is shown below.
VCC
Applicable pin:
CL1, CL2, SHL
M, E, FCS, and
TEST
Applicable pin:
D2 and D3
PMOS
D3
D2
NMOS
Input enable
GND
Figure 11 Input Pin Configuration
VCC
PMOS
Applicable pin:
D0L and D1R
Output data
PMOS
Output enable
NMOS
D0L
VCC
NMOS
Output data
PMOS
GND
PMOS
D1R
Output enable
NMOS
NMOS
Input enable
GND
Figure 12 Input/Output Pin Configuration
VCC
Applicable pin:
CAR
Applicable pin:
Y1–Y80
PMOS
PMOS
VCC
PMOS
Yn
NMOS
VCC
NMOS
VEE
NMOS
VEE
V1
V3
V4
V2
GND
Figure 13 Output Pin Configuration
161
HD66206
AC Characteristics 1 (In Column Driver Operation) (VCC = 5V ± 10%, GND = 0V, VCC – VEE = 6 to
28V, and Ta = –20 to +75 ° C, unless otherwise stated)
Item
Symbol
Applicable Pins
Min.
Max.
Unit
Clock cycle time
tCYC
CL2
125
—
ns
Clock high level width
tCWH
CL2 and CL1
40
—
ns
Clock low level width
tCWL
CL2
40
—
ns
Clock setup time
tSCL
CL1 and CL2
80
—
ns
Clock hold time
tHCL
CL1 and CL2
80
—
ns
Clock rise time
tr
CL1 and CL2
—
1
ns
1
Clock fall time
tf
CL1 and CL2
—
1
ns
1
Data setup time
tDS
D0L, D1R, D2, D3, and CL2
20
—
ns
Data hold time
tDH
D0L, D1R, D2, D3, and CL2
20
—
ns
Enable setup time
tESU
Carry output delay time
20
—
ns
tCAR
( and CL2
&$5 and CL2
—
70
ns
M phase difference
tCM
M and CL1
—
300
ns
CL1 cycle time
tCL1
CL1
tCYC × 50
—
ns
162
Note
2
HD66206
AC Characteristics 2 (In Column Driver Operation) (VCC = 2.7 to 4.5V, GND = 0V, VCC – VEE = 6 to
28V, and Ta = –20 to +75 ° C, unless otherwise stated)
Item
Symbol
Applicable pins
Min.
Max.
Unit
Clock cycle time
tCYC
CL2
152
—
ns
Clock high level width
tCWH
CL2 and CL1
65
—
ns
Clock low level width
tCWL
CL2
65
—
ns
Clock setup time
tSCL
CL1 and CL2
80
—
ns
Clock hold time
tHCL
CL1 and CL2
120
—
ns
Clock rise time
tr
CL1 and CL2
—
1
ns
1
Clock fall time
tf
CL1 and CL2
—
1
ns
1
Data setup time
tDS
D0L, D1R, D2, D3, and CL2
50
—
ns
Data hold time
tDH
D0L, D1R, D2, D3, and CL2
50
—
ns
Enable setup time
tESU
Carry output delay time
30
—
ns
tCAR
( and CL2
&$5 and CL2
—
100
ns
M phase difference
tCM
M and CL1
—
300
ns
CL1 cycle time
tCL1
CL1
tCYC × 50
—
ns
Note
2
Notes: 1. Clock rise time (tr) and clock fall time (tf) must satisfy the following conditions:
tr and tf < (tCYC – tCWH – tCWL)/2
tr and tf ≤ 50
2. Defined by connecting the load circuit shown in Figure 14.
Test point
30 pF
Figure 14 Load Circuit
163
HD66206
AC Characteristics 3 (In Common Driver Operation) (VCC = 2.7 to 5.5V, GND = 0V, VCC – VEE = 6 to
28V, and Ta = –20 to +75 ° C, unless otherwise stated)
Item
Symbol
Applicable Pins
Min.
Clock cycle time
tCYC
CL2
10
—
µs
Clock high level width
tCWH
CL2
80
—
ns
Clock low level width
tCWL
CL2
1.0
—
µs
Clock rise time
tr
CL2
—
30
ns
Clock fall time
tf
CL2
—
30
ns
Data setup time
tDS
D0L, D1R, and CL2
100
—
ns
Data hold time
tDH
D0L, D1R, and CL2
100
—
ns
Data output delay time
tDD
D0L, D1R, and CL2
—
7.0
µs
Note: Defined by connecting the load circuit shown in Figure 15.
Test point
30 pF
Figure 15 Load Circuit
164
Max.
Unit
Note
1
HD66206
tr
tCWH
tf
tCYC
tCWL
VIH
CL2
VIL
tDS
tDH
VIH
D0L, D1R, D2, and D3
VIL
tCWH
tCL1
VIH
VIL
CL1
tSCL
tHCL
VIH
CL2
Last
data
tCAR
VIL
tCAR
VOH
CAR
VOL
E
VIL
tESU
tCM
M
VIH
VIL
Figure 16 Common Driver Operation Timing
165
HD66206
tf
tCWL
tr
tCWH
tCYC
VIH
CL2
VIL
tDS
tDH
VIH
Data in
VIL
(D0L, D1R)
tDD
Data out
(D0L, D1R)
VOH
VOL
Figure 17 Common Driver Operation Timing
166