HD61203U (Dot Matrix Liquid Crystal Graphic Display 64-Channel Common Driver) Preliminary Description The HD61203U is a common signal driver for dot matrix liquid crystal graphic display systems. It generates the timing signals (switch signal to convert LCD waveform to AC, frame synchronous signal) and supplies them to the column driver to control display. It provides 64 driver output lines and the impedance is low enough to drive a large screen. As the HD61203U is produced by a CMOS process, it is fit for use in portable battery-driven equipment utilizing the liquid crystal display’s low power consumption. The user can easily construct a dot matrix liquid crystal graphic display system by combining the HD61203U and the column (segment) driver HD61202U. Features • • • • • • • • • • Dot matrix liquid crystal graphic display common driver with low impedance Low impedance: 1.5 kΩ max Internal liquid crystal display driver circuit: 64 circuits Internal dynamic display timing generator circuit Display duty cycle When used with the column driver HD61202U: 1/48, 1/64, 1/96, 1/128 When used with the controller HD61830: Selectable out of 1/32 to 1/128 Low power dissipation: During displays: 5 mW Power supplies: VCC: 2.7~5.5V Power supply voltage for liquid crystal display drive: 8V to 16V CMOS process 100-pin plastic QFP, 100-pin plastic TQFP, chip 849 HD61203U Ordering Information Type No. Package HD61203UFS 100-pin plastic QFP (FP-100A) HD61203UTE 100-pin thin plastic QFP (TFP-100B) HCD61203U Chip 850 HD61203U HD61203UFS (FP-100A) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 X43 X44 X45 X46 X47 X48 X49 X50 X51 X52 X53 X54 X55 X56 X57 X58 X59 X60 X61 X62 X63 X64 VEE V6R V5R V2R V1R TH CL2 CL1 DS1 DS2 C NC R NC CR STB SHL GND NC M/S ø2 ø1 NC FRM M NC FCS DR X22 X21 X20 X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 VEE V6L V5L V2L V1L VCC DL FS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 X38 X39 X40 X41 X42 Pin Arrangement (Top view) 851 HD61203UTFIA (TFP-100B) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 DL FS DS1 DS2 C NC R NC CR STB SHL GND NC M/S ø2 ø1 NC FRM M NC FCS DR CL1 CL2 TH X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 VEE V6L V5L V2L V1L VCC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 X38 X39 X40 X41 X42 X43 X44 HD61203U (Top view) 852 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 X45 X46 X47 X48 X49 X50 X51 X52 X53 X54 X55 X56 X57 X58 X59 X60 X61 X62 X63 X64 VEE V6R V5R V2R V1R HD61203U Pad Arrangement NO.79 No.1 NO.2 NO.78 TYPE CODE HD61203U NO.28 No.29 NO.54 Chip Size : 3.40 × 4.08 µm2 Coordinate : Pad Center Origin : Chip center Pad Size : 90 × 90 µm2 No.52 Pad Location Coordinates Coordinate Y PAD Name Coordinate X Y R –586 PAD PAD No. Name 1 X22 X –1479 1853 34 2 X21 –1513 1712 35 3 X20 –1513 1544 36 4 X19 –1513 1385 37 5 X18 –1513 1238 38 6 X17 –1513 1091 39 SHL –196 7 X16 –1513 952 40 GND –65 8 X15 –1513 822 41 PAD No. CR –456 Coordinate Y PAD No. PAD Name 67 X56 1513 203 68 X55 1513 333 69 X54 1513 463 70 X53 1513 593 71 X52 1513 723 –1828 72 1513 853 –1828 73 X51 X50 1513 X49 1513 983 1122 –1828 –1828 X 9 X14 –1513 692 42 M/S 65 –1828 74 75 X48 1513 1261 10 X13 –1513 562 43 PHI2 195 –1828 76 X47 1513 1399 11 X12 X11 –1513 432 325 –1828 77 X46 1513 –1513 302 44 45 PHI1 12 78 X45 1513 13 X10 –1513 172 46 FRM 455 –1828 79 X44 1470 1546 1693 1853 14 X9 –1513 42 47 M 585 –1828 80 X43 1304 1853 15 X8 –1513 –88 48 81 X42 1170 1853 16 X7 –218 –349 49 50 X41 1040 1853 X6 –1513 –1513 82 17 83 X40 910 1853 18 X5 –1513 –479 51 84 X39 779 1853 19 X4 –1513 –609 52 85 X38 649 1853 20 X3 –1513 –739 53 86 X37 21 X2 –869 1513 –1522 87 X36 X1 VEE1 –999 54 55 V1R 22 –1513 –1513 519 389 V2R 88 X35 259 –1129 56 V5R –1236 89 X34 129 1853 V6L –1513 –1259 57 1513 1513 1513 –1374 –1513 –1097 90 X33 –1 23 24 FCS DR CL2 715 853 1407 –1828 –1828 –1828 1853 1853 1853 25 V5L –1513 –1389 58 V6R VEE2 1513 –967 91 X32 –131 1853 1853 26 V2L –1513 –1527 59 X64 1513 –837 92 X31 –261 1853 27 –1513 –1665 60 –707 93 X30 –391 1853 –1513 –1821 61 X63 X62 1513 28 V1L VCC 1513 –577 94 X29 –521 1853 29 DL –1375 –1853 62 X61 1513 –447 X28 –651 1853 30 FS –1213 –1853 63 X60 1513 X27 –781 1853 31 DS1 –976 –1828 64 X59 1513 –317 –187 95 96 97 X26 1853 32 DS2 –846 –1828 65 X58 1513 –57 98 X25 –911 –1041 33 C –716 –1828 66 X57 1513 73 99 100 X24 –1171 1853 X23 –1301 1853 1853 853 854 STB SHL DL TH CL1 VCC GND VEE V2L V6L Logic R f Cf R CR 1 X1 C Oscillator V1L V5L M/S 2 X2 FS DS1 DS2 ø1 Timing generation circuit Bidirectional shift register Liquid crystal display driver circuits 64 output terminals V2R V6R ø2 62 63 Logic 64 Logic Logic X62 X63 X64 V1R V5R M CL2 FRM FCS DR HD61203U Block Diagram HD61203U Block Functions Oscillator The CR oscillator generates display timing signals and operating clocks for the HD61202U. It is required when the HD61203U is used with the HD61202U. An oscillation resister Rf and an oscillation capacitor Cf are attached as shown in Figure 1. When using an external clock, input the clock into terminal CR and don’t connect any lines to terminals R and C. The oscillator is not required when the HD61203U is used with the HD61830. Then, connect terminal CR to the high level and don’t connect any lines to terminals R and C (Figure 2). R CR C R Open Rf Cf CR C External Open clock Figure 1 Oscillator Connection with HD61202U R Open CR VCC C Open Figure 2 Oscillator Connection with HD61830 855 HD61203U Timing Generator Circuit The timing generator circuit generates display timing and operating clock for the HD61202U. This circuit is required when the HD61203U is used with the HD61202U. Connect terminal M/S to high level (master mode). It is not necessary when the display timing signal is supplied from other circuits, for example, from HD61830. In this case connect the terminals FS, DS1, and DS2 to high level and M/S to low level (slave mode). Bidirectional Shift Register A 64-bit bidirectional shift register. The data is shifted from DL to DR when SHL is at high level and from DR to DL when SHL is at low level. In this case, CL2 is used as shift clock. The lowest order bit of the bidirectional shift register, which is on the DL side, corresponds to X1 and the highest order bit on the DR side corresponds to X64. Liquid Crystal Display Driver Circuit The combination of the data from the shift register with the M signal allows one of the four liquid crystal display driver levels V1, V2, V5 and V6 to be transferred to the output terminals (Table 1). Table 1 Output Levels Data from the Shift Register M Output Level 1 1 V2 0 1 V6 1 0 V1 0 0 V5 856 HD61203U HD61203U Terminal Functions Terminal Name Number of Terminals VCC GND VEE I/O Connected to Functions 1 1 2 Power supply VCC–GND: Power supply for internal logic. V1L, V2L V5L, V6L V1R, V2R V5R, V6R 8 Power supply M/S 1 VCC–VEE: Power supply for driver circuit logic. Liquid crystal display driver level power supply. V1L (V1R), V2L (V2R): Selected level V5L (V5R), V6L (V6R): Non-selected level Voltages of the level power supplies connected to V1L and V1R should be the same. (This applies to the combination of V2L & V2R, V5L & V5R and V6L & V6R respectively.) I VCC or GND Selects master/slave. • M/S = VCC: Master mode When the HD61203U is used with the HD61202U, timing generation circuit operates to supply display timing signals and operation clock to the HD61202U. Each of I/O common terminals DL, DR, CL2, and M is in the output state. • M/S = GND: Slave mode The timing operation circuit stops operating. The HD61203U is used in this mode when combined with the HD61830. Even if combined with the HD61202U, this mode is used when display timing signals (M, data, CL2, etc.) are supplied by another HD61203U in the master mode. Terminals M and CL2 are in the input state. When SHL is VCC, DL is in the input state and DR is in the output state. When SHL is GND, DL is in the output state and DR is in the input state. FCS 1 I VCC or GND Selects shift clock phase. • FCS = VCC Shift register operates at the rising edge of CL2. Select this condition when HD61203U is used with HD61202U or when MA of the HD61830 connects to CL2 in combination with the HD61830. • FCS = GND Shift register operates at the fall of CL2. Select this condition when CL1 of HD61830 connects to CL2 in combination with the HD61830. 857 HD61203U Terminal Name Number of Terminals I/O Connected to Functions FS 1 I VCC or GND Selects frequency. When the frame frequency is 70 Hz, the oscillation frequency should be: fOSC = 430 kHz at FCS = VCC fOSC = 215 kHz at FCS = GND This terminal is active only in the master mode. Connect it to VCC in the slave mode. DS1, DS2 2 I VCC or GND Selects display duty factor. Display Duty Factor 1/48 1/64 1/96 1/128 DS1 GND GND VCC VCC DS2 GND VCC GND VCC These terminals are valid only in the master mode. Connect them to VCC in the slave mode. 67% TH CL1 1 1 1 CR, R, C 3 I VCC or GND Input terminal for testing Connect to 67% VCC. Connect TH and CL1 to GND. Oscillator In the master mode, use these terminals as shown below: Internal oscillation Rf R Cf CR External clock Open External clock Open R CR C C In the slave mode, stop the oscillator as shown below: ø1, ø2 858 2 O HD61202U Open VCC Open R CR C Operating clock output terminals for the HD61202U • Master mode Connect these terminals to terminals ø1 and ø2 of the HD61202U respectively. • Slave mode Don’t connect any lines to these terminals. HD61203U Terminal Name Number of Terminals I/O Connected to Functions FRM 1 O HD61202U M 1 I/O Frame signal • Master mode Connect this terminal to terminal FRM of the HD61202U. • Slave mode Don’t connect any lines to this terminal. MB of Signal to convert LCD driver signal into AC HD61830 or M • Master mode: Output terminal of HD61202U Connect this terminal to terminal M of the HD61202U. • CL2 DL, DR 1 2 I/O I/O CL1 or MA of HD61830 or CL of HD61202U Open or FLM of HD61830 Slave mode: Input terminal Connect this terminal to terminal MB of the HD61830. Shift clock • Master mode: Output terminal Connect this terminal to terminal CL of the HD61202U. • Slave mode: Input terminal Connect this terminal to terminal CL1 or MA of the HD61830. Data I/O terminals of bidirectional shift register DL corresponds to X1’s side and DR to X64’s side. • Master mode Output common scanning signal. Don’t connect any lines to these terminals normally. • Slave mode Connect terminal FLM of the HD61830 to DL (when SHL = VCC) or DR (when SHL = GND). M/S NC 5 SHL 1 VCC GND SHL VCC GND VCC GND DL Output Output Input Output DR Output Output Output Input Open Not used. VCC or GND Selects shift direction of bidirectional shift register. Don’t connect any lines to this terminal. I SHL Shift Direction Common Scanning Direction VCC DL → DR X1 → X64 GND DL ← DR X1 ← X64 859 HD61203U Terminal Name Number of Terminals I/O Connected to Functions X1–X64 64 O Liquid crystal display Liquid crystal display driver output Output one of the four liquid crystal display driver 1 M Data Output level 1 0 0 1 0 V2 V6 V1 V5 When SHL is VCC, X1 corresponds to COM1 and X64 corresponds to COM64. When SHL is GND, X64 corresponds to COM1 and X1 corresponds to COM64. 860 L L H H L B C D E F L L L L L L H H H H H L } Fixed L L L L L L Rf: Oscillation resister Cf: Oscillation capacitor H H H H H H CL1 FCS FS “—” means “open”. Notes: H: VCC L: GND L M/S TH A H L L L L H H H or or H H L H L H H H H H H H H H H Cf Rf Cf Rf H H H DS1 DS2 STB CR — Rf Rf — — — R — Cf Cf — — — C — — — ø2 — — — FRM From MB of HD61830 From MB of HD61830 From MB of HD61830 M — — — From M of HD61203U No. 1 To ø1 of To ø2 of To FRM of To M of HD61202U HD61202U HD61202U HD61202U HD61203U To ø1 of To ø2 of To FRM of To M of HD61202U HD61202U HD61202U HD61202U — — — ø1 From CL2 of HD61203U No. 1 To CL of HD61202U To CL2 of HD61203U To CL of HD61202U From MA of HD61830 From MA of HD61830 From CL1 of HD61830 CL2 L — From DL/DR of HD61203U No. 1 — L To DL/DR of HD61203U No. 2 — H L H — — L H From DL/DR of HD61203U No. 1 To DL/DR of HD61203U No. 2 L H From FLM of HD61830 — L H From FLM of HD61830 DL H SHL COM65–COM128 COM64–COM1 COM1–COM64 COM64–COM1 COM1–COM64 X1–X64 COM64–COM1 COM1–COM64 COM1–COM64 COM64–COM1 From DL/DR COM64–COM1 of HD61203U No. 1 — — To DL/DR COM1–COM64 of HD61203U No. 2 — — From DL/DR COM128–COM65 of HD61203U No. 1 — From FLM of HD61830 To DL/DR of HD61203U No. 2 From FLM of HD61830 — DR HD61203U Example of Application HD61203U Connection List 861 HD61203U Outline of HD61203U System Configuration Use with HD61830 1. When display duty ratio of LCD is 1/64 HD61830 No. 1 COM1 COM64 No. 1 COM1 COM64 COM1 COM64 LCD One HD61203U drives common signals. Refer to Connection List A. One HD61203U drives common signals for upper and lower panels. Refer to Connection List A. Two HD61203Us drive upper and lower panels separately to ensure the quality of display. No. 1 and No. 2 operate in parallel. For both of No. 1 and No. 2, refer to Connection List A. LCD HD61830 Upper Lower HD61830 No. 1 No. 2 LCD COM1 COM64 COM1 COM64 Upper Lower 2. When display duty ratio of LCD is from 1/65 to 1/128 HD61830 No. 1 COM1 COM128 LCD Two HD61203Us connected serially drive common signals. Refer to Connection List B for No. 1. Refer to Connection List C for No. 2. Two HD61203Us connected serially drive upper and lower panels in parallel. Refer to Connection List B for No. 1. Refer to Connection List C for No. 2. Two sets of HD61203Us connected serially drive upper and lower panels in parallel to ensure the quality of display. Refer to Connection List B for No. 1 and 3. Refer to Connection List C for No. 2 and 4. No. 2 HD61830 No. 1 No. 2 LCD COM1 Upper COM128 COM1 Lower COM128 HD61830 No. 1 LCD No. 2 No. 3 No. 4 862 COM1 Upper COM128 COM1 Lower COM128 HD61203U Use with HD61202 (1/64 Duty Ratio) No. 1 COM1 COM64 LCD HD61202U HD61202U One HD61203U drives common signals and supplies timing signals to the HD61202Us. Refer to Connection List D. LCD COM1 COM64 No. 1 COM1 COM64 HD61202U Upper Lower Refer to Connection One HD61203U drives List D. upper and lower panels and supplies timing signals to the HD61202Us. HD61202U No. 1 No. 2 LCD COM1 COM64 COM1 COM64 HD61202U Upper Lower Two HD61203Us drive upper and lower panels in parallel to ensure the quality of display. No. 1 supplies timing signals to No. 2 and the HD61202Us. Refer to Connection List E for No. 1. Refer to Connection List F for No. 2. 863 HD61203U Connection Example 1 Use with HD61202U (RAM Type Segment Driver) 1. 1/64 duty ratio (see Connection List D) X1 (X64) C Cf COM1 CR LCD panel Rf R1 R2 R1 R1 R3 V6 – + R3 – + V3 R3 – + – + V4 R3 V5 R3 V2 VEE –10V 0V V5L, V5R V2L, V2R VEE Contrast GND Open Open COM64 V6L, V6R DL DR HD61203U R1 X64 (X1) V1L, V1R M CL2 FRM ø1 ø2 VCC SHL DS1 DS2 TH CL1 FS M/S FCS STB M CL FRM ø1 ø2 HD61202U V1L, V1R V3L, V3R V4L, V4R V2L, V2R VCC GND VEE R3 V1 R VCC V1 V3 V4 V2 VCC GND VEE +5V (VCC) R3 = 15 Ω ( ) is at SHL = Low Note: The values of R1 and R2 vary with the LCD panel used. When bias factor is 1/9, the values of R1 and R2 should satisfy R1 1 = 4R1 + R2 9 For example, R1 = 3 kΩ, R2 = 15 kΩ Figure 3 Example 1 864 1 V6 V6 * V5 V1 V1 2 1 * 3 2 V5 V5 3 47 48 1 frame 49 63 ( ): at SHL = Low Note: * Phase difference between DL (DR) and CL2 X2 (X63) X1 (X64) M DR (DL) DL (DR) FRM CL2 ø2 ø1 C 64 * * V6 V2 1 DL (DR) CL2 ø2 V2 V6 2 V6 3 1 frame 63 64 * * V5 V1 1 HD61203U Figure 4 Example 1 Waveform (RAM Type, 1/64 Duty Cycle) 865 HD61203U Connection Example 2 Use with HD61830 (Display Controller) Open VCC Open C CR R X1 (X64) VCC VCC X64 (X1) V1 V1L, V1R V6 V6L, V6R V5 V5L, V5R V2 V2L, V2R COM1 LCD panel HD61203U See connection example 1. 1/64 duty ratio (see Connection List A) COM64 M CL2 DL (DR) DR (DL) M CL1 FLM Open HD61830 (Display controller) VCC VEE VEE GND GND Open Open Open FRM ø1 ø2 SHL DS1 DS2 TH CL1 FS M/S FCS STB ( ) is at SHL = Low Figure 5 Example 2 (1/64 Duty Ratio) 866 From HD61830 V2 V6 X2 (X63) X64 V6 (X1) V6 X1 (X64) CL1 FLM MB V5 V5 V1 2 V1 3 V5 V5 ( ): at SHL = Low 1 4 1 frame 64 V1 1 V6 V6 V2 2 V2 V6 3 V6 1 frame 64 V2 1 V5 V5 V1 HD61203U Figure 6 Example 2 Waveform (1/64 Duty Ratio) 867 HD61203U 2. 1/100 duty ratio (see Connection List B, C) R CR C VCC Open Open VCC V1L, V1R V6L, V6R V5L, V5R V2L, V2R VEE GND V1 V6 M CL2 DL (DR) HD61203U (master) No. 1 DR (DL) See Connection Example 1 VCC V5 V2 VEE GND VCC SHL DS1 DS2 TH CL1 FS M/S FCS STB X1 (X64) COM1 X64 (X1) LCD panel M CL2 DL (DR) DR (DL) FLM MA MB VCC V1L, V1R V6L, V6R V5L, V5R V2L, V2R VEE GND Open VCC Open C CR R HD61203U (slave) No. 2 HD61830 Display controller Open COM64 COM65 X1 (X64) COM100 X36 (X29) SHL DS1 DS2 TH CL1 FS M/S FCS STB VCC Note: ( ) is at SHL = Low Figure 7 Example 2 (1/100 Duty Ratio) 868 HD61830 HD61203U No. 1 HD61203U No. 2 X36 (X29) X1 (X64) X64 (X1) X1 (X64) V6 DR(DL) HD61203U No. 1 MA FLM MB V2 V6 V6 V6 100 V5 V5 V5 V1 1 V5 2 3 V1 64 V1 V5 65 1 frame V5 66 V1 100 V6 V6 V6 V2 1 V6 2 3 V2 64 V2 65 1 frame 66 V2 100 V5 V5 V5 V1 1 2 HD61203U Figure 8 Example 2 Waveform (1/100 Duty Ratio) 869 HD61203U Absolute Maximum Ratings Item Symbol Limit Unit Notes Power supply voltage (1) VCC –0.3 to +7.0 V 2 Power supply voltage (2) VEE VCC – 17.0 to VCC + 0.3 V 5 Terminal voltage (1) VT1 –0.3 to VCC + 0.3 V 2, 3 Terminal voltage (2) VT2 VEE – 0.3 to VCC + 0.3 V 4, 5 Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Notes: 1. If LSIs are used beyond absolute maximum ratings, they may be permanently destroyed. We strongly recommend you to use the LSI within electrical characteristic limits for normal operation, because use beyond these conditions will cause malfunction and poor reliability. 2. Based on GND = 0V. 3. Applies to input terminals (except V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R) and I/O terminals at high impedance. 4. Applies to V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R. 5. Apply the same value of voltages to V1L and V1R, V2L and V2R, V5L and V5R, V6L and V6R, VEE (23 pin) and VEE (58 pin) respectively. Maintain VCC ≥ V1L = V1R ≥ V6L = V6R ≥ V5L = V5R ≥ V2L = V2R ≥ VEE 870 HD61203U Electrical Characteristics DC Characteristics (VCC = 2.7V to 5.5V, GND = 0V, VCC–VEE = 8.0 to 16.0V, Ta = –20 to +75°C) Specifications Test Item Symbol Min Typ Max Unit Input high voltage VIH 0.7 × VCC — VCC V 1 Input low voltage VIL GND — 0.3 × VCC V 1 Output high voltage VOH VCC – 0.4 — — V IOH = –0.4 mA 2 Output low voltage VOL — — 0.4 V IOL = 0.4 mA 2 Vi–Xj on resistance RON — — 1.5 kΩ VCC–VEE = 10V Load current ±150 µA 13 Input leakage current IIL1 –1.0 — 1.0 µA Vin = 0 to VCC 3 Input leakage current IIL2 –2.0 — 2.0 µA Vin = VEE to VCC 4 Operating frequency fopr1 50 — 600 kHz In master mode external clock operation 5 Operating frequency fopr2 0.5 — 1500 kHz In slave mode shift register 6 Oscillation frequency fosc 315 450 585 kHz Cf = 20 pF ± 5% Rf = 47 kΩ ± 2% 7, 12 Dissipation current (1) IGG1 — — 1.0 mA In master mode 1/128 duty cycle Cf = 20 pF Rf = 47 kΩ 8, 9 Dissipation current (2) IGG2 — — 200 µA In slave mode 1/128 duty cycle 8, 10 Dissipation current — — 100 µA In master mode 1/128 duty cycle 8, 11 IEE Test Conditions Notes Notes: 1. Applies to input terminals FS, DS1, DS2, CR, SHL, M/S, and FCS and I/O terminals DL, M, DR and CL2 in the input state. 2. Applies to output terminals, ø1, ø2, and FRM and I/O common terminals DL, M, DR, and CL2 in the output status. 3. Applies to input terminals FS, DS1, DS2, CR, 67%, SHL, M/S, FCS, CL1, and TH, I/O terminals DL, M, DR, and CL2 in the input state and NC terminals. 4. Applies to V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R. Don’t connect any lines to X1 to X64. 871 HD61203U 5. External clock is as follows. TH External clock waveform TL Duty cycle = 0.7 VCC 0.5 VCC 0.3 VCC tfcp trcp External clock Open Open CR R C TH × 100% TH + TL Min Typ Max Unit Duty cycle 45 50 55 % trcp — — 50 ns tfcp — — 50 ns 6. Applies to the shift register in the slave mode. For details, refer to AC characteristics. 7. Connect oscillation resistor (Rf) and oscillation capacitance (Cf) as shown in this figure. Oscillation frequency (fOSC) is twice as much as the frequency (fø) at ø1 or ø2. Cf Rf CR R C ø1, ø2 Cf = 20 pF Rf = 47 kΩ fOSC = 2 × fø 8. No lines are connected to output terminals and current flowing through the input circuit is excluded. This value is specified at VIH = VCC and VIL = GND. 9. This value is specified for current flowing through GND in the following conditions: Internal oscillation circuit is used. Each terminal of DS1, DS2, FS, SHL, M/S, 67%, and FCS is connected to VCC and each of CL1 and TH to GND. Oscillator is set as/ described in note 7. 10. This value is specified for current flowing through GND under the following conditions: Each terminals of DS1, DS2, FS, SHL, 67%, FCS and CR is connected to VCC, CL1, TH, and M/S to GND and the terminals CL2, M, and DL are respectively connected to terminals CL2, M, and DL of the HD61203U under the condition described in note 9. 11. This value is specified for current flowing through VEE under the condition described in note 9. Don’t connect any lines to terminal V. 12. This figure shows a typical relation among oscillation frequency, Rf and Cf. Oscillation frequency may vary with the mounting conditions. fOSC (kHz) 600 Cf = 20 pF 400 200 0 50 Rf (kΩ) 872 100 HD61203U 13. Resistance between terminal X and terminal V (one of V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R) when load current flows through one of the terminals X1 to X64. This value is specified under the following conditions: VCC–VEE = 10V V1L = V1R, V6L = V6R = VCC – 1/7 (VCC–VEE) V2L = V2R, V5L = V5R = VEE + 1/7 (VCC–VEE) RON V1L, V1R V6L, V6R Terminal X (X1 to X64) V5L, V5R V2L, V2R Connect one of the lines The following is a description of the range of power supply voltage for liquid crystal display drive. Apply positive voltage to V1L = V1R and V6L = V6R and negative voltage to V2L = V2R and V5L = V5R within the ÆV range. This range allows stable impedance on driver output (RON). Notice that ÆV depends on power supply voltage VCC–VEE. VCC V1 (V1L = V1R) Range of power supply voltage for liquid crystal display drive V6 (V6L = V6R) ∆V (V) ∆V 3.5 2 ∆V V5 (V5L = V5R) V2 (V2L = V2R) VEE 8 16 VCC–VEE (V) Correlation between driver output waveform and power supply voltage for liquid crystal display drive Correlation between power supply voltage VCC–VEE and ∆V 873 HD61203U Terminal Configuration Input Terminal Applicable terminals: CR, M/S, SHL, FCS, DS1, DS2, FS VCC PMOS NMOS I/O Terminal Applicable terminals: DL, DR, CL2, M VCC (Input circuit) PMOS VCC Enable NMOS PMOS Data NMOS Output circuit (tristate) Output Terminal VCC Applicable terminals: ø1, ø2, FRM PMOS NMOS Applicable terminals: X1 to X64 Output Terminal PMOS V1L, V1R VCC PMOS V6L, V6R VCC NMOS V5L, V5R VEE NMOS VEE 874 V2L, V2R HD61203U AC Characteristics (VCC = 2.7V to 5.5V, GND = 0V, Ta = –20 to +75°C) In the Slave Mode (M/S = GND) CL2 (FCS = GND) (Shift clock) 0.7 VCC CL2 (FCS = VCC) (Shift clock) 0.7 VCC tWLCL2L 0.3 VCC tf tr tr tf tWLCL2H tDS tWHCL2H tWHCL2L 0.3 VCC tDH tDD DL (SHL = VCC) DR (SHL = GND) Input data 0.7 VCC 0.3 VCC tDHW DR (SHL = VCC) DL (SHL = GND) Output data 0.7 VCC 0.3 VCC Item Symbol Min Typ Max Unit CL2 low level width (FCS = GND) tWLCL2L 450 — — ns CL2 high level width (FCS = GND) tWLCL2H 150 — — ns CL2 low level width (FCS = VCC) tWHCL2L 150 — — ns CL2 high level width (FCS = VCC) tWHCL2H 450 — — ns Data setup time tDS 100 — — ns Data hold time tDH 100 — — ns Data delay time tDD — — 200 ns Data hold time tDHW 10 — — ns CL2 rise time tr — — 30 ns CL2 fall time tf — — 30 ns Note 1 Notes: 1. The following load circuit is connected for specification. Output terminal 30 pF (includes jig capacitance) 875 HD61203U 2. In the master mode (M/S = VCC, FCS = VCC, Cf = 20 pF, Rf = 47 kΩ) CL2 0.7 VCC tWCL2L tWCL2H 0.3 VCC tDH tDS tDH tDS 0.7 VCC DL (SHL = VCC) DR (SHL = GND) 0.3 VCC tDD tDD 0.7 VCC DR (SHL = VCC) DL (SHL = GND) 0.3 VCC tDFRM tDFRM 0.7 VCC FRM 0.3 VCC tDM 0.7 VCC M 0.3 VCC tf tr tWø1H 0.7 VCC ø1 0.3 VCC tWø1L tD12 tD21 0.7 VCC ø2 tWø2H tf tWø2L tr 876 0.3 VCC HD61203U Item Symbol Min Typ Max Unit Data setup time tDS 20 — — µs Data hold time tDH 40 — — µs Data delay time tDD 5 — — µs FRM delay time tDFRM –2 — +2 µs M delay time tDM –2 — +2 µs CL2 low level width tWCL2L 35 — — µs CL2 high level width tWCL2H 35 — — µs ø1 low level width tWø1L 700 — — ns ø2 low level width tWø2L 700 — — ns ø1 high level width tWø1H 2100 — — ns ø2 high level width tWø2H 2100 — — ns ø1–ø2 phase difference tD12 700 — — ns ø2–ø1 phase difference tD21 700 — — ns ø1, ø2 rise time tr — — 150 ns ø1, ø2 fall time tf — — 150 ns 877