TI TPS65835RKPR

TPS65835
Advanced PMU With Integrated MSP430 For Active
Shutter 3D Glasses
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLVSAF6
June 2011
TPS65835
SLVSAF6 – JUNE 2011
www.ti.com
Contents
1
2
3
2
.................................................................................................................. 7
1.1
Features ...................................................................................................................... 7
1.2
Description ................................................................................................................... 7
1.3
Block Diagram ............................................................................................................... 8
1.4
Pin Descriptions ............................................................................................................. 9
1.5
Package Pin Assignments ............................................................................................... 11
POWER MANAGEMENT CORE ............................................................................................ 12
2.1
Recommended Operating Conditions .................................................................................. 12
2.2
Absolute Maximum Ratings .............................................................................................. 12
2.3
Thermal Information ....................................................................................................... 13
2.4
Quiescent Current ......................................................................................................... 13
2.5
Electrical Characteristics ................................................................................................. 13
2.6
System Operation ......................................................................................................... 17
2.6.1
System Power Up .............................................................................................. 17
2.6.2
System Operation Using Push Button Switch .............................................................. 18
2.6.3
System Operation Using Slider Switch ...................................................................... 19
2.7
Linear Charger Operation ................................................................................................ 20
2.7.1
Battery and TS Detection ...................................................................................... 20
2.7.2
Battery Charging ................................................................................................ 20
2.7.2.1
Pre-charge .......................................................................................... 21
2.7.2.2
Charge Termination ................................................................................ 21
2.7.2.3
Recharge ............................................................................................ 21
2.7.2.4
Charge Timers ...................................................................................... 21
2.7.3
Charger Status (nCHG_STAT Pin) ........................................................................... 22
2.8
LDO Operation ............................................................................................................. 22
2.8.1
LDO Internal Current Limit .................................................................................... 22
2.9
Boost Converter Operation ............................................................................................... 23
2.9.1
Boost Thermal Shutdown ...................................................................................... 23
2.9.2
Boost Load Disconnect ........................................................................................ 24
2.10 Full H-Bridge Analog Switches .......................................................................................... 24
2.10.1 H-Bridge Switch Control ....................................................................................... 24
2.11 Power Management Core Control ....................................................................................... 26
2.11.1 SLEEP / Power Control Pin Function ........................................................................ 26
2.11.2 COMP Pin Functionality ....................................................................................... 26
2.11.3 SW_SEL Pin Functionality .................................................................................... 27
2.11.4 SWITCH Pin ..................................................................................................... 27
2.11.5 Slider Switch Behavior ......................................................................................... 27
2.11.6 Push-Button Switch Behavior ................................................................................. 28
MSP430 CORE .................................................................................................................. 30
3.1
MSP430 Electrical Characteristics ...................................................................................... 30
3.1.1
MSP430 Recommended Operating Conditions ............................................................ 30
3.1.2
Active Mode Supply Current Into VCC Excluding External Current ....................................... 30
3.1.3
Typical Characteristics, Active Mode Supply Current (Into VCC) ......................................... 31
3.1.4
Low-Power Mode Supply Currents (Into VCC) Excluding External Current ............................. 31
3.1.5
Typical Characteristics, Low-Power Mode Supply Currents .............................................. 32
INTRODUCTION
Contents
Copyright © 2011, Texas Instruments Incorporated
TPS65835
SLVSAF6 – JUNE 2011
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4
.............................................................................. 32
.................................................................................... 32
3.1.8
Outputs, Ports Px ............................................................................................... 32
3.1.9
Output Frequency, Ports Px ................................................................................... 33
3.1.10 Typical Characteristics, Outputs .............................................................................. 33
3.1.11 Pin-Oscillator Frequency – Ports Px ......................................................................... 34
3.1.12 Typical Characteristics, Pin-Oscillator Frequency .......................................................... 35
3.1.13 POR/Brownout Reset (BOR) .................................................................................. 35
3.1.14 Typical Characteristics, POR/Brownout Reset (BOR) ..................................................... 36
3.1.15 DCO Frequency ................................................................................................. 37
3.1.16 Calibrated DCO Frequencies, Tolerance .................................................................... 38
3.1.17 Wake-Up From Lower-Power Modes (LPM3/4) ............................................................ 39
3.1.18 Typical Characteristics, DCO Clock Wake-Up Time From LPM3/4 ...................................... 39
3.1.19 Crystal Oscillator, XT1, Low-Frequency Mode ............................................................. 40
3.1.20 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ............................................... 40
3.1.21 Timer_A .......................................................................................................... 41
3.1.22 USCI (UART Mode) ............................................................................................ 41
3.1.23 USCI (SPI Master Mode) ...................................................................................... 41
3.1.24 USCI (SPI Slave Mode) ........................................................................................ 42
3.1.25 USCI (I2C Mode) ............................................................................................... 43
3.1.26 Comparator_A+ ................................................................................................. 44
3.1.27 Typical Characteristics – Comparator_A+ ................................................................... 44
3.1.28 10-Bit ADC, Power Supply and Input Range Conditions .................................................. 45
3.1.29 10-Bit ADC, Built-In Voltage Reference ..................................................................... 46
3.1.30 10-Bit ADC, External Reference .............................................................................. 46
3.1.31 10-Bit ADC, Timing Parameters .............................................................................. 47
3.1.32 10-Bit ADC, Linearity Parameters ............................................................................ 47
3.1.33 10-Bit ADC, Temperature Sensor and Built-In VMID ........................................................ 47
3.1.34 Flash Memory ................................................................................................... 48
3.1.35 RAM .............................................................................................................. 48
3.1.36 JTAG and Spy-Bi-Wire Interface ............................................................................. 48
3.1.37 JTAG Fuse ...................................................................................................... 48
3.2
MSP430 Core Operation ................................................................................................. 49
3.2.1
Description ....................................................................................................... 49
3.2.2
Accessible MSP430 Pins ...................................................................................... 50
3.2.3
MSP430 Port Functions and Programming Options ....................................................... 52
3.2.4
Operating Modes ............................................................................................... 55
3.2.5
MSP430x2xx User's Guide .................................................................................... 55
APPLICATION INFORMATION ............................................................................................. 56
4.1
Applications Schematic ................................................................................................... 56
4.2
Boost Converter Application Information ............................................................................... 56
4.2.1
Setting Boost Output Voltage ................................................................................. 56
4.2.2
Boost Inductor Selection ....................................................................................... 57
4.2.3
Boost Capacitor Selection ..................................................................................... 58
4.3
Bypassing Default Push-Button SWITCH Functionality .............................................................. 58
4.4
MSP430 Programming .................................................................................................... 60
3.1.6
Schmitt-Trigger Inputs, Ports Px
3.1.7
Leakage Current, Ports Px
Copyright © 2011, Texas Instruments Incorporated
Contents
3
TPS65835
SLVSAF6 – JUNE 2011
4.4.1
4
Contents
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Code To Setup Power Functions
.............................................................................
60
Copyright © 2011, Texas Instruments Incorporated
TPS65835
SLVSAF6 – JUNE 2011
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List of Figures
..............................................................................
1-1
TPS65835 Simplified Functional Block Diagram
1-2
TPS65835 Package Pin Assignments ......................................................................................... 11
2-1
System Power Up State Diagram .............................................................................................. 18
2-2
Push Button State Diagram ..................................................................................................... 19
2-3
System Operation Using Slider Switch ........................................................................................ 19
2-4
Thermistor Detection and Circuit
2-5
Battery Charge Phases .......................................................................................................... 21
2-10
Boost Load Disconnect .......................................................................................................... 24
2-11
H-Bridge States ................................................................................................................... 25
2-12
............................................................................................
...................................................................................
COMP Pin Internal Connection .................................................................................................
SWITCH, Slider Power On-Off Behavior ......................................................................................
SWITCH, Push-button Power On Behavior ...................................................................................
SWITCH, Push-button Power Off Behavior ...................................................................................
Safe Operating Area .............................................................................................................
POR/Brownout Reset (BOR) vs Supply Voltage .............................................................................
SPI Master Mode, CKPH = 0 ...................................................................................................
SPI Master Mode, CKPH = 1 ...................................................................................................
SPI Slave Mode, CKPH = 0.....................................................................................................
SPI Slave Mode, CKPH = 1.....................................................................................................
I2C Mode Timing .................................................................................................................
MSP430 Functional Block Diagram ............................................................................................
TPS65835 Applications Schematic ............................................................................................
Boost Feedback Network Schematic ..........................................................................................
Bypassing Default TPS65835 Push Button SWITCH Timing...............................................................
SWITCH Press and SLEEP Signal to Control System Power Off .........................................................
2-13
2-14
2-15
2-16
2-17
3-1
3-12
3-16
3-17
3-18
3-19
3-20
3-24
4-1
4-2
4-3
4-4
..............................................................................................
H-Bridge States from Oscilloscope
SLEEP Signal to Force System Power Off
Copyright © 2011, Texas Instruments Incorporated
List of Figures
8
20
26
26
26
28
29
29
30
36
42
42
43
43
44
50
56
57
58
59
5
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SLVSAF6 – JUNE 2011
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List of Tables
...................................................................................................................
1-1
Pin Descriptions
1-2
Pin Absolute Maximum Ratings ................................................................................................ 10
2-1
nCHG_STAT Functionality ...................................................................................................... 22
2-2
VLDO_SET Functionality ........................................................................................................ 22
2-3
H-Bridge States from Inputs
25
2-4
Scaling Resistors for COMP Pin Function (VVLDO = 2.2 V)
27
2-5
2-6
3-1
3-2
3-3
3-4
3-5
3-6
4-1
6
....................................................................................................
.................................................................
Scaling Resistors for COMP Pin Function (VVLDO = 3.0 V) .................................................................
SW_SEL Settings ................................................................................................................
Internally Connected Pins: MSP430 to Power Management Core ........................................................
Externally Available MSP430 Pins .............................................................................................
Internal MSP430 Pin Functions and Programming Options ................................................................
External MSP430 Port 1 Functions and Programming Options ............................................................
External MSP430 Port 2 Functions and Programming Options ............................................................
External MSP430 Port 3 Functions and Programming Options ............................................................
Recommended RFB1 and RFB2 Values (for IQ(FB) = 5 µA) ....................................................................
List of Tables
9
27
27
50
51
52
53
54
55
57
Copyright © 2011, Texas Instruments Incorporated
TPS65835
SLVSAF6 – JUNE 2011
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Advanced PMU With Integrated MSP430 For Active Shutter 3D Glasses
Check for Samples: TPS65835
1
INTRODUCTION
1.1
Features
• Power Management Core
– Linear Charger
• Three Charger Phases: Pre-charge, Fast
Charge, and Charge Termination
• LED Current Sinks for Power Good and
Charger Status Indication
– LDO Supply for External Modules &
Integrated MSP430 Power
– Boost Converter
• Adjustable Output Voltage: 8 V to 16 V
– Full H-Bridge Analog Switches
• Internally Controlled by MSP430 Core for
System Functions
• MSP430 Core
– Ultralow Power Consumption
• Active Mode: 280 µA at 1 MHz, 2.2 V
• Standby Mode: 0.5 µA
• Off Mode (RAM Retention): 0.1 µA
– Five Power-Saving Modes
12
1.2
– 16-Bit RISC Architecture
– 16 kB Flash
– Two 16-Bit Timer_A Modules With Three
Capture/Compare Registers
– 10-Bit 200-ksps A/D Converter With Internal
Reference, Sample-and-Hold, and Autoscan
– Universal Serial Communications Interface,
Supports IrDA Encode/Decode and
Synchronous SPI
• Enhanced UART Supporting Auto
Baudrate Detection (LIN)
• IrDA Encoder and Decoder
• Synchronous SPI
• I2C™
– Serial Onboard Programming
• No External Programming Voltage
Needed
• Programmable Code Protection by
Security Fuse
– For Complete Module Descriptions, See the
MSP430x2xx Family User's Guide (SLAU144)
Description
The TPS65835 is a PMU for active shutter 3D glasses consisting of a power management core and an
MSP430 microcontroller. The power management core has an integrated power path, linear charger, LDO,
boost converter, and full H-bridge analog switches for left and right shutter operation in a pair of active
shutter 3D glasses. The MSP430 core supports the synchronization and communications from an IR, RF,
or other communications module through the integrated universal serial communications and timer
interfaces for operation of the H-bridge switches on the power management core.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Phillips.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS65835
SLVSAF6 – JUNE 2011
1.3
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Block Diagram
Figure 1-1. TPS65835 Simplified Functional Block Diagram
8
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1.4
Pin Descriptions
Table 1-1. Pin Descriptions
PIN NAME
I/O
PIN NO.
DESCRIPTION
POWER MANAGEMENT CORE (PMIC)
VIN
I
26
AC or USB Adapter Input
ISET
I/O
18
Fast-Charge Current Setting Resistor
TS
I
19
Pin for 10 kΩ NTC Thermistor Connection
FLOAT IF THERMISTOR / TS FUNCTION IS NOT USED
nCHG_STAT
O
38
Open-drain Output, Charger Status Indication
CONNECT TO GROUND IF FUNCTION IS NOT USED
BAT
I/O
22
Charger Power Stage Output and Battery Voltage Sense Input
SYS
O
23
Output Terminal to System
VLDO
O
27
LDO Output
VLDO_SET
I
28
Sets LDO Output Voltage (see Table 2-2)
SWITCH
I
33
Switch Input for Device Power On/Off
SW_SEL
I
35
Selects Type of Switch Connected to SWITCH Pin (see Table 2-6)
BST_SW
I
12
Boost Switch Node
BST_FB
I
15
Boost Feedback Node
BST_OUT
O
11
Boost Output
LCRN
O
8
H-Bridge Output for Right LC Shutter, "Negative" Terminal
LCRP
O
7
H-Bridge Output for Right LC Shutter, "Positive" Terminal
LCLN
O
6
H-Bridge Output for Left LC Shutter, "Negative" Terminal
LCLP
O
5
H-Bridge Output for Left LC Shutter, "Positive" Terminal
PSCL
I/O
37
I2C Clock Pin (only used for TI debug and test)
GROUND PIN IN APPLICATION
PSDA
I/O
36
I2C Data Pin (only used for TI debug and test)
GROUND PIN IN APPLICATION
PGNDBST
-
14
PMIC Boost Power Ground (1)
AGND
-
29
PMIC Analog Ground (1)
DGND
-
4
PMIC Digital Ground (1)
30
General-purpose digital I/O pin
Timer0_A, capture: CCI0A input, compare: Out0 output
USCI_A0 receive data input in UART mode
USCI_A0 slave data out/master in SPI mode
ADC10 analog input A1
Comparator_A+, CA1 input
31
General-purpose digital I/O pin
Timer0_A, capture: CCI1A input, compare: Out1 output
USCI_A0 transmit data output in UART mode
USCI_A0 slave data in/master out in SPI mode
ADC10 analog input A2
Comparator_A+, CA2 input
32
General-purpose digital I/O pin
ADC10, conversion clock output
ADC10 analog input A3
ADC10 negative reference voltage
Comparator_A+, CA3 input
Comparator_A+, output
34
General-purpose digital I/O pin
SMCLK signal output
USCI_B0 slave transmit enable
USCI_A0 clock input/output
ADC10 analog input A4
ADC10 positive reference voltage
Comparator_A+, CA4 input
JTAG test clock, input terminal for device programming and test
MSP430 Microcontroller
P1.1/
TA0.0/
UCA0RXD/
UCA0SOMI/
A1/
CA1
P1.2/
TA0.1/
UCA0TXD/
UCA0SIMO/
A2/
CA2
P1.3/
ADC10CLK/
A3
VREF-/VEREF-/
CA3/
CAOUT
P1.4/
SMCLK/
UCB0STE
UCA0CLK/
A4
VREF+/VEREF+/
CA4
TCK
(1)
I/O
I/O
I/O
I/O
MSP430 ground and grounds for PMIC (Power Management Core) are connected internally.
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Table 1-1. Pin Descriptions (continued)
PIN NAME
P1.5/
TA0.0/
UCB0CLK/
UCA0STE/
A5/
CA5/
TMS
P1.6/
TA0.1/
A6/
CA6/
UCB0SOMI/
UCB0SCL/
TDI/TCLK
I/O
I/O
I/O
PIN NO.
DESCRIPTION
39
General-purpose digital I/O pin
Timer0_A, compare: Out0 output
USCI_B0 clock input/output
USCI_A0 slave transmit enable
ADC10 analog input A5
Comparator_A+, CA5 input
JTAG test mode select, input terminal for device programming and test
13
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
ADC10 analog input A6
Comparator_A+, CA6 input
USCI_B0 slave out/master in SPI mode
USCI_B0 SCL I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
P1.7/
A7/
CA7/
CAOUT/
UCB0SIMO/
UCB0SDA/
TDO/TDI
I/O
16
General-purpose digital I/O pin
ADC10 analog input A7
Comparator_A+, CA7 input
Comparator_A+, output
USCI_B0 slave in/master out in SPI mode
USCI_B0 SDA I2C data in I2C mode
JTAG test data output terminal or test data input during programming and test (2)
P2.1/
TA1.1
I/O
1
General-purpose digital I/O pin
Timer1_A, capture: CCI1A input, compare: Out1 output
P2.2/
TA1.1
I/O
2
General-purpose digital I/O pin
Timer1_A, capture: CCI1B input, compare: Out1 output
P2.6/
XIN/
TA0.1
I/O
24
General-purpose digital I/O pin
XIN, Input terminal of crystal oscillator
TA0.1, Timer0_A, compare: Out1 output
P2.7/
XOUT
I/O
21
General-purpose digital I/O pin
Output terminal of crystal oscillator (3))
P3.3/
TA1.2
I/O
3
General-purpose digital I/O pin
Timer1_A, compare: Out2 output
P3.5/
TA0.1
I/O
9
General-purpose digital I/O pin
Timer0_A, compare: Out0 output
nRST/
NMI/
SBWTDIO
I/O
17
Reset
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/
SBWTCK
I
20
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DVSS
-
25
MSP430 Ground reference (4)
Thermal PAD
-
41
There is an internal electrical connection between the exposed thermal pad and the AGND ground
pin of the device. The thermal pad must be connected to the same potential as the AGND pin on
the printed circuit board. Do not use the thermal pad as the primary ground input for the device.
AGND pin must be connected to ground at all times.
N/C
-
10, 40
MISC. AND PACKAGE
(2)
(3)
(4)
All N/C pins are not connected internally (package to die). They should be connected to the main
system ground.
TDO or TDI is selected via JTAG instruction.
If P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this
pad after reset.
MSP430 ground and grounds for PMIC (Power Management Core) are connected internally.
Table 1-2. Pin Absolute Maximum Ratings
PIN
VALUE / UNIT
Input voltage range on all pins (except for VIN, BST_OUT, BST_SW, BST_FB, VLDO, LCLP, LCLN, LCRP,
LCRN, AGND, DGND, PGNDBST, and MSP430 Core pins) with respect to AGND
-0.3 V to 7.0 V
VIN with respect to AGND
-0.3 V to 28.0 V
BST_OUT, BST_SW with respect to PGNDBST
-0.3 V to 18.0 V
BST_FB with respect to PGNDBST, VLDO with respect to DGND
-0.3 V to 3.6 V
MSP430 Core Pins
-0.3 V to 4.1 V
10
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1.5
Package Pin Assignments
Figure 1-2. TPS65835 Package Pin Assignments
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2
POWER MANAGEMENT CORE
2.1
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
SUBSYSTEM AND PARAMETER
MIN
NOM
MAX
UNIT
CHARGER / POWER PATH
3.7
28 (1)
V
200
mA
VVIN
Voltage range at charger input pin
IVIN
Input current at VIN pin
CVIN
Capacitor on VIN pin
LVIN
Inductance at VIN pin
VSYS
Voltage range at SYS pin
ISYS(OUT)
Output current at SYS pin
CSYS
Capacitor on SYS pin
0.1
VBAT
Voltage range at BAT pin
2.5
6.4
V
CBAT
Capacitor on BAT pin
4.7
10
µF
REXT(nCHG_STAT)
Resistor connected to nCHG_STAT pin to limit
current into pin
320
10
µF
0
2
µH
2.5
6.4
V
100
mA
10
µF
0.1
2.2
4.7
Ω
BOOST CONVERTER / H-BRIDGE SWITCHES
VIN(BST_SW)
Input voltage range for boost converter
VBST_OUT
Output voltage range for boost converter
2.5
6.5
8
16
CBST_OUT
Boost output capacitor
3.3
V
10
µF
LBST_SW (2)
Inductor connected between SYS and BST_SW pins
4.7
10 (3)
µH
1
10
µF
0.4
V
4.7
V
LDO
CVLDO
External decoupling cap on pin VLDO
POWER MANAGEMENT CORE CONTROL (LOGIC LEVELS FOR GPIOs)
VIL(PMIC)
GPIO low level (BST_EN, CHG_EN, SW_SEL,
VLDO_SET and to switch H-Bridge inputs to a low, 0,
level)
VIH(PMIC)
GPIO high level (BST_EN, CHG_EN, SW_SEL,
VLDO_SET and to switch H-Bridge inputs to a high,
1, level)
(1)
(2)
(3)
2.2
1.2
V
VIN pin has 28 V ESD protection
See Section 2.9 for information on boost converter inductor selection.
Design optimized for boost operation with 10 µH inductor
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MINIMUM
MAXIMUM
UNITS
Operating free-air temperature, TA
0
60
°C
Max Junction Temperature, TJ, Electrical Characteristics Guaranteed
0
85
°C
Max Junction temperature, TJ, Functionality Guaranteed (1)
0
105
°C
(1)
12
Device has a thermal shutdown feature implemented that shuts down at 105 °C
POWER MANAGEMENT CORE
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2.3
Thermal Information
TPS65835
THERMAL METRIC
RKP
UNITS
40 PINS
θJA
Junction-to-ambient thermal resistance (1)
31.9
θJCtop
Junction-to-case (top) thermal resistance (2)
22.7
(3)
θJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter (4)
ψJB
Junction-to-board characterization parameter (5)
6.1
(6)
1.4
θJCbot
(1)
(2)
(3)
(4)
(5)
(6)
6.2
Junction-to-case (bottom) thermal resistance
°C/W
0.3
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
2.4
Quiescent Current
over operating free-air temperature range (unless otherwise noted)
TYP
MAX
UNIT
IQ(SLEEP)
Power management core quiescent
current in sleep mode
PARAMETER
@ 25° C
VBAT = 3.6 V
VVIN = 0 V
No load on LDO
CHG_EN, BST_EN grounded
BST_FB = 300 mV
Power management core in sleep
mode / device 'off'
8.6
10.5
µA
IQ(ACTIVE)
Power management core quiescent
current in active mode
@ 25° C
VBAT = 3.6 V
VVIN = 0 V
Boost enabled but not switching,
H-bridge in grounded state
No load on LDO
Power management core in active
mode
39
53.5
µA
MIN
TYP
MAX
UNIT
3.3
3.45
V
2.5
TEST CONDITIONS
MIN
Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
BATTERY CHARGER POWER PATH
VUVLO(VIN)
Undervoltage lockout at power path
input, VIN pin
VVIN: 0 V → 4 V
3.2
VHYS-
Hysteresis on UVLO at power path
input, VIN pin
VVIN: 4 V → 0 V
200
300
mV
UVLO(VIN)
VIN-DT
Input power detection threshold
Input power detected if: (VVIN > VBAT
+ VIN-DT);
VBAT = 3.6 V
VVIN: 3.5 V → 4 V
40
140
mV
VHYS-INDT
Hysteresis on VIN-DT
VBAT = 3.6 V
VVIN: 4 V → 3.5 V
20
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6.4
6.6
6.8
UNIT
VOVP
Input over-voltage protection
threshold
VVIN: 5 V → 7 V
VHYS-OVP
Hysteresis on OVP
VVIN: 11 V → 5 V
VDO(VIN-
VIN pin to SYS pin dropout voltage
VVIN – VSYS
ISYS = 150 mA (including IBAT)
VVIN = 4.35 V
VBAT = 3.6 V
350
mV
BAT pin to SYS pin dropout voltage
VBAT – VSYS
ISYS = 100 mA
VVIN = 0 V
VBAT > 3 V
150
mV
IVIN(MAX)
Maximum power path input current
at pin VIN
VVIN = 5 V
VSUP(ENT)
Enter battery supplement mode
VSYS ≤
(VBAT - 40
mV)
V
VSUP(EXIT)
Exit battery supplement mode
VSYS ≥
(VBAT - 20
mV)
V
VSUP(SC)
Output short-circuit limit in
supplement mode
250
mV
VO(SC)
Output short-circuit detection
threshold, power-on
0.9
V
SYS)
VDO(BATSYS)
105
V
mV
200
mA
BATTERY CHARGER
ICC
Active supply current into VIN pin
IBAT(SC)
Source current for BAT pin
short-circuit detection
VBAT(SC)
BAT pin short-circuit detection
threshold
1.6
1.8
2.0
V
VBAT(REG)
Battery charger output voltage
–1%
4.20
1%
V
VLOWV
Pre-charge to fast-charge transition
threshold
2.9
3.0
3.1
V
ICHG
Charger fast charge current range
ICHG = KISET / RISET
100
mA
KISET
Battery fast charge current set factor VVIN = 5 V
ICHG = KISET / RISET
IVIN(MAX) > ICHG
ICHG = 100 mA
No load on SYS pin, thermal loop
not active.
–20%
450
20%
AΩ
IPRECHG
Pre-charge current
0.07 ×
ICHG
0.10 ×
ICHG
0.15 ×
ICHG
mA
ITERM
Charge current value for termination
detection threshold
ICHG = 100 mA
7
10
15
mA
VRCH
Recharge detection threshold
VBAT below nominal charger voltage,
VBAT(REG)
55
100
170
mV
IBAT(DET)
Sink current for battery detection
tCHG
Charge safety timer
(18000 seconds = 5 hours)
tPRECHG
Pre-charge timer
(1800 seconds = 30 minutes)
VDPPM
DPPM threshold
ILEAK(nCHG) Leakage current for nCHG_STAT
pin
RDSON(nCH
G)
14
VVIN = 5 V
No load on SYS pin
VBAT > VBAT(REG)
2
1
VVIN = 5 V
VBAT(REG) > VBAT > VLOWV
5
mA
1
s
1800
s
VBAT +
100 mV
V
20
POWER MANAGEMENT CORE
mA
18000
VnCHG_STAT = 4.2 V
CHG_EN = LOW (Charger disabled)
On resistance for nCHG_STAT
MOSFET switch
mA
100
nA
60
Ω
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
IMAX(nCHG)
TEST CONDITIONS
MIN
TYP
Maximum input current to
nCHG_STAT pin
MAX
UNIT
50
mA
BATTERY CHARGER NTC MONITOR
75
µA
2100
mV
300
mV
300
mV
30
mV
Charger lower thermal regulation
limit
75
°C
TJ(REG_UPP Charger upper thermal regulation
limit
ER)
95
°C
Charger thermal shutdown
temperature
105
°C
TJ(OFF-HYS) Charger thermal shutdown
hysteresis
20
°C
ITSBIAS
TS pin bias current
VCOLD
0°C charge threshold for 10kΩ NTC
(β = 3490)
VHYS(COLD) Low temperature threshold
hysteresis
VHOT
50°C charge threshold for 10kΩ
NTC
(β = 3490)
VHYS(HOT)
High temperature threshold
hysteresis
Battery charging and battery / NTC
temperature increasing
Battery charging and battery / NTC
temperature decreasing
BATTERY CHARGER THERMAL REGULATION
TJ(REG_LO
WER)
TJ(OFF)
LDO
IMAX(LDO)
Maximum LDO output current,
VVLDO = 2.2 V
VSYS = 4.2 V
VVIN = 0 V
VLDO_SET = 0 V
30
Maximum LDO output current,
VVLDO = 3.0 V
VSYS = 4.2 V
VVIN = 0 V
VLDO_SET = VSYS
30
mA
mA
ISC(LDO)
Short circuit current limit
100
mA
VVLDO
LDO output voltage
VLDO_SET = LOW
(VLDO_SET pin connected to
DGND)
3.7 V ≤ VVIN ≤ 6.5 V
ILOAD(LDO) = -10 mA
2.13
2.2
2.27
V
VVLDO
LDO output voltage
VLDO_SET = HIGH
(VVLDO_SET = VSYS)
3.7 V ≤ VVIN ≤ 6.5 V
ILOAD(LDO) = -10 mA
2.91
3.0
3.09
V
VDO(LDO)
LDO Dropout voltage
VVIN - VLDO when in dropout
ILOAD(LDO) = -10 mA
200
mV
Line regulation
3.7 V ≤ VVIN ≤ 6.5 V
ILOAD(LDO) = -10 mA
-1
1
%
Load regulation
VVIN = 3.5 V
0.1 mA ≤ ILOAD(LDO) ≤ -10 mA
-2
2
%
Power supply rejection ratio
@20 KHz, ILOAD(LDO) = 10 mA
VDO(LDO) = 0.5 V
CVLDO = 10 µF
PSRR
30
45
dB
BOOST CONVERTER
IQ(BST)
Boost operating quiescent current
Boost Enabled, BST_EN = High
IOUT(BST) = 0 mA
(boost is not switching)
VBAT = 3.6 V
RDSON(BST) Boost MOSFET switch on-resistance VIN(BST) = 2.5 V
ISW(MAIN) = 200 mA
2
4.5
µA
0.8
1.2
Ω
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ILKG(BST_S
W)
Leakage into BST_SW pin
(includes leakage into analog
h-bridge switches)
ISWLIM(BST)
Boost MOSFET switch current limit
VDIODE(BST Voltage across integrated boost
diode during normal operation
)
VREF(BST)
TEST CONDITIONS
MIN
TYP
BST_EN signal = LOW (Boost
disabled)
VBST_SW = 4.2 V
No load on BST_OUT pin
100
150
BST_EN signal = HIGH
VBST_SW = 16.0 V
IBST_OUT = - 2 mA
UNIT
90
nA
200
mA
1.0
V
1.17
1.2
1.23
V
VREFHYS(BS Boost reference voltage hysteresis
on BST_FB pin
T)
2
2.5
3.2
%
TON(BST)
Maximum on time detection
threshold
5
6.5
8
µs
TOFF(BST)
Minimum off time detection threshold
1.4
1.75
2.1
TSHUT(BST)
Boost thermal shutdown threshold
105
°C
TSHUT-
Boost thermal shutdown threshold
hysteresis
20
°C
HYS(BST)
Boost reference voltage on BST_FB
pin
MAX
µs
FULL H-BRIDGE ANALOG SWITCHES
IQ(HSW)
Operating quiescent current for
h-bridge switches
RDSON(HSW H-bridge switches on resistance
20
5
µA
40
Ω
)
TDELAY(HS
W-H)
TDELAY(HS
W-L)
H-bridge switch propagation delay,
input switched from low to high
state.
VHBxy = 0 V → VVLDO
100
ns
H-bridge switch propagation delay,
input switched from high to low
state.
VHBxy = VVLDO → 0 V
100
ns
POWER MANAGEMENT CORE CONTROLLER
VIL(PMIC)
Low logic level for logic signals on
IO logic level decreasing:
power management core
VSYS → 0 V
(BST_EN, CHG_EN, SLEEP, HBR1, IIN = 1 mA
HBR2, HBL1, HBL2)
VIH(PMIC)
High logic level for signals on power IO logic level increasing:
management core
0 V → VSYS
(BST_EN, CHG_EN, SLEEP, HBR1, IIN = 1 mA
HBR2, HBL1, HBL2)
VGOOD(LDO Power fault detection threshold
0.4
1.2
V
V
VVLDO decreasing
1.96
V
)
VGOOD_HYS Power fault detection hysteresis
VVLDO increasing
50
mV
(LDO)
VBATCOMP
COMP pin voltage (scaled down
battery voltage)
VBAT = 4.2 V
VVLDO = 2.2 V
1.85
VBAT = 2.5 V
VVLDO = 2.2 V
1.10
VBAT = 4.2 V
VVLDO = 3.0 V
VBAT = 3.3 V
VVLDO = 3.0 V
16
POWER MANAGEMENT CORE
1.90
1.50
V
V
V
V
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2.6
System Operation
The system must complete the power up routine before it enters normal operating mode. The specific
system operation depends on the setting defined by the state of the SW_SEL pin. The details of the
system operation for each configuration of the SW_SEL pin are contained in this section.
2.6.1
System Power Up
Figure 2-1. System Power Up State Diagram
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System Operation Using Push Button Switch
Figure 2-2. Push Button State Diagram
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2.6.3
System Operation Using Slider Switch
Figure 2-3. System Operation Using Slider Switch
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Linear Charger Operation
This device has an integrated Li-Ion battery charger and system power path management feature targeted
at space-limited portable applications. The architecture powers the system while simultaneously and
independently charging the battery. This feature reduces the number of charge and discharge cycles on
the battery, allows for proper charge termination, and enables the system to run with a defective or absent
battery pack. It also allows instant system turn-on even with a totally discharged battery.
The input power source for charging the battery and running the system can be an AC adapter or USB
port connected to the VIN pin as long as the input meets the device operating conditions outlined in this
datasheet. The power-path management feature automatically reduces the charging current if the system
load increases. Note that the charger input, VIN, has voltage protection up to 28 V.
2.7.1
Battery and TS Detection
To detect and determine between a good or damaged battery, the device checks for a short circuit on the
BAT pin by sourcing IBAT(SC) to the battery and monitoring the voltage on the BAT pin. While sourcing this
current if the BAT pin voltage exceeds VBAT(SC), a battery has been detected. If the voltage stays below
the VBAT(SC) level, the battery is presumed to be damaged and not safe to charge.
The device will also check for the presence of a 10 kΩ NTC thermistor attached to the TS pin of the
device. The check for the NTC thermistor on the TS pin is done much like the battery detection feature
described previously. The voltage on the TS pin is compared against a defined level and if it is found to be
above the threshold, the NTC thermistor is assumed to be disconnected or not used in the system. To
reduce the system quiescent current, the NTC thermistor temperature sensing function is only enabled
when the device is charging and when the thermistor has been detected.
Figure 2-4. Thermistor Detection and Circuit
2.7.2
Battery Charging
The battery is charged in three phases: conditioning pre-charge, constant-current fast charge (current
regulation), and a constant-voltage tapering (voltage regulation). In all charge phases, an internal control
loop monitors the IC junction temperature and reduces the charge current if an internal temperature
threshold is exceeded. Figure 2-5 shows what happens in each of the three charge phases:
20
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Figure 2-5. Battery Charge Phases
In the pre-charge phase, the battery is charged with the pre-charge current that is scaled to be 10% of the
fast-charge current set by the resistor connected to the ISET pin. Once the battery voltage crosses the
VLOWV threshold, the battery is charged with the fast-charge current (ICHG). As the battery voltage reaches
VBAT(REG), the battery is held at a constant voltage of VBAT(REG) and the charge current tapers off as the
battery approaches full charge. When the battery current reaches ITERM, the charger indicates charging is
done by making the nCHG_STAT pin high impedance. Note that termination detection is disabled
whenever the charge rate is reduced from the set point because of the actions of the thermal loop, the
DPM loop, or the VIN(LOWV) loop.
2.7.2.1
Pre-charge
The value for the pre-charge current is set to be 10% of the charge current that is set by the external
resistor, RISET. Pre-charge current is scaled to lower currents when the charger is in thermal regulation.
2.7.2.2
Charge Termination
In the fast charge state, once VBAT ≥ VBAT(REG), the charger enters constant voltage mode. In constant
voltage mode, the charge current will taper until termination when the charge current falls below the I(TERM)
threshold (typically 10% of the programmed fast charge current). Termination current is not scaled when
the charger is in thermal regulation. When the charging is terminated, the nCHG_STAT pin will be high
impedance (effectively turning off any LED that is connected to this pin).
2.7.2.3
Recharge
Once a charge cycle is complete and termination is reached, the battery voltage is monitored. If VBAT <
VBAT(REG) - VRCH, the device determines if the battery has been removed. If the battery is still present, then
the recharge cycle begins and will end when VBAT ≥ VBAT(REG).
2.7.2.4
Charge Timers
The charger in this device has internal safety timers for the pre-charge and fast charge phases to prevent
potential damage to either the battery or the system. The default values for these timers are found as
follows: Pre-charge timer = 0.5 hours (30 minutes) and Fast charge timer = 5 hours (300 minutes).
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During the fast charge phase, the following events may increase the timer durations:
1. The system load current activates the DPM loop which reduces the available charging current
2. The input current is reduced because the input voltage has fallen to VIN(LOW)
3. The device has entered thermal regulation because the IC junction temperature has exceeded TJ(REG)
During each of these events, the internal timers are slowed down proportionately to the reduction in
charging current.
If the pre-charge timer expires before the battery voltage reaches VLOWV, the charger indicates a fault
condition.
2.7.3
Charger Status (nCHG_STAT Pin)
The nCHG_STAT pin is used to indicate the charger status by an externally connected resistor and LED
circuit. The pin is an open drain input and the internal switch is controlled by the logic inside of the
charger. This pin may also be connected to a GPIO of the system MCU to indicate charging status. The
table below details the status of the nCHG_STAT pin for various operating states of the charger.
Table 2-1. nCHG_STAT Functionality
Charging Status
2.8
nCHG_STAT FET / LED
Pre-charge / Fast Charge / Charge Termination
ON
Recharge
OFF
OVP
OFF
SLEEP
OFF
LDO Operation
The power management core has a low dropout linear regulator (LDO) with variable output voltage
capability. This LDO is used for supplying the microcontroller and may be used to supply either an
external IR or RF module, depending on system requirements. The LDO can supply a continuous current
of up to 30 mA.
The output voltage (VVLDO) of the LDO is set by the state of the VLDO_SET pin. See Table 2-2 for details
on setting the LDO output voltage.
Table 2-2. VLDO_SET Functionality
2.8.1
VLDO_SET State
VLDO Output Voltage (VVLDO)
Low (VLDO_SET < VIL(PMIC))
2.2 V
High (VLDO_SET > VIH(PMIC))
3.0 V
LDO Internal Current Limit
The internal current limit feature helps to protect the LDO regulator during fault conditions. During current
limit, the output sources a fixed amount of current that is defined in the electrical specification table. The
voltage on the output in this stage can not be regulated and will be VOUT = ILIMIT × RLOAD. The pass
transistor integrated into the LDO will dissipate power, (VIN - VOUT) × ILIMIT, until the device enters thermal
shutdown. In thermal shutdown the device will enter the "SLEEP / POWER OFF" state which means that
the LDO will then be disabled and shut off.
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2.9
Boost Converter Operation
The boost converter in this device is designed for the load of active shutter 3D glasses. This load is
typically a light load where the average current is 2 mA or lower and the peak current out of a battery is
limited in operation. This asynchronous boost converter operates with a minimum off time / maximum on
time for the integrated low side switch, these values are specified in the electrical characteristics table of
this datasheet.
The peak output voltage from the boost converter is adjustable and set by using an external resistor
divider connected between BST_OUT, the BST_FB pin, and ground. The peak output voltage is set by
choosing resistors for the feedback network such that the voltage on the BST_FB pin is VREF(BST) = 1.2 V.
See Section 4.2 for more information on calculating resistance values for this feedback network.
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
The efficiency curves for various input voltages over the typical 3D glasses load range (2 mA and lower)
are shown below. All curves are for a target VOUT of 16 V. For output voltages less than 16 V, a higher
efficiency at each operating input voltage should be expected. Note that efficiency is dependent upon the
external boost feedback network resistances, the inductor used, and the type of load connected.
60
50
40
40
30
20
20
VIN = 3.0 V
0
0.01
10
VOUT = 16.0 V
0.1
Output Current (mA)
1
VIN = 3.7 V
0
0.01
2
G000
Figure 2-6. Boost Efficiency vs. IOUT, VIN = 3.0 V,
VOUT = 16 V
100
90
80
80
70
70
50
40
20
0.1
Output Current (mA)
1
10
2
VIN = 5.5 V
0
0.01
G000
Figure 2-8. Boost Efficiency vs. IOUT, VIN = 4.2 V,
VOUT = 16 V
G000
40
30
VOUT = 16.0 V
2
50
20
VIN = 4.2 V
0
0.01
1
60
30
10
0.1
Output Current (mA)
100
90
60
VOUT = 16.0 V
Figure 2-7. Boost Efficiency vs. IOUT, VIN = 3.7 V,
VOUT = 16 V
Efficiency (%)
Efficiency (%)
50
30
10
2.9.1
60
VOUT = 16.0 V
0.1
Output Current (mA)
1
2
G000
Figure 2-9. Boost Efficiency vs. IOUT, VIN = 5.5 V,
VOUT = 16 V
Boost Thermal Shutdown
An internal thermal shutdown mode is implemented in the boost converter that shuts down the device if
the typical junction temperature of 105°C is exceeded. If the device is in thermal shutdown mode, the
main switch of the boost is open and the device enters the "SLEEP / POWER OFF" state.
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Boost Load Disconnect
When the boost is disabled (BST_EN = LOW), the H-bridge is automatically placed into the OFF state. In
the OFF state the high side H-bridge switches are open and the low side switches of the H-bridge are
closed. The OFF state grounds and discharges the load, potentially prolonging the life of the LC shutters
by eliminating any DC content (see Section 2.10.1 for more information regarding the H-bridge states).
The disconnection of the load is done with the H-Bridge and can be seen in the next figure (Figure 2-10).
Figure 2-10. Boost Load Disconnect
An advantage to this topology for disconnecting the load is that the boost output capacitor is charged to
approximately the SYS voltage level, specifically VSYS - VDIODE(BST), when the boost is disabled. This
design ensures that there is not a large in-rush current into the boost output capacitor when the boost is
enabled. The boost operation efficiency is also increased because there is no load disconnect switch in
the boost output path, such a switch would decrease efficiency because of the resistance that it would
introduce.
2.10 Full H-Bridge Analog Switches
The TPS65835 has two integrated full H-bridge analog switches that are connected to GPIO ports on the
MSP430 and can be controlled by the MSP430 core for various system functions. There is an internal
level shifter that takes care of the input signals to the H-Bridge switches.
2.10.1 H-Bridge Switch Control
The H-Bridge switches are controlled by the MSP430 core for system operation - specifically to control
charge polarity on the LCD shutters. Depending on the state of the signals from the MSP430 core, the
H-Bridge will be put into 4 different states. These states are:
• OPEN: All Switches Opened
• CHARGE+: Boost Output Voltage Present on Pins LCLP or LCRP
• CHARGE-: Boost Output Voltage Present on Pins LCLN or LCRN
• GROUNDED: High side switches are opened and low side switches are closed
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If CHARGE+ state is followed by the CHARGE- state, the voltage across the capacitor connected to the
H-Bridge output terminals will be reversed. The system is automatically put into the GROUNDED state
when the boost is disabled by the BST_EN pin - for more details see Section 2.6.
Table 2-3. H-Bridge States from Inputs
HBx2 [HBL2 & HBR2]
HBx1 [HBL1 & HBR1]
0
0
OPEN
0
1
CHARGE +
1
0
CHARGE -
1
1
GROUNDED
H-Bridge State
Figure 2-11. H-Bridge States
Figure 2-12. H-Bridge States from Oscilloscope
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2.11 Power Management Core Control
The power management core is controlled with external pins that can set system behavior by their status
along with internal connections to GPIOs from the MSP430 that can be modified depending on the code
implemented in the MSP430.
2.11.1 SLEEP / Power Control Pin Function
The internal SLEEP signal between the power management device and the MSP430 can be used to
control the power down behavior of the device. This has multiple practical applications such as a
watchdog implementation for the communication between the sender (TV) and the 3D glasses (receiver)
or different required system on and off times; typically when the push-button press timing for an off event
is a few seconds in length, programmable by software in the system MCU.
If there is a requirement that the push-button press for system on and off events are different, the SLEEP
signal must be set to a logic high value (VSLEEP > VIH(PMIC)) upon system startup. This implementation
allows the device to power down the system on the falling edge of the SLEEP signal
(when: VSLEEP < VIL(PMIC)).
Figure 2-13. SLEEP Signal to Force System Power Off
2.11.2 COMP Pin Functionality
The COMP pin is used to output a scaled down voltage level related to the battery voltage for input to the
comparator of the MSP430. Applications for this COMP feature could be to generate an interrupt on the
MSP430 when the battery voltage drops under a threshold and the device can then be shut down or
indicate to the end user with an LED that the battery requires charging.
Figure 2-14. COMP Pin Internal Connection
26
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Table 2-4. Scaling Resistors for COMP Pin Function
(VVLDO = 2.2 V)
Scaling Resistors for COMP Pin
Function
Value
RBSCL1
3.0 MΩ
RBSCL2
2.36 MΩ
Table 2-5. Scaling Resistors for COMP Pin Function
(VVLDO = 3.0 V)
Scaling Resistors for COMP Pin
Function
Value
RBSCL1
3.0 MΩ
RBSCL2
2.48 MΩ
Using the designed values in Table 2-4 or Table 2-5, the voltage on the COMP pin will be: VCOMP = 0.5 ×
VVLDO + 300 mV. This assures that the COMP pin voltage will be close to half of the LDO output voltage
plus the LDO dropout voltage of the device. The COMP pin can also be used as an input to ADC channel
A0 of the integrated MSP430 microcontroller. This is useful if greater measurement accuracy or increased
functionality is desired from this function.
2.11.3 SW_SEL Pin Functionality
The SW_SEL pin is used to select what type of switch is connected to the SWITCH pin of the device.
Selection between a push-button and a slider switch can be made based on the state of this pin.
Table 2-6. SW_SEL Settings
SW_SEL State
Type of Switch Selected
Low
(VSW_SEL < VIL(PMIC))
Slider Switch
High
(VSW_SEL > VIH(PMIC))
Push-button
When the push button switch type is selected, the device will debounce the SWITCH input with a 32 ms
timer for both the ON and OFF events and either power on or off the device. Using the push-button switch
function, the ON and OFF timings are equal; tON = tOFF. If the system requirements are such that the on
and off timings should be different, tON ≠ tOFF, then refer to the following section for the correct system
setup: Section 4.3. When the slider switch operation is selected, the SWITCH pin must be externally
pulled up to the SYS voltage with a resistor and the output connected to the slider switch. When the
SWITCH pin is pulled to ground, the device will turn on and enter the power up sequence.
2.11.4 SWITCH Pin
The SWITCH pin behavior is defined by the SW_SEL pin (Section 2.11.3) which defines the type of switch
that is connected to the system; either a slider switch or push-button.
2.11.5 Slider Switch Behavior
If a slider switch is connected in the system then the system power state and VLDO output (which powers
the internal MSP430) is defined by the state of the slider switch. If the slider is in the "off" position than the
SWITCH pin should be connected to the SYS pin. If the slider is in the "on" position than the SWITCH pin
should be connected to ground. Figure 2-15 details the system operation using the slider switch
configuration.
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Figure 2-15. SWITCH, Slider Power On-Off Behavior
2.11.6 Push-Button Switch Behavior
The system is powered on or off by a push-button press after a press that is greater than 32 ms. The
following figures (Figure 2-16 and Figure 2-17) show the system behavior and the expected VLDO output
during the normal push-button operation where the ON and OFF press timings are the same value,
tON = tOFF.
Figure 2-16. SWITCH, Push-button Power On Behavior
28
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Figure 2-17. SWITCH, Push-button Power Off Behavior
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3
MSP430 CORE
3.1
MSP430 Electrical Characteristics
3.1.1
MSP430 Recommended Operating Conditions
MIN
VCC
Supply voltage
VSS
Supply voltage
(1)
(2)
MAX
1.8
3.6
During flash
programming/erase
2.2
3.6
0
Processor frequency (maximum MCLK frequency using the
USART module) (1) (2)
fSYSTEM
NOM
During program execution
UNIT
V
V
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
6
VCC = 2.7 V,
Duty cycle = 50% ± 10%
dc
12
VCC = 3.3 V,
Duty cycle = 50% ± 10%
dc
16
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend :
System Frequency - MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
1.8 V
Note:
2.7 V
2.2 V
Supply Voltage - V
3.3 V 3.6 V
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 3-1. Safe Operating Area
3.1.2
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (3) (4)
PARAMETER
IAM,1MHz
(3)
(4)
30
Active mode (AM)
current at 1 MHz
TEST CONDITIONS
TA
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 0 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
VCC
MIN
TYP
2.2 V
230
3V
330
MAX
420
UNIT
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
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3.1.3
Typical Characteristics, Active Mode Supply Current (Into VCC)
5.0
4.0
Active Mode Current − mA
Active Mode Current − mA
f DCO = 16 MHz
4.0
3.0
f DCO = 12 MHz
2.0
f DCO = 8 MHz
1.0
TA = 85 °C
3.0
TA = 25 °C
VCC = 3 V
2.0
TA = 85 °C
TA = 25 °C
1.0
f DCO = 1 MHz
0.0
1.5
2.0
2.5
3.0
3.5
VCC = 2.2 V
0.0
0.0
4.0
4.0
VCC − Supply Voltage − V
Figure 3-2. Active Mode Current vs VCC, TA = 25°C
3.1.4
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 3-3. Active Mode Current vs DCO Frequency
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TA
VCC
Low-power mode 0
(LPM0) current (1)
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
25°C
2.2 V
56
µA
ILPM2
Low-power mode 2
(LPM2) current (2)
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
22
µA
ILPM3,LFXT1
Low-power mode 3
(LPM3) current (2)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
0.7
1.5
µA
ILPM3,VLO
Low-power mode 3
current, (LPM3) (2)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
0.5
0.7
µA
0.5
Low-power mode 4
(LPM4) current (3)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
0.1
ILPM4
0.8
1.7
ILPM0,1MHz
(1)
(2)
(1)
(2)
(3)
TEST CONDITIONS
25°C
85°C
2.2 V
MIN
(2)
TYP
MAX
UNIT
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
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Typical Characteristics, Low-Power Mode Supply Currents
3.00
2.50
2.75
2.25
ILPM4 – Low-Power Mode Current – µA
ILPM3 – Low-Power Mode Current – µA
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
2.50
2.25
2.00
1.75
1.50
Vcc = 3.6 V
1.25
Vcc = 3 V
1.00
Vcc = 2.2 V
0.75
0.50
2.00
1.75
1.50
0.00
-40
0
-20
40
20
60
Vcc = 3.6 V
1.00
Vcc = 3 V
0.75
Vcc = 2.2 V
0.50
Vcc = 1.8 V
0.25
1.25
0.25
0.00
-40
80
Vcc = 1.8 V
0
-20
40
60
80
TA – Temperature – °C
TA – Temperature – °C
Figure 3-4. LPM3 Current vs Temperature
3.1.6
20
Figure 3-5. LPM4 Current vs Temperature
Schmitt-Trigger Inputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
MIN
RPull
Pullup/pulldown resistor
CI
Input capacitance
VIN = VSS or VCC
TYP
MAX
UNIT
0.45 VCC
0.75 VCC
1.35
2.25
0.25 VCC
0.55 VCC
3V
0.75
1.65
3V
0.3
1
V
3V
20
50
kΩ
3V
For pullup: VIN = VSS
For pulldown: VIN = VCC
3.1.7
VCC
35
5
V
V
pF
Leakage Current, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
TEST CONDITIONS
VCC
(1) (2)
High-impedance leakage current
MIN
3V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
3.1.8
Outputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
I(OHmax) = –6 mA (1)
3V
VCC – 0.3
V
VOL
Low-level output voltage
I(OLmax) = 6 mA (1)
3V
VSS + 0.3
V
(1)
32
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
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3.1.9
Output Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Port output frequency
(with load)
fPx.y
fPort_CLK
(1)
(2)
TEST CONDITIONS
Clock output frequency
Px.y, CL = 20 pF, RL = 1 kΩ (1)
Px.y, CL = 20 pF
VCC
(2)
(2)
MIN
TYP
MAX
UNIT
3V
12
MHz
3V
16
MHz
A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
3.1.10 Typical Characteristics, Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
VCC = 2.2 V
P1.7
TA = 25°C
25
TA = 85°C
20
15
10
5
0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
30
VCC = 3 V
P1.7
TA = 25°C
40
TA = 85°C
30
20
10
0
0
0.5
1
1.5
2
2.5
0
VOL − Low-Level Output Voltage − V
Figure 3-6.
0.5
1
1.5
2
2.5
3
3.5
VOL − Low-Level Output Voltage − V
Figure 3-7.
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over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
VCC = 2.2 V
P1.7
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
0
−5
−10
−15
TA = 85°C
−20
TA = 25°C
−25
0
0.5
VCC = 3 V
P1.7
−10
−20
−30
TA = 85°C
−40
TA = 25°C
−50
1
1.5
2
2.5
0
0.5
VOH − High-Level Output Voltage − V
1
1.5
2
2.5
3
3.5
MAX
UNIT
VOH − High-Level Output Voltage − V
Figure 3-8.
Figure 3-9.
3.1.11 Pin-Oscillator Frequency – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
foP1.x
Port output oscillation frequency
foP2.x
Port output oscillation frequency
foP2.6/7
Port output oscillation frequency
foP3.x
Port output oscillation frequency
(1)
(2)
34
TEST CONDITIONS
P1.y, CL = 10 pF, RL = 100 kΩ
VCC
(1) (2)
3V
P1.y, CL = 20 pF, RL = 100 kΩ (1) (2)
P2.0 to P2.5, CL = 10 pF, RL = 100 kΩ (1) (2)
P2.0 to P2.5, CL = 20 pF, RL = 100 kΩ
P2.6 and P2.7, CL = 20 pF, RL = 100
kΩ (1) (2)
(1) (2)
MIN
TYP
1400
900
1800
3V
1000
3V
700
P3.y, CL = 10 pF, RL = 100 kΩ (1) (2)
1800
(1) (2)
1000
P3.y, CL = 20 pF, RL = 100 kΩ
kHz
kHz
kHz
kHz
A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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3.1.12 Typical Characteristics, Pin-Oscillator Frequency
TYPICAL OSCILLATING FREQUENCY
vs
LOAD CAPACITANCE
TYPICAL OSCILLATING FREQUENCY
vs
LOAD CAPACITANCE
1.50
VCC = 3.0 V
1.35
fosc − Typical Oscillation Frequency − MHz
fosc − Typical Oscillation Frequency − MHz
1.50
1.20
1.05
P1.y
0.90
P2.0 ... P2.5
0.75
P2.6, P2.7
0.60
0.45
0.30
0.15
0.00
VCC = 2.2 V
1.35
1.20
1.05
P1.y
0.90
P2.0 ... P2.5
0.75
P2.6, P2.7
0.60
0.45
0.30
0.15
0.00
10
50
100
10
CLOAD − External Capacitance − pF
50
100
CLOAD − External Capacitance − pF
A. One output active at a time.
B. One output active at a time.
Figure 3-10.
Figure 3-11.
3.1.13 POR/Brownout Reset (BOR) (3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
0.7 ×
UNIT
VCC(start)
See Figure 3-12
dVCC/dt ≤ 3 V/s
V(B_IT–)
See Figure 3-12 through Figure 3-14
dVCC/dt ≤ 3 V/s
1.35
V
Vhys(B_IT–)
See Figure 3-12
dVCC/dt ≤ 3 V/s
140
mV
td(BOR)
See Figure 3-12
2000
µs
t(reset)
Pulse length needed at RST/NMI pin to
accepted reset internally
(3)
V(B_IT--)
2.2 V
V
µs
2
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) +
Vhys(B_IT–)is ≤ 1.8 V.
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VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 3-12. POR/Brownout Reset (BOR) vs Supply Voltage
3.1.14 Typical Characteristics, POR/Brownout Reset (BOR)
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
t pw − Pulse Width − µs
1 ns
t pw − Pulse Width − µs
Figure 3-13. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
t f = tr
1
1000
tf
tr
t pw − Pulse Width − µs
t pw − Pulse Width − µs
Figure 3-14. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
36
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3.1.15 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
Supply voltage
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
RSELx = 15
3
3.6
0.14
MHz
0.17
MHz
V
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
3V
0.06
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
3V
0.07
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
3V
0.15
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
3V
0.21
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
3V
0.30
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
3V
0.41
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
3V
0.58
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
3V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
3V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
3V
1.6
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
3V
2.3
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
3V
3.4
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
3V
4.25
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
3V
4.30
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
3V
6.00
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
3V
8.60
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3V
1.35
ratio
SDCO
Frequency step between
tap DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
3V
1.08
ratio
Measured at SMCLK output
3V
50
Duty cycle
MHz
7.30
MHz
9.60
MHz
13.9
MHz
12.0
18.5
MHz
16.0
26.0
MHz
7.8
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3.1.16 Calibrated DCO Frequencies, Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
1-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
3
%
1-MHz tolerance over VCC
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
30°C
1.8 V to 3.6 V
-3
±2
3
%
1-MHz tolerance overall
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
1.8 V to 3.6 V
-6
±3
6
%
8-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
3
%
8-MHz tolerance over VCC
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
30°C
2.2 V to 3.6 V
-3
±2
3
%
8-MHz tolerance overall
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
2.2 V to 3.6 V
-6
±3
6
%
12-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
3
%
12-MHz tolerance over VCC
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
30°C
2.7 V to 3.6 V
-3
±2
3
%
12-MHz tolerance overall
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
2.7 V to 3.6 V
-6
±3
6
%
16-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
3
%
16-MHz tolerance over VCC
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
30°C
3.3 V to 3.6 V
-3
±2
3
%
16-MHz tolerance overall
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
3.3 V to 3.6 V
-6
±3
6
%
(1)
38
This is the frequency change from the measured frequency at 30°C over temperature.
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3.1.17 Wake-Up From Lower-Power Modes (LPM3/4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tDCO,LPM3/4
DCO clock wake-up time from
LPM3/4 (1)
tCPU,LPM3/4
CPU wake-up time from LPM3/4 (2)
(1)
(2)
VCC
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz
MIN
TYP
3V
MAX
UNIT
1.5
µs
1/fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
3.1.18 Typical Characteristics, DCO Clock Wake-Up Time From LPM3/4
DCO Wake Time − µs
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 3-15. DCO Wake-Up Time From LPM3 vs DCO Frequency
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3.1.19 Crystal Oscillator, XT1, Low-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER (1)
TEST CONDITIONS
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
LF mode
OALF
Oscillation allowance for
LF crystals
Integrated effective load
capacitance, LF mode (2)
CL,eff
XTS = 0, LFXT1Sx = 0 or 1
10000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Oscillator fault frequency,
LF mode (3)
XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4)
UNIT
Hz
50000
Hz
kΩ
XTS = 0, XCAPx = 0
fFault,LF
(4)
1.8 V to 3.6 V
MAX
32768
500
LF mode
(3)
TYP
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
Duty cycle
(2)
MIN
1.8 V to 3.6 V
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
(1)
VCC
2.2 V
30
2.2 V
10
50
pF
70
%
10000
Hz
To
•
•
•
•
•
•
•
improve EMI on the XT1 oscillator, the following guidelines should be observed.
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
3.1.20 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TA
VCC
MIN
TYP
MAX
fVLO
VLO frequency
PARAMETER
-40°C to 85°C
3V
4
12
20
dfVLO/dT
VLO frequency temperature drift
-40°C to 85°C
3V
25°C
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
40
MSP430 CORE
UNIT
kHz
0.5
%/°C
4
%/V
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3.1.21 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
SMCLK, duty cycle = 50% ± 10%
tTA,cap
Timer_A capture timing
TA0, TA1
VCC
MIN
3V
20
TYP
MAX
fSYSTEM
UNIT
MHz
ns
3.1.22 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
SMCLK, duty cycle = 50% ± 10%
fUSCI
USCI input clock frequency
fmax,BITCLK
Maximum BITCLK clock frequency
(equals baudrate in MBaud) (1)
3V
2
tτ
UART receive deglitch time (2)
3V
50
(1)
(2)
TYP
MAX
fSYSTEM
UNIT
MHz
MHz
100
600
ns
The DCO wake-up time must be considered in LPM3/4 for baud rates above 1 MHz.
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their width should exceed the maximum specification of the deglitch time.
3.1.23 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 3-16
and Figure 3-17)
PARAMETER
TEST CONDITIONS
VCC
MIN
SMCLK, duty cycle = 50% ± 10%
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
3V
75
tHD,MI
SOMI input data hold time
3V
0
tVALID,MO
SIMO output data valid time
UCLK edge to SIMO valid, CL = 20 pF
3V
TYP
MAX
UNIT
fSYSTEM
MHz
ns
ns
20
ns
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 3-16. SPI Master Mode, CKPH = 0
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 3-17. SPI Master Mode, CKPH = 1
3.1.24 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 3-18
and Figure 3-19)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
STE lead time, STE low to clock
3V
tSTE,LAG
STE lag time, Last clock to STE high
3V
tSTE,ACC
STE access time, STE low to SOMI data out
3V
50
ns
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
3V
50
ns
tSU,SI
SIMO input data setup time
3V
15
ns
tHD,SI
SIMO input data hold time
3V
10
ns
tVALID,SO
UCLK edge to SOMI valid,
CL = 20 pF
SOMI output data valid time
tSTE,LEAD
3V
50
UNIT
tSTE,LEAD
ns
10
ns
50
75
ns
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,SI
tLO/HI
tHD,SI
SIMO
tSTE,ACC
tHD,SO
tVALID,SO
tSTE,DIS
SOMI
Figure 3-18. SPI Slave Mode, CKPH = 0
42
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tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tHD,MO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 3-19. SPI Slave Mode, CKPH = 1
3.1.25 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 3-20)
PARAMETER
TEST CONDITIONS
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
3V
0
TYP
SMCLK, duty cycle = 50% ± 10%
fSCL ≤ 100 kHz
MAX
UNIT
fSYSTEM
MHz
400
kHz
4.0
3V
µs
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
3V
0
tSU,DAT
Data setup time
3V
250
ns
tSU,STO
Setup time for STOP
3V
4.0
µs
tSP
Pulse width of spikes suppressed by
input filter
3V
50
fSCL > 100 kHz
fSCL ≤ 100 kHz
4.7
3V
fSCL > 100 kHz
tSU,STA
tHD,STA
0.6
µs
0.6
tHD,STA
ns
100
600
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 3-20. I2C Mode Timing
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3.1.26 Comparator_A+
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
I(DD)
I(Refladder/
RefDiode)
VCC
MIN
TYP
MAX
UNIT
CAON = 1, CARSEL = 0, CAREF = 0
3V
45
µA
CAON = 1, CARSEL = 0, CAREF = 1/2/3,
No load at CA0 and CA1
3V
45
µA
V(IC)
Common–mode input voltage
CAON = 1
3V
V(Ref025)
(Voltage at 0.25 VCC node) / VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at CA0 and CA1
3V
0.24
V(Ref050)
(Voltage at 0.5 VCC node) / VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at CA0 and CA1
3V
0.48
V(RefVT)
See Figure 3-21 and Figure 3-22
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at CA0 and CA1, TA = 85°C
3V
490
mV
V(offset)
Offset voltage (2)
3V
±10
mV
Vhys
Input hysteresis
3V
0.7
mV
120
ns
1.5
µs
TA = 25°C, Overdrive 10 mV,
Without filter: CAF = 0
Response time
(low-high and high-low)
t(response)
(1)
(2)
CAON = 1
0
VCC-1
V
3V
TA = 25°C, Overdrive 10 mV,
With filter: CAF = 1
The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification.
The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The
two successive measurements are then summed together.
3.1.27 Typical Characteristics – Comparator_A+
650
650
VCC = 2.2 V
V(RefVT) – Reference Voltage – mV
V(RefVT) – Reference Voltage – mV
VCC = 3 V
600
Typical
550
500
450
400
-45
Typical
550
500
450
400
-25
-5
15
35
55
75
TA – Free-Air Temperature – °C
95
115
Figure 3-21. V(RefVT) vs Temperature, VCC = 3 V
44
600
-45
-25
-5
15
35
55
75
TA – Free-Air Temperature – °C
95
115
Figure 3-22. V(RefVT) vs Temperature, VCC = 2.2 V
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Short Resistance – kW
100
VCC = 1.8 V
VCC = 2.2 V
VCC = 3 V
10
VCC = 3.6 V
1
0
0.2
0.4
0.6
0.8
1
VIN/VCC – Normalized Input Voltage – V/V
Figure 3-23. Short Resistance vs VIN/VCC
3.1.28 10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (3)
PARAMETER
VCC
TEST CONDITIONS
Analog supply voltage
VAx
Analog input voltage
IADC10
IREF+
VCC
VSS = 0 V
(1)
ADC10 supply current
TA
(2)
Reference supply current,
reference buffer disabled (3)
All Ax terminals, Analog inputs
selected in ADC10AE register
fADC10CLK = 5.0 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
3V
25°C
3V
MIN
TYP
MAX
UNIT
2.2
3.6
V
0
VCC
V
0.6
mA
0.25
25°C
3V
mA
0.25
IREFB,0
fADC10CLK = 5.0 MHz,
Reference buffer supply
ADC10ON = 0, REFON = 1,
current with ADC10SR = 0 (3) REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
25°C
3V
1.1
mA
IREFB,1
fADC10CLK = 5.0 MHz,
Reference buffer supply
ADC10ON = 0, REFON = 1,
current with ADC10SR = 1 (3) REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
25°C
3V
0.5
mA
CI
Input capacitance
Only one terminal Ax can be selected
at one time
25°C
3V
Input MUX ON resistance
0 V ≤ VAx ≤ VCC
25°C
3V
RI
(3)
(1)
(2)
(3)
27
1000
pF
Ω
The leakage current is defined in the leakage current table with Px.y/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
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3.1.29 10-Bit ADC, Built-In Voltage Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC,REF+
IVREF+ ≤ 1 mA, REF2_5V = 0
Positive built-in reference
analog supply voltage range IVREF+ ≤ 1 mA, REF2_5V = 1
VREF+
Positive built-in reference
voltage
ILD,VREF+
Maximum VREF+ load
current
VREF+ load regulation
IVREF+ ≤ IVREF+max, REF2_5V = 0
IVREF+ ≤ IVREF+max, REF2_5V = 1
VCC
MIN
TYP
2.2
3V
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≉ 1.25 V,
REF2_5V = 1
UNIT
V
2.9
1.41
1.5
1.59
2.35
2.5
2.65
±1
3V
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≉ 0.75 V,
REF2_5V = 0
MAX
V
mA
±2
3V
LSB
±2
VREF+ load regulation
response time
IVREF+ = 100 µA→900 µA,
VAx ≉ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB,
ADC10SR = 0
3V
400
ns
CVREF+
Maximum capacitance at
pin VREF+
IVREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1
3V
100
pF
TCREF+
Temperature coefficient
IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA
3V
±100
ppm/
°C
tREFON
Settling time of internal
reference voltage to 99.9%
VREF
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 → 1
3.6 V
30
µs
tREFBURST
Settling time of reference
buffer to 99.9% VREF
IVREF+ = 0.5 mA,
REF2_5V = 1, REFON = 1,
REFBURST = 1, ADC10SR = 0
3V
2
µs
3.1.30 10-Bit ADC, External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VEREF+
Positive external reference input
voltage range (1)
TEST CONDITIONS
3
0
1.2
V
1.4
VCC
V
Differential external reference
input voltage range,
ΔVEREF = VEREF+ – VEREF–
VEREF+ > VEREF–
(1)
(2)
(3)
(4)
46
Static input current into VEREF–
UNIT
1.4
ΔVEREF
IVEREF–
MAX
VEREF– ≤ VEREF+ ≤ VCC – 0.15 V,
SREF1 = 1, SREF0 = 1 (2)
VEREF+ > VEREF–
(1)
TYP
VCC
Negative external reference input
voltage range (3)
Static input current into VEREF+
MIN
1.4
VEREF–
IVEREF+
VCC
VEREF+ > VEREF–,
SREF1 = 1, SREF0 = 0
V
(4)
0 V ≤ VEREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
3V
±1
0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1 (2)
3V
0
0 V ≤ VEREF– ≤ VCC
3V
±1
µA
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
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3.1.31 10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC10SR = 0
fADC10CLK
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10OSC
ADC10 built-in oscillator
frequency
ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
tCONVERT
Conversion time
tADC10ON
Turn-on settling time of
the ADC
(1)
VCC
ADC10SR = 1
MIN
TYP
MAX
0.45
6.3
0.45
1.5
3V
3.7
6.3
3V
2.06
3.51
3V
UNIT
MHz
MHz
µs
13 ×
ADC10DIV ×
1/fADC10CLK
fADC10CLK from ACLK, MCLK, or SMCLK:
ADC10SSELx ≠ 0
(1)
100
ns
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
3.1.32 10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
EI
Integral linearity error
PARAMETER
TEST CONDITIONS
VCC
3V
±1
LSB
ED
Differential linearity error
3V
±1
LSB
EO
Offset error
±1
LSB
EG
Gain error
3V
±1.1
±2
LSB
ET
Total unadjusted error
3V
±2
±5
LSB
TYP
MAX
UNIT
Source impedance RS < 100 Ω
MIN
TYP
3V
3.1.33 10-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISENSOR
Temperature sensor supply
current (1)
TCSENSOR
TEST CONDITIONS
VCC
REFON = 0, INCHx = 0Ah,
TA = 25°C
ADC10ON = 1, INCHx = 0Ah
(2)
3V
60
3V
3.55
tSensor(sample)
Sample time required if channel
10 is selected (3)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
3V
IVMID
Current into divider at channel 11
ADC10ON = 1, INCHx = 0Bh
3V
VMID
VCC divider at channel 11
ADC10ON = 1, INCHx = 0Bh,
VMID ≉ 0.5 × VCC
3V
tVMID(sample)
Sample time required if channel
11 is selected (5)
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
3V
(1)
(2)
(3)
(4)
(5)
MIN
µA
mV/°C
µs
30
(4)
1.5
1220
µA
V
ns
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor (273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
No additional current is needed. The VMID is used during sampling.
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
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3.1.34 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.2 V/3.6 V
1
5
mA
IERASE
Supply current from VCC during erase
2.2 V/3.6 V
1
7
mA
tCPT
Cumulative program time (1)
2.2 V/3.6 V
10
ms
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
20
4
Program/erase endurance
10
ms
5
10
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
(2)
30
tFTG
tBlock,
0
Block program time for first byte or word
(2)
25
tFTG
tBlock,
1-63
Block program time for each additional byte or
word
(2)
18
tFTG
tBlock,
End
Block program end-sequence wait time
(2)
6
tFTG
tMass Erase
Mass erase time
(2)
10593
tFTG
tSeg Erase
Segment erase time
(2)
4819
tFTG
(1)
(2)
100
years
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
3.1.35 RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
TEST CONDITIONS
(1)
MIN
CPU halted
MAX
1.6
UNIT
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
3.1.36 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2.2 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V
0.025
15
µs
tSBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge (1))
2.2 V
1
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V
15
100
fTCK
TCK input frequency (2)
2.2 V
0
5
MHz
Internal pulldown resistance on TEST
2.2 V
25
90
kΩ
RInternal
(1)
(2)
TEST CONDITIONS
VCC
MIN
TYP
60
µs
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
3.1.37 JTAG Fuse (3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
(3)
48
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
100
V
mA
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
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over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tFB
3.2
TEST CONDITIONS
Time to blow fuse
MIN
MAX
UNIT
1
ms
MSP430 Core Operation
NOTE
For support and specific questions related to the MSP430 in the TPS65835 device, please
refer to TI's E2E PMU forum and post relevant questions to the forum at the following link:
TI E2E PMU Forum.
Please format your posting as follows:
• Title: TPS65835 "specific topic"
• Body: Question, with supporting code and oscilloscope screen captures if applicable.
3.2.1
Description
The MSP430 integrated into the TPS65835 is from the MSP430x2xx family of ultralow-power
microcontrollers. The architecture, combined with five low-power modes is optimized to achieve extended
battery life in portable applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and
constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO)
allows wake-up from low-power modes to active mode in less than 1␣s. The list of the peripherals and
modules included in this MSP430 are as follows:
• Up to 16 MHz CPU
• Timer0_A3 and Timer1_A3
– Up to Two 16-Bit Timer_A with Three
• 16 kB Flash Memory
Capture/Compare Registers
• 512 B RAM
•
Watchdog
WDT+
• Basic Clock Module
• USCI A0, Universal Serial Communication
– Internal Frequencies up to 16 MHz with
Interface
one Calibrated Frequency
– Enhanced UART Supporting Auto
– Internal
Very-Low-Power
baudrate Detection (LIN)
Low-Frequency (LF) Oscillator
– IrDA Encoder and Decoder
– 32 kHz Crystal Support
– Synchronous SPI
– External Digital Clock Source
– I2C
• 10-Bit ADC
• USCI B0, Universal Serial Communication
– 200-ksps
Analog-to-Digital
(A/D)
Interface
Converter with Internal Reference,
– Synchronous SPI
Sample-and-Hold, and Autoscan
– I2C
• Comparator A+ (Comp_A+)
• JTAG / Spy-By-Wire
– For Analog Signal Compare Function or
Slope
Analog-to-Digital
(A/D)
Conversion
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Figure 3-24. MSP430 Functional Block Diagram
3.2.2
Accessible MSP430 Pins
There are a number of internal pins connected between the MSP430 core and the power management
core as well as external pins on the MSP430. Internal pins are not available externally but can be
controlled by the MSP430 core in various ways. A table describing all available MSP430 pin functions
(Table 3-1) along with a block diagram detailing the MSP430 core and the pin connectivity (see
Figure 3-24) has been made available.
Table 3-1. Internally Connected Pins: MSP430 to Power Management Core
Power Management
Core Pin
MSP430 Core Pin
VLDO
AVCC / DVCC
Voltage supplied by LDO on power management core, connected to MSP430 power
management module
Enabled by SWITCH pin input
COMP
P1.0 / A0 / CA0
Scaled down voltage of the BAT pin. Connected to Comparator_A+ channel CA0 or
ADC channel A0 of the MSP430
To use "COMP" and Comp_A+ module function of the MSP430, the pin must be
configured properly
DO NOT CONFIGURE THIS PIN AS A GPIO AND PULL THIS PIN UP OR DOWN,
THIS WILL INCREASE THE OPERATING CURRENT OF THE DEVICE
(1)
50
Functionality
BST_EN
P3.2
Enable pin for the boost on the power management core, ACTIVE HIGH
CHG_EN
P3.1
Enable pin for the charger on the power management core, ACTIVE HIGH
SLEEP
P3.0
Can put entire device into SLEEP state dependent upon system events, e.g.,
extended loss of IR or RF synchronization (1)
HBL1
P2.0
Control pin 1 for left frame of active shutter glasses
HBL2
P2.3
Control pin 2 for left frame of active shutter glasses
HBR1
P2.4
Control pin 1 for right frame of active shutter glasses
HBR2
P2.5
Control pin 2 for right frame of active shutter glasses
Note that the SLEEP signal can not be used to wake the system if it is already in the SLEEP state since the LDO used to power the
MSP430 would be disabled in this state.
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Table 3-2. Externally Available MSP430 Pins
Pin Name
I/O
Functionality
I/O
General-purpose digital I/O pin
Timer0_A, capture: CCI0A input, compare: Out0 output
USCI_A0 receive data input in UART mode
USCI_A0 slave data out/master in SPI mode
ADC10 analog input A1
Comparator_A+, CA1 input
I/O
General-purpose digital I/O pin
Timer0_A, capture: CCI1A input, compare: Out1 output
USCI_A0 transmit data output in UART mode
USCI_A0 slave data in/master out in SPI mode
ADC10 analog input A2
Comparator_A+, CA2 input
I/O
General-purpose digital I/O pin
ADC10, conversion clock output
ADC10 analog input A3
ADC10 negative reference voltage
Comparator_A+, CA3 input
Comparator_A+, output
I/O
General-purpose digital I/O pin
SMCLK signal output
USCI_B0 slave transmit enable
USCI_A0 clock input/output
ADC10 analog input A4
ADC10 positive reference voltage
Comparator_A+, CA4 input
JTAG test clock, input terminal for device programming and test
I/O
General-purpose digital I/O pin
Timer0_A, compare: Out0 output
USCI_B0 clock input/output
USCI_A0 slave transmit enable
ADC10 analog input A5
Comparator_A+, CA5 input
JTAG test mode select, input terminal for device programming and test
I/O
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
ADC10 analog input A6
Comparator_A+, CA6 input
USCI_B0 slave out/master in SPI mode
USCI_B0 SCL I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
P1.7/
A7/
CA7/
CAOUT/
UCB0SIMO/
UCB0SDA/
TDO/TDI
I/O
General-purpose digital I/O pin
ADC10 analog input A7
Comparator_A+, CA7 input
Comparator_A+, output
USCI_B0 slave in/master out in SPI mode
USCI_B0 SDA I2C data in I2C mode
JTAG test data output terminal or test data input during programming and test (1)
P2.1/
TA1.1
I/O
General-purpose digital I/O pin
Timer1_A, capture: CCI1A input, compare: Out1 output
P2.2/
TA1.1
I/O
General-purpose digital I/O pin
Timer1_A, capture: CCI1B input, compare: Out1 output
P2.6/
XIN/
TA0.1
I/O
General-purpose digital I/O pin
XIN, Input terminal of crystal oscillator
TA0.1, Timer0_A, compare: Out1 output
P2.7/
XOUT
I/O
General-purpose digital I/O pin
Output terminal of crystal oscillator (2))
P3.3/
TA1.2
I/O
General-purpose digital I/O pin
Timer1_A, compare: Out2 output
P3.5/
TA0.1
I/O
General-purpose digital I/O pin
Timer0_A, compare: Out0 output
P1.1/
TA0.0/
UCA0RXD/
UCA0SOMI/
A1/
CA1
P1.2/
TA0.1/
UCA0TXD/
UCA0SIMO/
A2/
CA2
P1.3/
ADC10CLK/
A3
VREF-/VEREF-/
CA3/
CAOUT
P1.4/
SMCLK/
UCB0STE
UCA0CLK/
A4
VREF+/VEREF+/
CA4
TCK
P1.5/
TA0.0/
UCB0CLK/
UCA0STE/
A5/
CA5/
TMS
P1.6/
TA0.1/
A6/
CA6/
UCB0SOMI/
UCB0SCL/
TDI/TCLK
(1)
(2)
TDO or TDI is selected via JTAG instruction.
If P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this
pad after reset.
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Table 3-2. Externally Available MSP430 Pins (continued)
Pin Name
I/O
Functionality
nRST/
NMI/
SBWTDIO
I
Reset
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/
SBWTCK
I
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DVSS
3.2.3
N/A
MSP430 ground reference
MSP430 Port Functions and Programming Options
This section details the programming options that are available for each of the pins that are accessible on
the MSP430.
Table 3-3. Internal MSP430 Pin Functions and Programming Options
PIN NAME
(P_.x) (1)
MSP430 CONTROL BITS / SIGNALS
x
P1.0/
A0/
P1.x (I/O)
0
CA0
P2.0/
FUNCTION
0
0
0
X
1 (y = 0)
0
CA0
X
X
X
0
1 (y = 0)
I: 0; O: 1
0
0
—
—
1
1
0
—
—
I: 0; O: 1
0
0
—
—
1
1
0
—
—
I: 0; O: 1
0
0
—
—
1
1
0
—
—
I: 0; O: 1
0
0
—
—
P2.x (I/O), HBL1 internal
signal
Timer1_A3.TA0
P2.4/
P2.x (I/O), HBR1 internal
signal
TA1.2
Timer1_A3.TA2
P2.5/
P2.x (I/O), HBR2 internal
signal
TA1.2
Timer1_A3.TA2
P3.0/
P3.x (I/O), SLEEP signal
P3.1/
1
Timer0_A3.TA2
P3.x (I/O), CHG_EN signal,
ACTIVE HIGH
TA1.2
Timer1_A3.TA2
P3.2/
P3.x (I/O), BST_EN signal,
ACTIVE HIGH
TA1.2
(1)
(2)
52
2
0
0
TA1.0
0
CAPD.y
X
P2.3/
TA0.2
ADC10AE.x
INCH.x=1
X
P2.x (I/O), HBL2 internal
signal
5
P_SEL2.x
I: 0; O: 1
Timer1_A3.TA0
4
P_SEL.x
A0
TA1.0
3
P_DIR.x
(2)
Timer1_A3.TA2
1
1
0
—
—
I: 0; O: 1
0
0
—
—
1
1
0
—
—
I: 0; O: 1
0
0
—
—
1
1
0
—
—
I: 0; O: 1
0
0
—
—
1
1
0
—
—
Example: To program port P2.0, the appropriate control bits and MSP430 signals would need to be referenced as "P2DIR.0",
"P2SEL.0", and "P2SEL2.0".
X = don't care, — = not applicable
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Table 3-4. External MSP430 Port 1 Functions and Programming Options
PIN NAME
(P1.x) (1)
MSP430 CONTROL BITS / SIGNALS
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
ADC10AE.x
INCH.x=1
CAPD.y
I: 0; O: 1
0
0
0
0
1
1
0
0
0
TA0.CCI0A
0
1
0
0
0
UCA0RXD
from USCI
1
1
0
0
UCA0SOMI
from USCI
1
1
0
0
P1.1/
P1.x (I/O)
TA0.0/
TA0.0
UCA0RXD/
UCA0SOMI/
1
(2)
A1/
A1
X
X
X
1 (y = 1)
0
CA1/
CA1
X
X
X
0
1 (y = 1)
Pin Osc
Capacitive sensing
X
0
1
0
0
P1.2/
P1.x (I/O)
I: 0; O: 1
0
0
0
0
TA0.1/
TA0.1
1
1
0
0
0
TA0.CCI1A
0
1
0
0
0
UCA0TXD
from USCI
1
1
0
0
UCA0SIMO
0
UCA0TXD/
UCA0SIMO/
2
from USCI
1
1
0
A2/
A2
X
X
X
1 (y = 2)
0
CA2/
CA2
X
X
X
0
1 (y = 2)
Pin Osc
Capacitive sensing
P1.3/
P1.x (I/O)
ADC10CLK/
X
0
1
0
0
I: 0; O: 1
0
0
0
0
ADC10CLK
1
1
0
0
0
A3
X
X
X
1 (y = 3)
0
VREF-
X
X
X
1
0
VEREF-/
VEREF-
X
X
X
1
0
CA3
CA3
X
X
X
0
1 (y = 3)
Pin Osc
Capacitive sensing
P1.4/
P1.x (I/O)
SMCLK/
SMCLK
UCB0STE/
UCA0CLK/
VREF+/
A3/
VREF-/
VEREF+/
3
4
X
0
1
0
0
I: 0; O: 1
0
0
0
0
1
1
0
0
0
UCB0STE
from USCI
1
1
1 (y = 4)
0
UCA0CLK
from USCI
1
1
1 (y = 4)
0
VREF+
X
X
X
1
0
0
VEREF+
X
X
X
1
A4/
A4
X
X
X
1 (y = 4)
0
CA4/
CA4
X
X
X
0
1 (y = 4)
TCK/
TCK (JTAG Mode = 1)
X
X
X
0
0
Pin Osc
Capacitive sensing
P1.5/
P1.x (I/O)
TA0.0/
TA0.0
UCB0CLK/
UCA0STE/
X
0
1
0
0
I: 0; O: 1
0
0
0
0
1
1
0
0
0
UCB0CLK
from USCI
1
1
0
0
UCA0STE
from USCI
1
1
0
0
A5
X
X
X
1 (y = 5)
0
CA5/
CA5
X
X
X
0
1 (y = 5)
TMS/
TMS (JTAG Mode = 1)
X
X
X
0
0
Pin Osc
Capacitive sensing
X
0
1
0
0
A5/
(1)
(2)
5
Example: To program port P1.1, the appropriate control bits and MSP430 signals would need to be referenced as "P1DIR.1",
"P1SEL.1", and "P1SEL2.1".
X = don't care
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Table 3-4. External MSP430 Port 1 Functions and Programming Options (continued)
PIN NAME
(P1.x) (1)
MSP430 CONTROL BITS / SIGNALS
x
FUNCTION
(2)
P1DIR.x
P1SEL.x
P1SEL2.x
ADC10AE.x
INCH.x=1
CAPD.y
I: 0; O: 1
0
0
0
0
1
1
0
0
0
P1.6/
P1.x (I/O)
TA0.1/
TA0.1
UCB0SOMI/
UCB0SOMI
from USCI
1
1
0
0
UCB0SCL/
UCB0SCL
from USCI
1
1
0
0
A6
X
X
X
1 (y = 6)
0
CA6/
CA6
X
X
X
0
1 (y = 6)
TDI/TCLK/
TDI/TCLK (JTAG Mode = 1)
X
X
X
0
0
Pin Osc
Capacitive sensing
X
0
1
0
0
P1.7/
P1.x (I/O)
I: 0; O: 1
0
0
0
0
UCB0SIMO/
UCB0SIMO
from USCI
1
1
0
0
UCB0SDA/
UCB0SDA
from USCI
1
1
0
0
A7/
A7
X
X
X
1 (y = 7)
0
A6/
6
7
CA7/
CA7
X
X
X
0
1 (y = 7)
CAOUT/
CAOUT
1
1
0
0
0
TDO/TDI/
TDO/TDI (JTAG Mode = 1)
X
X
X
0
0
Pin Osc
Capacitive sensing
X
0
1
0
0
Table 3-5. External MSP430 Port 2 Functions and Programming Options
PIN NAME
(P2.x) (1)
x
FUNCTION
MSP430 CONTROL BITS / SIGNALS
(2)
P2DIR.x
P2SEL.x
P2SEL2.x
P2.1/
P2.x (I/O)
I: 0; O: 1
0
0
TA1.1/
Timer1_A3.CCI1A
0
1
0
Timer1_A3.TA1
1
1
0
1
Pin Osc
Capacitive sensing
P2.2/
P2.x (I/O)
TA1.1/
Timer1_A3.CCI1B
2
X
0
1
I: 0; O: 1
0
0
0
1
0
Timer1_A3.TA1
1
1
0
Pin Osc
Capacitive sensing
X
0
1
P2.6/
P2.x (I/O)
I: 0; O: 1
0
0
XIN/
XIN, LFXT1 Oscillator Input
0
1
0
6
TA0.1/
Timer0_A3.TA1
1
1
0
Pin Osc
Capacitive sensing
X
0
1
P2.7/
P2.x (I/O)
I: 0; O: 1
0
0
XOUT, LFXT1 Oscillator
Output
1
1
0
Capacitive sensing
X
0
1
XOUT/
7
Pin Osc
(1)
(2)
54
Example: To program port P2.1, the appropriate control bits and MSP430 signals would need to be referenced as "P2DIR.1",
"P2SEL.1", and "P2SEL2.1".
X = don't care
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Table 3-6. External MSP430 Port 3 Functions and Programming Options
PIN NAME
(P3.x) (1)
x
P3.3/
3
Pin Osc
P3.5/
5
Pin Osc
(2)
(2)
P3DIR.x
P3SEL.x
P3SEL2.x
0
0
Timer1_A3.TA2
1
1
0
Capacitive sensing
X
0
1
P3.x (I/O)
TA1.1/
MSP430 CONTROL BITS / SIGNALS
I: 0; O: 1
P3.x (I/O)
TA1.1/
(1)
FUNCTION
I: 0; O: 1
0
0
Timer0_A3.TA2
1
1
0
Capacitive sensing
X
0
1
Example: To program port P3.3, the appropriate control bits and MSP430 signals would need to be referenced as "P3DIR.3",
"P3SEL.3", and "P3SEL2.3".
X = don't care
3.2.4
Operating Modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An
interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
• Low-power mode 2 (LPM2)
– All clocks are active
– CPU is disabled
– MCLK and SMCLK are disabled
• Low-power mode 0 (LPM0)
– DCO's dc-generator remains enabled
– CPU is disabled
– ACLK remains active
– ACLK and SMCLK remain active, MCLK
is disabled
• Low-power mode 3 (LPM3)
• Low-power mode 1 (LPM1)
– CPU is disabled
– CPU is disabled
– MCLK and SMCLK are disabled
– ACLK and SMCLK remain active, MCLK
– DCO's dc-generator is disabled
is disabled
– ACLK remains active
– DCO's dc-generator is disabled if DCO
• Low-power mode 4 (LPM4)
not used in active mode
– CPU is disabled
– ACLK is disabled
– MCLK and SMCLK are disabled
– DCO's dc-generator is disabled
– Crystal oscillator is stopped
3.2.5
MSP430x2xx User's Guide
To view the user's guide for the MSP430 integrated into this device, see MSP430x2xx Family User's
Guide. The list of peripherals found in this MSP430 is listed in the section: Section 3.2.1.
MSP430 CORE
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4
APPLICATION INFORMATION
4.1
Applications Schematic
Figure 4-1. TPS65835 Applications Schematic
4.2
4.2.1
Boost Converter Application Information
Setting Boost Output Voltage
To set the boost converter output voltage of this device, two external resistors that form a feedback
network are required. The values recommended below (in Table 4-1) are given for a desired quiescent
current of 5 µA when the boost is enabled and switching. See Figure 4-2 for the detail of the applications
schematic that shows the boost feedback network and the resistor names used in the table below.
56
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Figure 4-2. Boost Feedback Network Schematic
Table 4-1. Recommended RFB1 and RFB2 Values (for IQ(FB) = 5 µA)
(1)
Targeted VBST_OUT
RFB1 (1)
RFB2 (1)
8V
1.3 MΩ
240 kΩ
10 V
1.8 MΩ
240 kΩ
12 V
2.2 MΩ
240 kΩ
14 V
2.4 MΩ
240 kΩ
16 V
3.0 MΩ
240 kΩ
Resistance values given in closest standard value (5% tolerance, E24 grouping).
These resistance values can also be calculated using the following information. To start, it is helpful to
target a quiescent current through the boost feedback network while the device is operating (IQ(FB)). When
the boost output voltage and this targeted quiescent current is known, the total feedback network
resistance can be found.
The value for RFB2 can be found by using the boost feedback pin voltage (VFB = 1.2 V, see "Electrical
Characteristics" in Section 2) and IQ(FB) in the following equation:
RFB1 + RFB2 = VBST_OUT / IQ(FB)
RFB2 = (1.2 V) / IQ(FB)
To find RFB1, simply subtract the RFB2 from RFB(TOT):
RFB1 = RFB(TOT) - RFB2
4.2.2
Boost Inductor Selection
The selection of the boost inductor and output capacitor is very important to the performance of the boost
converter. The boost has been designed for optimized operation when a 10 µH inductor is used. Smaller
inductors, down to 4.7 µH, may be used but there will be a slight loss in overall operating efficiency. A few
inductors that have been tested and found to give good performance can be found in the list below:
Recommended 10 µH inductors
• TDK VLS201612ET-100M (10 µH, IMAX = 0.53 A, RDC = 0.85 Ω)
• Taiyo Yuden CBC2016B100M (10 µH, IMAX = 0.41 A, RDC = 0.82 Ω)
APPLICATION INFORMATION
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4.2.3
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Boost Capacitor Selection
The recommended minimum value for the capacitor on the boost output, BST_OUT pin, is 4.7 µF. Values
that are larger can be used with the measurable impact being a slight reduction in the boost converter
output voltage ripple while values smaller than this will result in an increased boost output voltage ripple.
Note that the voltage rating of the capacitor should be sized for the maximum expected voltage at the
BST_OUT pin.
4.3
Bypassing Default Push-Button SWITCH Functionality
If the SWITCH pin functionality is not required to power on and off the device because of different system
requirements (SWITCH timing requirements of system will be controlled by the internal MSP430), then the
feature can be bypassed. The following diagram shows the connections required for this configuration.
Figure 4-3. Bypassing Default TPS65835 Push Button SWITCH Timing
In a system where a different push-button SWITCH off timing is required, the SLEEP pin is used to control
the power off of the device. After system power up, the MCU must force the SLEEP pin to a high state
(VSLEEP > VIH(PMIC)). Once the SWITCH push-button is pressed to shut the system down, a timer in the
MCU should be active and counting the desired tOFF time of the device. Once this tOFF time is detected,
the MCU can assert the SLEEP signal to a logic low level (VSLEEP < VIL(PMIC)). It is on the falling edge of
the SLEEP signal where the system will be powered off (see Figure 4-4)
58
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Figure 4-4. SWITCH Press and SLEEP Signal to Control System Power Off
APPLICATION INFORMATION
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4.4
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MSP430 Programming
In order to program the integrated MSP430 in the TPS65835 device, ensure that the programming
environment supports the TPS65835 device.
4.4.1
Code To Setup Power Functions
This section will detail a basic code to control the MSP430 in the TPS65835 and how to configure the
power functions and control the power die. Please reference Table 3-3 for the details on configuring the
MSP430 pins. Note that "//" is a comment and this code was written using Code Composer Studio in C.
// SETUP H-BRIDGE PINS
P2DIR |= (BIT5 + BIT4 + BIT3 + BIT0);
P2REN |= (BIT5 + BIT4 + BIT3 + BIT0);
// Set PxDIR to 1 for outputs
// Enable pullup/pulldown resistors on outputs
// SETUP SLEEP, CHG_EN, AND BST_EN
P3DIR |= (BIT2 + BIT1 + BIT0);
P3REN |= (BIT2 + BIT1 + BIT0);
// Set PxDIR to 1 for outputs
// Enable pullup/pulldown resistors on outputs
The previous code setup the power pins for outputs, now they must be controlled with MSP430 code.
Refer to the following code to perform initial setup and to control the power functions (SLEEP, CHG_EN,
and BST_EN):
P3OUT &= ~BIT0;
// P3OUT |= BIT0;
// Set SLEEP mode signal low; SLEEP Function is disabled
// Set SLEEP mode signal high (sleep control via MSP430)
// P3OUT &= ~BIT1;
P3OUT |= BIT1;
// Set CHG_EN signal low (disable charger)
// Set CHG_EN signal high (enable charger)
// P3OUT &= ~BIT2;
P3OUT |= BIT2;
// Set BST_EN low (disable boost)
// Set BST_EN high (enable boost)
The H-Bridge pins can be controlled in a similar manner (see Section 2.10.1). The following code is only
meant to cover each H-Bridge mode of operation and the appropriate code needed to put it in that state:
60
// BOTH SIDES IN OPEN STATE
P2OUT &= ~(BIT3 + BIT0);
P2OUT &= ~(BIT5 + BIT4);
// HBL2 = 0, HBL1 = 0
// HBR2 = 0, HBR1 = 0
// BOTH SIDES IN GROUNDED STATE
P2OUT |= BIT3 + BIT0;
P2OUT |= BIT5 + BIT4;
// HBL2 = 1, HBL1 = 1
// HBR2 = 1, HBR1 = 1
// LEFT SIDE IN CHARGE+ STATE
P2OUT &= ~BIT3; P2OUT |= BIT0;
// HBL2 = 0, HBL1 = 1
// LEFT SIDE IN CHARGE- STATE
P2OUT |= BIT3; P2OUT &= ~BIT0;
// HBL2 = 1, HBL1 = 0
// RIGHT SIDE IN CHARGE+ STATE
P2OUT &= ~BIT5; P2OUT |= BIT4;
// HBR2 = 0, HBR1 = 1
// RIGHT SIDE IN CHARGE- STATE
P2OUT |= BIT5; P2OUT &= ~BIT4;
// HBR2 = 1, HBR1 = 0
APPLICATION INFORMATION
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PACKAGE OPTION ADDENDUM
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1-Aug-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TPS65835RKPR
ACTIVE
VQFN
RKP
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS65835RKPT
ACTIVE
VQFN
RKP
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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