SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999 D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) 4-Ω Switch Connection Between Two Ports Isolation Under Power-Off Conditions Break-Before-Make Feature ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Plastic Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV), and 300-mil Shrink Small-Outline (DL) Packages NOTE: S0 1A1 1A2 2A1 2A2 3A1 3A2 GND 4A1 4A2 5A1 5A2 6A1 6A2 7A1 7A2 VCC 8A1 GND 8A2 9A1 9A2 10A1 10A2 11A1 11A2 12A1 12A2 For tape and reel order entry: The DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR. description The SN74CBTLV16212 provides 24 bits of high-speed bus switching or exchanging. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device operates as a 24-bit bus switch or a 12-bit bus exchanger, which provides data exchanging between the four signal ports via the data-select (S0, S1, S2) terminals. The SN74CBTLV16212 is specified by the break-before-make feature to have no through current when switching between B ports. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 S1 S2 1B1 1B2 2B1 2B2 3B1 GND 3B2 4B1 4B2 5B1 5B2 6B1 6B2 7B1 7B2 8B1 GND 8B2 9B1 9B2 10B1 10B2 11B1 11B2 12B1 12B2 The SN74CBTLV16212 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999 FUNCTION TABLE INPUTS 2 INPUTS/OUTPUTS S2 S1 S0 L L L L L H L FUNCTION A1 A2 L Z Z Disconnect H B1 Z A1 port = B1 port B2 Z A1 port = B2 port L H H Z B1 A2 port = B1 port H L L Z B2 A2 port = B2 port H L H Z Z Disconnect H H L B1 B2 A1 port = B1 port A2 port = B2 port H H H B2 B1 A1 port = B2 port A2 port = B1 port POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999 logic diagram (positive logic) 1A1 2 54 SW 1B1 SW SW 3 53 SW 1A2 12A1 27 1B2 30 SW 12B1 SW SW 28 29 SW 12A2 12B2 1 S0 S1 56 55 S2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999 simplified schematic, each FET switch A B (OE) absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DGG package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W DGV package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DL package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) VCC Supply voltage VIH High level control input voltage High-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low level control input voltage Low-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 2.3 3.6 1.7 UNIT V V 2 0.7 0.8 V TA Operating free-air temperature –40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK II VCC = 3 V, VCC = 3.6 V, II = –18 mA VI = VCC or GND Ioff ICC VCC = 0, VCC = 3.6 V, VI or VO= 0 to 3.6 V IO = 0, VCC = 3.6 V, VI = 3 V or 0 One input at 3 V, VO = 3 V or 0, OE = VCC ∆ICC‡ Control inputs Ci Control inputs Cio(OFF) MIN TYP† VI = VCC or GND Other inputs at VCC or GND MAX UNIT –1.2 V ±1 µA 10 µA 10 µA 300 µA 5 VCC = 2.3 2 3 V, V TYP at VCC = 2.5 V ron§ VCC = 3 V pF 8 pF VI = 0 II = 64 mA II = 24 mA 5 8 5 8 VI = 1.7 V, II = 15 mA 27 40 VI = 0 II = 64 mA II = 24 mA 5 7 5 7 Ω VI = 2.4 V, II = 15 mA 10 15 † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. § Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 and 2) VCC = 2.5 V ± 0.2 V FROM (INPUT) TO (OUTPUT) tpd¶ A or B B or A tpd ten S B or A 3 11.1 S A or B 3 10.9 PARAMETER MIN MAX VCC = 3.3 V ± 0.3 V MIN 0.15 UNIT MAX 0.25 ns 3 8.8 ns 3 8.6 ns tdis S A or B 1 8.7 2 8.8 ns ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND VCC Output Control LOAD CIRCUIT VCC/2 0V tPZL VCC VCC/2 Input VCC/2 0V tPLH VCC/2 tPLZ VCC VCC/2 tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VOL VCC/2 Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBTLV16212 LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Output Control (low-level enabling) LOAD CIRCUIT 3V 1.5 V 0V tPZL 3V Input 1.5 V 1.5 V 0V tPLH tPHL VOH Output 1.5 V 1.5 V VOL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V tPLZ 3V 1.5 V tPZH VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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