SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 D D D D D D D D D D D Four (’391), Eight (’389) or Sixteen (’387) Line Drivers Meet or Exceed the Requirements of ANSI EIA / TIA-644 Standard Designed for Signaling Rates† up to 630 Mbps With Very Low Radiation (EMI) Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-Ω Load Propagation Delay Times Less Than 2.9 ns Output Skew Is Less Than 150 ps Part-to-Part Skew Is Less Than 1.5 ns 35-mW Total Power Dissipation in Each Driver Operating at 200 MHz Driver Is High Impedance When Disabled or With VCC < 1.5 V SN65’ Version Bus-Pin ESD Protection Exceeds 15 kV Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch Low-Voltage TTL (LVTTL) Logic Inputs Are 5-V Tolerant ’LVDS389 DBT PACKAGE (TOP VIEW) GND VCC GND ENA A1A A2A A3A A4A GND VCC GND B1A B2A B3A B4A ENB GND VCC GND 1 38 2 37 3 36 4 5 6 7 35 34 33 32 8 31 9 30 10 29 11 28 12 27 13 26 14 15 16 17 18 19 25 24 23 22 21 20 A1Y A1Z A2Y A2Z A3Y A3Z A4Y A4Z NC NC NC B1Y B1Z B2Y B2Z B3Y B3Z B4Y B4Z ’LVDS391 D OR PW PACKAGE (TOP VIEW) description This family of four, eight, and sixteen differential line drivers implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the sixteen current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled. EN1,2 1A 2A VCC GND 3A 4A EN3,4 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z ’LVDS387 DGG PACKAGE (TOP VIEW) GND VCC VCC GND ENA A1A A2A A3A A4A ENB B1A B2A B3A B4A GND VCC VCC GND C1A C2A C3A C4A ENC D1A D2A D3A D4A END GND VCC VCC GND 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 A1Y A1Z A2Y A2Z A3Y A3Z A4Y A4Z B1Y B1Z B2Y B2Z B3Y B3Z B4Y B4Z C1Y C1Z C2Y C2Z C3Y C3Z C4Y C4Z D1Y D1Z D2Y D2Z D3Y D3Z D4Y D4Z The intended application of this device and signaling technique is for point-to-point and multidrop baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media can be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel receivers, the SN65LVDS386 or SN65LVDS388, over 300 million data transfers per second in single-edge clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second) Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 description (continued) When disabled, the driver outputs are high impedance. Each driver input (A) and enable (EN) have an internal pulldown that will drive the input to a low level when open circuited. The SN65LVDS387, SN65LVDS389, and SN65LVDS391 are characterized for operation from –40°C to 85°C. The SN75LVDS387, SN75LVDS389, and SN75LVDS391 are characterized for operation from 0°C to 70°C. logic diagram (positive logic) 1Y 1A 1Y 1A 1Z 1Z EN 2Y 2A 2Y 2A 2Z 2Z EN 3Y 3A 3Y 3A 3Z 3Z EN 4Y 4A 4Y 4A 4Z 4Z (1/4 of ’LVDS387 or 1/2 of ’LVDS389 shown) (’LVDS391 shown) AVAILABLE OPTIONS TEMPERATURE RANGE NO. OF DRIVERS BUS-PIN ESD –40°C to 85°C 16 15 kV SN75LVDS387DGG 0°C to 70°C 16 4 kV SN65LVDS389DBT –40°C to 85°C 8 15 kV PART NUMBER† SN65LVDS387DGG SN75LVDS389DBT 0°C to 70°C 8 4 kV SN65LVDS391D –40°C to 85°C 4 15 kV SN75LVDS391D 0°C to 70°C 4 4 kV –40°C to 85°C 4 15 kV SN65LVDS391PW SN75LVDS391PW 0°C to 70°C 4 4 kV † This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., SN65LVDS387DGGR). DRIVER FUNCTION TABLE INPUT ENABLE A EN Y H H H L L H L H X L Z Z OPEN H L H OUTPUTS Z H = high-level, L = low-level, X = irrelevant, Z = high-impedance (off) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 equivalent input and output schematic diagrams EQUIVALENT OF EACH A OR EN INPUT VCC TYPICAL OF ALL OUTPUTS VCC 50 Ω A or EN Input 10 kΩ 5Ω Y or Z Output 7V 300 kΩ 7V absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V Input voltage range: Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V Y or Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V Electrostatic discharge: SN65’ (Y, Z, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:15 kV, B: 500 V SN75’ (Y, Z, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:4 kV, B: 400 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating Table) Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 7.6 mW/°C 608 mW 494 mW PACKAGE TA ≤ 25°C D 950 mW DBT 1071 mW 8.5 mW/°C 688 mW 556 mW DGG 2094 mW 16.7 mW/°C 1342 mW 1089 mW PW 774 mW 6.2 mW/°C 496 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow. 402 mW recommended operating conditions MIN NOM MAX Supply voltage, VCC 3 3.3 3.6 High-level input voltage, VIH 2 Low-level input voltage, VIL Operating temperature O erating free-air tem erature, TA POST OFFICE BOX 655303 UNIT V V 0.8 V SN75’ 0 70 °C SN65’ – 40 85 °C • DALLAS, TEXAS 75265 3 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS |VOD| Differential output voltage magnitude ∆|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage RL = 100 Ω Ω, , See Figure 1 and Figure 2 See Figure 3 ’LVDS387 ’LVDS391 Supply current MAX 340 454 High-level input current 1.125 1.375 – 50 50 mV 50 150 mV 85 95 50 70 20 26 0.5 1.5 0.5 1.5 0.5 1.3 3 20 2 10 µA ± 24 mA ± 12 mA ±1 µA ±1 µA VIH = 2 V VIL = 0.8 V Low-level input current IOS Short circuit output current Short-circuit IOZ IO(OFF) High-impedance output current CIN Input capacitance CO Output capacitance VOY or VOZ = 0 V VOD = 0 V VO = 0 V or VCC VCC = 1.5 V, Power-off output current mV 50 Disabled, Di bl d VIN = 0 V or VCC ’LVDS391 UNIT – 50 ’LVDS387 ’LVDS389 IIH IIL TYP† 247 Enabled, RL = 100 Ω , VIN = 0.8 V or 2 V ’LVDS389 ICC MIN VO = 2.4 V VI = 0.4 sin (4E6πt) + 0.5 V VI = 0.4 sin (4E6πt) + 0.5 V, Disabled V mA µA 5 pF 9.4 pF † All typical values are at 25°C and with a 3.3-V supply. switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tPLH tPHL Propagation delay time, low-to-high-level output 0.9 1.7 2.9 ns Propagation delay time, high-to-low-level output 0.9 1.6 2.9 ns tr tf Differential output signal rise time 0.4 0.8 1 ns 0.4 0.8 1 ns tsk(p) Pulse skew (|tPHL – tPLH|) 150 500 ps tsk(o) tsk(pp) Output skew‡ 80 150 ps 1.5 ns tPZH tPZL Propagation delay time, high-impedance-to-high-level output 6.4 15 ns Propagation delay time, high-impedance-to-low-level output 5.9 15 ns tPHZ tPLZ Propagation delay time, high-level-to-high-impedance output 3.5 15 ns 4.5 15 ns RL = 100 Ω , CL = 10 pF, See Figure 4 Differential output signal fall time Part-to-part skew§ See Figure 5 Propagation delay time, low-level-to-high-impedance output † All typical values are at 25°C and with a 3.3-V supply. ‡ tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected together. § tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in this data sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 PARAMETER MEASUREMENT INFORMATION IOY Y II A VOD IOZ Z VOY GND VI VOC VOZ (VOY + VOZ)/2 Figure 1. Voltage and Current Definitions 3.75 kΩ Y 100 Ω 3.75 kΩ VOD Input Z ± 0 V ≤ VTEST ≤ 2.4 V Figure 2. VOD Test Circuit Y 49.9 Ω ± 1% (2 Places) 3V VI Input 0V Z 50 pF VOC(PP) VOC VOC(SS) VO NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP) is made on test equipment with a – 3 dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage 2V 1.4 V 0.8 V Input Input Z tPHL tPLH Y VOD 100 Ω ± 1 % 100% 80% VOD(H) Output CL = 10 pF (2 Places) 0V VOD(L) 20% 0% tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 PARAMETER MEASUREMENT INFORMATION 49.9 Ω ± 1% (2 Places) Y 0.8 V or 2 V Z + Input CL = 10 pF (2 Places) VOY 1.2 V – 2V 1.4 V 0.8 V Input VOY or VOZ VOZ tPZH tPHZ ≅ 1.4 V 1.3 V 1.2 V tPZL tPLZ 1.2 V VOZ 1.1 V or ≅1V VOY NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 5. Enable and Disable Time Circuit and Definitions 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 TYPICAL CHARACTERISTICS ’LVDS391 SUPPLY CURRENT (RMS) vs SWITCHING FREQUENCY 60 All outputs loaded and enabled. I CC – Supply Current – mA 50 VCC = 3.6 V 40 30 VCC = 3.3 V VCC = 3 V 20 10 0 0 50 100 150 200 250 300 f – Frequency – MHz Figure 6 ’LVDS389 SUPPLY CURRENT (RMS) vs SWITCHING FREQUENCY 240 110 220 100 I CC – Supply Current – mA I CC – Supply Current – mA ’LVDS387 SUPPLY CURRENT (RMS) vs SWITCHING FREQUENCY 200 VCC = 3.6 V 180 160 VCC = 3.3 V 140 VCC = 3 V 120 90 80 VCC = 3.6 V 70 VCC = 3.3 V 60 VCC = 3 V 50 100 All outputs loaded and enabled. All outputs loaded and enabled. 40 80 0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 f – Frequency – MHz f – Frequency – MHz Figure 8 Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 TYPICAL CHARACTERISTICS HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.1 t PHL – High-To-Low Propagation Delay Time – ns t PLH – Low-To-High Propagation Delay Time – ns LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.0 VCC = 3.6 V 1.9 1.8 1.7 VCC = 3 V 1.6 VCC = 3.3 V 1.5 1.4 1.3 –40 –20 0 20 40 60 80 100 2.2 2.0 VCC = 3 V 1.8 VCC = 3.3 V 1.6 1.4 VCC = 3.6 V 1.2 1.0 –40 –20 0 Figure 9 60 80 100 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 3.5 VCC = 3.3 V TA = 25°C VOH – High-Level Output Voltage – V VOL – Low-Level Output Voltage – V 40 Figure 10 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 3 2 1 0 0 2 4 6 IOL – Low-Level Output Current – mA VCC = 3.3 V TA = 25°C 3 2.5 2 1.5 1 0.5 0 –4 –3 –2 Figure 12 POST OFFICE BOX 655303 –1 IOH – High-Level Output Current – mA Figure 11 8 20 Ta – Free-Air Temperature – °C TA – Free-Air Temperature – °C • DALLAS, TEXAS 75265 0 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs TIME VOY VO – Output Voltage – V VOZ VOD t – Time – ns Figure 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 APPLICATION INFORMATION Host Host Controller Power Balanced Interconnect Power Target T DBn DBn Target Controller T DBn–1 DBn–1 T DBn–2 DBn–2 T DBn–3 DBn–3 T DB2 DB2 T DB1 DB1 T DB0 DB0 T TX Clock RX Clock SN65LVDS387 or 389 LVDS Receiver(s) Indicates twisting of the conductors. Indicates the line termination T circuit. Figure 14. Typical Application Schematic Signaling Rate vs Distance The ultimate data transfer rate over a given cable or trace length involves many variables. Starting with the capabilities of this LVDS driver to reproduce a data pulse as short as 1.6 ns (a 630 Mbps signaling rate) with less than 500 ps of pulse distortion, any degradation of this pulse by the transmission media will necessarily reduce the timing margin at the receiving end of the data link. The timing uncertainty induced by the transmission media is commonly referred to as jitter and comes from numerous sources. The characteristics of a particular transmission media can be quantified by using an eyepattern measurement such as shown in Figure 12, which shows about 340 ps of jitter or 20% of the data pulse width. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 APPLICATION INFORMATION height abs . jitter width unit interval Figure 15. Typical LVDS Eyepattern A generally accepted range of jitter at the receiver inputs that allows data recovery is 5% to 20% of the unit interval (data pulse width). Table 1 shows the signaling rate achieved on various cables and lengths at a 5% eyepattern jitter with a typical LVDS driver. Table 1. Signaling Rates for Various Cables for 5% Eyepattern Jitter LENGTH (m) CABLE† A (Mbps) B (Mbps) C (Mbps) D (Mbps) E (Mbps) F (Mbps) 1 240 200 240 270 180 230 5 205 210 230 250 215 230 10 180 150 195 200 145 180 † Cable A: CAT 3, specified up to 16 MHz, no shield, outside conductor diameter (∅) 0.52 mm Cable B: CAT 5, specified up to 100 MHz, no shield, ∅ 0.52 mm Cable C: CAT 5, specified up to 100 MHz, taped over all shield, ∅ 0.52 mm Cable D: CAT 5 (exceeding CAT 5), specified up to 300 MHz, braided over all shield plus taped individual shield for any pair, ∅ 0.64 mm (AWG22) Cable E: CAT 5 (exceeding CAT 5), specified up to 350 MHz, ∅ 0.64 mm (AWG22), no shield Cable F: CAT 5 (exceeding CAT 5), specified up to 350 MHz, “self-shielded”, ∅ 0.64 mm (AWG22) During synchronous parallel transfers, skew between the data and clock lines will also reduce the timing margin. This must be accounted for in the system timing budget. Fortunately, the low output skew of this LVDS driver will generally be a small portion of this budget. other LVDS products For other products and applications notes in the LVDS and LVDM product families visit our Web site at http://www.ti.com/sc/datatran. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. 12 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 MECHANICAL DATA DBT (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 30 PINS SHOWN 0,50 0,27 0,17 30 16 0,08 M 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 15 0°– 8° 0,75 0,50 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 28 30 38 44 50 A MAX 7,90 7,90 9,80 11,10 12,60 A MIN 7,70 7,70 9,60 10,90 12,40 DIM 4073252/D 09/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 MECHANICAL DATA DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. 14 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 PACKAGE OPTION ADDENDUM www.ti.com 14-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LVDS387DGG ACTIVE TSSOP DGG 64 25 None CU NIPDAU Level-1-220C-UNLIM SN65LVDS387DGGR ACTIVE TSSOP DGG 64 2000 None CU NIPDAU Level-1-220C-UNLIM Level-2-220C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) SN65LVDS389DBT ACTIVE SM8 DBT 38 50 None CU NIPDAU SN65LVDS389DBTG4 PREVIEW SM8 DBT 38 50 None Call TI SN65LVDS389DBTR ACTIVE SM8 DBT 38 2000 None CU NIPDAU SN65LVDS389DBTRG4 PREVIEW SM8 DBT 38 2000 None Call TI SN65LVDS391D ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM SN65LVDS391DR ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM Call TI Level-2-220C-1 YEAR Call TI SN65LVDS391PW ACTIVE TSSOP PW 16 90 None CU NIPDAU Level-1-220C-UNLIM SN65LVDS391PWR ACTIVE TSSOP PW 16 2000 None CU NIPDAU Level-1-220C-UNLIM SN75LVDS387DGG ACTIVE TSSOP DGG 64 25 None CU NIPDAU Level-1-220C-UNLIM SN75LVDS387DGGR ACTIVE TSSOP DGG 64 2000 None CU NIPDAU Level-1-220C-UNLIM SN75LVDS389DBT ACTIVE SM8 DBT 38 50 None CU NIPDAU Level-2-220C-1 YEAR SN75LVDS389DBTG4 ACTIVE SM8 DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN75LVDS389DBTR ACTIVE SM8 DBT 38 2000 None CU NIPDAU Level-2-220C-1 YEAR SN75LVDS389DBTRG4 ACTIVE SM8 DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN75LVDS391D ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM SN75LVDS391DR ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM SN75LVDS391PW ACTIVE TSSOP PW 16 90 None CU NIPDAU Level-1-220C-UNLIM SN75LVDS391PWR ACTIVE TSSOP PW 16 2000 None CU NIPDAU Level-1-220C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Mar-2005 reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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