Advanced Information SVG-2066 / SVG-2066Z 500MHz - 2200MHz 6-Bit Variable Gain Amp Product Description Sirenza Microdevices’ SVG-2066 is an IC based 6-bit digital 31.5dB range attenuator cascaded with a linear class A amplifier in a low-cost surface-mountable 6x6 QFN plastic package. This product is specifically designed as a high linearity variable gain amplifier for infrastructure equipment that can be used in either the RF transmit or RF receive path. It features both parallel or serial programmability, programmable power up states, latchable parallel control, 3V or 5V combatible logic and robust Class 1B ESD. The SVG2066 features configurable pin I/O’s for optimizing the part over application specific bands. Functional Block Diagram Serial or Parallel Select S-P 2 Bit Power Up State Programming U1 U2 VDD Serial Interface DATA CLK VCC LE RFIN RFOUT Pb RoHS Compliant & Green Package 6mm x 6mm QFN Package Product Features • • • • • • • • • • P1dB = 25dBm @ 2140MHz OIP3 Typical 41dBm @ 2GHz Gain = 15dB at 850MHz 31.5dB Attenuation range in 0.5dB steps Serial or Parallel Controlled Optional Latched Parallel Control Programmable Power Up States Immune to Latch-Up Positive Supply Voltage 3V or 5V Logic Compatible Applications • • • P0.5 P1 P2 P4 P8 P16 6-Bit Parallel Interface CDMA, W-CDMA Tx and Rx GSM, EDGE Tx and Rx High Performance VGA applications Key Specifications Symbol fO P1dB S21 IP3 NF Parameters: Test Conditions, App circuit page 4 Z0 = 50Ω, VCC = 5.0V, Vdd=3V, I = 115mA, TL= 30ºC Unit Min. Frequency of Operation MHz 500 Output Power at 1dB Compression – 850MHz Output Power at 1dB Compression – 2.14GHz Small Signal Gain – 850MHz @ 0dB state Small Signal Gain – 2.14GHz @ 0dB state Third Order Intercept (Pout = 9dBm per tone) - 850MHz Third Order Intercept (Pout = 9dBm per tone) - 2.14GHz Noise Figure at 850 MHz @ 0 dB state Noise Figure at 2140 MHz @ 0 dB state IRL Input Return Loss 850-2200 MHz ( 0dB attenuation ) ORL Output Return Loss 850-2200MHz ( 0dB attenuation ) Ts Icq Rth, j-l 10%/90% Settling time dBm dB dBm 23.5 Current (Vcc = 5V,Vdd=3v) mA ºC/W 2200 25 15 9.5 11 13.5 39 39 41 5.9 6.9 9 9 nS Thermal Resistance (junction - lead) Max. 24 dB dB Typ. 7.9 12 12 320 100 115 130 70 The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Specification continued Symbol ERR Parameters: Test Conditions Z0 = 50Ω, VCC = 5.0V,Vdd=3V Iq = 115mA Unit Atten setting accuracy any state (500MHz-2200MHz) Min. Typ. Max. +/- 0.2 +/- (0.2+3% Atten setting) 30.3 31.5 32.7 2.7 3.0 3.3 dB DYNR Attenuation dynamic range FCLK Serial Data Clock Frequency VDD Drain voltage of Attenuator V IDD Drain Supply Current uA LH Digital Logic High V 0.7xVDD VDD LL Digital Logic Low V 0 0.3xVDD Digital Logic Leakage uA ILEAK dB MHz 20 40 Absolute Maximum Ratings Parameters MIn VCC Bias Current (IC) Max Unit 220 mA VCC Bias Voltage 8 V Power Dissipation 1.5 W V Drain Voltage (VDD) -0.3 4.0 Voltage on any Digital Input -0.3 VDD+0.3 V Operating Lead Temperature (TL) -40 +85 ºC 21 dBm -40 +150 ºC Operating Junction Temperature (TJ) +150 ºC ESD Human Body Model 500 V Max RF Input Power Storage Temperature Range 100 1 Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation the device voltage and current must not exceed the maximum operating values specified in the table on page one. Bias conditions should also satisfy the following expression: IDVD < (TJ - TL) / RTH’ j-l Digital Interfacing: Serial or Parallel Mode Selection The SVG-2066 can be controlled with either a serial or parallel interface. The S-P bit selects the mode: S-P=low for parallel mode and S-P=high for serial mode. Parallel Mode Operation For latched parallel interfacing the LE line should be held low while changing attenuation state control logic P0.5 thru P16. To load data pulse LE from low to high and to low again. See Figure 1 and Table 1 on the next page for the parallel mode timing diagram and specifications. For direct parallel mode operation the LE line should be held high and the attenuation state is directly loaded when the parallel line logic changes. The truth table for parallel operation is shown in Table 2. Serial Mode Operation Three CMOS compatible signals control the attenuator in this mode: DATA, CLK and LE. When LE is high the latch is enabled and data in the serial shift register gets loaded. When the LE is low the data in the shift register is latched. Refer to Figure 2 for the timing diagram and Table 3 for the timing specifications. Power up State Programming At power up in serial mode the six control bits are set to the values available on the six parallel inputs P0.5 thru P16 (see Table 2). For parallel mode the power up state is set with the two bit word defined by U1 and U2. See the truth table in Table 4. 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 2 http://www.sirenza.com EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Figure 1: Parallel Mode Timing Diagram (S-P=0) Table 2: Parallel Mode Truth table (S-P=0) Attenuation State LE Data P0.5 thru P16 TD5 P0.5 P1 P2 P4 P8 P16 Reference 0 0 0 0 0 0 0.5 dB 1 0 0 0 0 0 1 dB 0 1 0 0 0 0 2 dB 0 0 1 0 0 0 4 dB 0 0 0 1 0 0 8 dB 0 0 0 0 1 0 16 dB 0 0 0 0 0 1 31.5 dB 1 1 1 1 1 1 TD7 TD6 Table 1: Parallel Mode Timing Specifications (S-P=0) Symbol Unit Min LE minimum pulse width Parameter TD6 nS 10 Delay set up time before rising LE edge TD5 nS 10 Data hold after falling edge of LE TD7 nS 10 Max Table 3: Serial Mode Timing Specifications Figure 2: Serial Mode Timing Diagram (S-P=1) LE CLK MSB DATA 16dB LSB 8dB 4dB 2dB 1dB 0.5dB TD1 Symbol Unit Min TD1 nS 10 Serial data hold after clock falling edge TD2 nS 10 LE delay after last clock falling edge TD3 nS 10 LE minimum pulse width TD4 nS 30 Serial data clock freq FCLK MHz Serial clock high time TCLKH nS 30 Serial clock low time TCLKL nS 30 Max 20 TD3 TD2 TD4 Table 4: Power Up Truth Table for Parallel Mode (S-P=0) Attenuation State Parameter Serial data delay before clock rising edge LE U1 U2 Reference 0 0 0 8 dB 0 1 0 16 dB 0 0 1 31 dB 0 1 1 Defined by P0.5 Thru P16 1 Not Applicable Not Applicable 303 South Technology Court Broomfield, CO 80021 Note: Serial mode power up (S-P=1) state is defined by the parallel input logic shown in Table 2. Phone: (800) SMI-MMIC 3 http://www.sirenza.com EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Pin Out Description Pin # Label 2,3,20,26,28 N/C These are unused pins and not wired inside the package. May be grounded or connected to adjacent pins. Description 1,7,8,10,16, 21,23,24,25,30 GND Pins are internally grounded 4 RFIN RF input pin. Connects to 100pF cap inside package. 5 J1 6 ATIN 9 P8 Parallel interface attenuation control bit 8 dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. 11 P4 Parallel interface attenuation control bit 4 dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. 12 P2 Parallel interface attenuation control bit 2 dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. 13 P1 Parallel interface attenuation control bit 1 dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. 14 P0.5 Parallel interface attenuation control bit 0.5dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. 15 P16 Parallel interface attenuation control bit 16dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. 17 ATOUT 18 J2 Jumper this pin to the attenuator output pin (ATOUT). Connects to 100pF cap inside package. 19 J3 Connect this pin to the amplifier input pin (AMPIN) with the appropriate AMPIN impedance matching 22 AMPIN Amplifier input pin. Internally connected to base of amplifier (~1.3V) 27 RFOUT Amplifier RF output pin. Internally connected to 5V. Not matched to 50 ohm. Use appropriate matching circuit. 29 VCC Power Supply pin to Amplifier. Apply 5.0V to this pin. 31 Data Serial interface data input. 32 CLK Serial interface clock input. 33 LE 34, 35 U1 / U2 Parallel mode power-up state logic bits. 0/0 = 0dB, 1/0 = 8dB, 0/1=16dB, 1/1=31dB 36 J5 Jumper this pin to GND on the PC board. Connects to 1000pF cap inside package. 37 J4 Jumper this pin on PC board to VDD pin 38. Connects to 1000pF bypass cap inside package. 38 VDD Power supply pin to Digital Attenuator. Apply 2.7-3.3V to this pin. May be set from another voltage with a voltage divider (pulls 40uA typ, 100uA max) 39 S-P Serial or parallel mode select. Logic low for parallel mode. Logic high for serial mode. 40 VSS Negative supply voltage or GND EPAD GND Exposed area on the bottom side of the package . GND with vias as shown in recommended landing pattern. Jumper this pin on the PC board to the attenuator input (ATIN) pin #6. Connects to 100pF cap inside package. Attenuator input pin Attenuator output pin. Latch enable input. Parallel mode can also be latch enabled with this pin. VSS 40 S-P 39 VDD 38 J4 37 J5 36 U2 35 U1 34 LE 33 CLK DATA 32 31 GND 1 30 NC 2 29 VCC NC 3 28 NC RFIN 4 27 RFOUT J1 5 26 ATIN 6 25 GND NC GND GND 7 24 GND GND 8 23 GND P8 GND 9 22 10 21 11 P4 12 P2 303 South Technology Court Broomfield, CO 80021 13 P1 14 P0.5 15 P16 16 GND 17 ATOUT Phone: (800) SMI-MMIC 4 18 J2 19 J3 AMPIN GND 20 NC http://www.sirenza.com EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Measured 850MHz Evaluation Board Data (Vcc = 5.0V, Vdd=3.0V, Iq =115mA) S11 vs. Frequency, T=+25c S21 vs. Frequency, T=+25c 0.0 20.0 Atten. level(dB) -5.0 0 -10.0 1 Atten. level(dB) 15.0 10.0 -20.0 4 1 S21 (dB) 2 S11 (dB) -15.0 0 5.0 16 -30.0 31 -35.0 -40.0 700 2 -5.0 4 -10.0 8 -25.0 0.0 8 -15.0 16 -20.0 31 -25.0 -30.0 750 800 850 900 950 700 1000 750 800 Atten. level(dB) 950 1000 -10.0 0 -15.0 1 -20.0 2 -25.0 4 -30.0 8 -35.0 16 -40.0 31 -45.0 0.4 Error Relative to Insertion Loss and Desired Atten. Setting (dB) 0.0 -5.0 Atten. level(dB) 0.2 0.0 1 -0.2 2 -0.4 -0.6 4 -0.8 8 -1.0 -1.2 16 -1.4 31 -1.6 -1.8 -2.0 -50.0 750 800 850 900 950 700 1000 750 800 850 900 950 1000 Freq. (MHz) Freq. (MHz) T= +25c, All 1dB Steps,Attenuation Error vs. Frequency 0.4 Error Relative to Insertion Loss and Desired Atten. Setting (dB) S22 (dB) 900 850MHz +25c Attenuation Error vs. Frequency S22 vs. Frequency, T=+25c 700 850 Freq. (MHz) Freq. (MHz) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 500 600 700 800 900 1000 Freq. (MHz) 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 5 http://www.sirenza.com EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Measured 850MHz Evaluation Board Data (Vcc = 5.0V, Vdd=3.0V, Iq =115mA) S11 vs. Frequency, T=-40c S21 vs. Frequency, T=-40c 20.0 0.0 Atten. level(dB) -5.0 S21 (dB) S11 (dB) 2 -20.0 0 5.0 1 -15.0 Atten. level(dB) 10.0 0 -10.0 15.0 4 -25.0 8 1 0.0 -5.0 2 -10.0 4 -15.0 8 16 -20.0 16 31 -25.0 31 -30.0 -35.0 -40.0 -30.0 700 750 800 850 900 950 1000 700 750 800 Freq. (MHz) S22 vs. Frequency, T=-40c 900 950 1000 T=-40c Attenuation Error vs. Frequency Atten. level(dB) -10.0 0 -15.0 1 S22 (dB) -20.0 2 -25.0 4 -30.0 -35.0 8 -40.0 16 -45.0 31 -50.0 Error Relative to Insertion Loss and Desired Atten. Setting (dB) 0.4 0.0 -5.0 0.2 Atten. level(dB) 0.0 -0.2 1 -0.4 2 -0.6 -0.8 4 -1.0 8 -1.2 16 -1.4 -1.6 31 -1.8 -2.0 700 750 800 850 900 950 1000 700 Freq. (MHz) 850MHz P1dB vs Atten 750 800 850 Freq. (MHz) 900 950 1000 Noise Figure vs Temp, F=850MHz, Atten.=0dB 28 27 8.0 26 7.0 25 6.0 24 5.0 NF(dB) P1dB 850 Freq. (MHz) 23 22 21 4.0 3.0 2.0 20 1.0 0 2 4 6 8 10 12 Atten. (dB) +25c -40c 14 16 18 0.0 -40 +85c 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 6 25 Temperture(C) 85 http://www.sirenza.com EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Measured 850MHz Evaluation Board Data (Vcc = 5.0V, Vdd=3.0V, Iq =115mA) S11 vs. Frequency, T=+85c S21 vs. Frequency, T=+85c 0.0 20.0 Atten. level(dB) 0 10.0 -10.0 0 1 5.0 2 0.0 -20.0 4 -25.0 8 -30.0 16 -35.0 31 -40.0 S21 (dB) S11 (dB) -15.0 Atten. level(dB) 15.0 -5.0 1 2 -5.0 -10.0 4 -15.0 8 -20.0 16 -25.0 31 -30.0 700 750 800 850 900 950 1000 700 750 800 Freq. (MHz) S22 vs. Frequency, T=+85c 900 950 1000 T=+85c Attenuation Error vs. Frequency Atten. level(dB) -5.0 0 -10.0 1 -20.0 2 -25.0 4 S22 (dB) -15.0 -30.0 8 -35.0 16 -40.0 31 -45.0 Error Relative to Insertion Loss and Desired Atten. Setting (dB) 0.4 0.0 Atten. level(dB) 0.2 0.0 -0.2 1 -0.4 2 -0.6 -0.8 4 -1.0 8 -1.2 16 -1.4 -1.6 31 -1.8 -2.0 -50.0 700 750 800 850 900 950 700 1000 750 800 Freq. (MHz) 50 50 IIP3(dBm) 60 40 30 10 10 15 20 25 30 0 Atten(dB) +25c -40c 1000 30 20 10 950 40 20 5 900 Input IP3 vs atten level 60 0 850 Freq. (MHz) Output IP3 vs atten level OIP3(dBm) 850 Freq. (MHz) +85c 303 South Technology Court Broomfield, CO 80021 5 10 15 +25c Phone: (800) SMI-MMIC 7 20 25 30 Atten(dB) -40c +85c http://www.sirenza.com EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Measured 2.14GHz Evaluation Board Data (Vcc = 5.0V, Vdd=3.0V, Iq =115mA) S11 vs. Frequency, T= +25c S21 vs. Frequency, T= +25c 0.0 15.0 Atten. level (dB) Atten. level (dB) -5.0 0 10.0 1 5.0 2 0.0 0 -10.0 S11 (dB) S21 (dB) 1 -15.0 -20.0 4 -25.0 8 -30.0 16 -40.0 1.70 1.80 1.90 2.00 2.10 2.20 2.30 4 -10.0 8 -15.0 31 -35.0 2 -5.0 16 -20.0 31 -25.0 1.70 2.40 1.80 1.90 2.00 S22 vs. Frequency, T= +25c 2.20 2.30 2.40 T=+25c Attenuation Error vs. Frequency 0.0 0.4 Error Relative to Insertion Loss and Desired Atten. Setting (dB) 0 -10.0 1 2 -15.0 4 8 -20.0 16 -25.0 Atten. Level(dB) 0.2 Atten. Level(dB) -5.0 31 1 0.0 -0.2 2 -0.4 4 -0.6 -0.8 8 -1.0 16 -1.2 -1.4 31 -1.6 -30.0 1.70 -1.8 1.80 1.90 2.00 2.10 2.20 2.30 2.40 1.70 1.80 1.90 2.00 Freq. (GHz) 2.10 2.20 2.30 2.40 Freq. (GHz) All 1dB Steps, T= +25c Attenuation Error vs. Frequency 0.4 0.2 Error Relative to Insertion Loss and Desired Atten. Setting (dB) S22 (dB) 2.10 Freq. (GHz) Freq. (GHz) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 Freq. (GHz) 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 8 http://www.sirenza.com EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Measured 2.14GHz Evaluation Board Data (Vcc = 5.0V, Vdd=3.0V, Iq =115mA) S11 vs. Frequency, T= -40c S21 vs. Frequency, T= -40c 0.0 15.0 Atten. level (dB) -5.0 Atten. level (dB) 0 10.0 1 5.0 2 0.0 0 -10.0 S11 (dB) -20.0 4 -25.0 8 -30.0 16 S21 (dB) 1 -15.0 2 -5.0 4 -10.0 8 -15.0 16 31 -35.0 -20.0 -40.0 1.70 1.80 1.90 2.00 2.10 2.20 2.30 31 -25.0 2.40 1.70 1.80 1.90 Freq. (GHz) 2.00 2.10 2.20 2.30 2.40 Freq. (GHz) T=-40c Attenuation Error vs. Frequency S22 vs. Frequency, T= -40c T= -40c Attenuation Error vs. Frequency 0.6 0.0 Atten. Level(dB 0.4 Atten. Level(dB) -5.0 0 S22 (dB) -10.0 1 2 -15.0 4 8 -20.0 16 -25.0 31 Error Relative to Insertion Loss and Desired Error Relative to Insertion Loss and Desired Atten. Setting (dB) Atten. Setting (dB) 0.6 Atten. ) level(dB) 0.2 0.4 1 0.2 1 0.0 0.0 -0.2 2 2 -0.4 -0.4 4 4 -0.2 -0.6 -0.6 8 -0.8 -0.8 -1.0 -1.0 16 -1.2 31 -1.2 -1.4 31 -1.6 -1.4 -1.8 -1.6 1.7 1.70 -30.0 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 1.8 1.80 Freq. (GHz) 2.0 2.00 2.1 2.10 2.2 2.20 2.32.30 2.42.40 Noise Figure vs Temp, F=2.14GHz, Atten.=0dB P1dB vs Atten 9.0 26 25 24 23 22 21 20 7.0 8.0 6.0 NF(dB) P1dB 1.9 1.90 Freq. Freq.(GHz) (GHz) 28 27 5.0 4.0 3.0 2.0 1.0 0 2 4 6 8 10 12 14 16 18 0.0 Attenuation (dB) +25c -40c -40 +85c 303 South Technology Court Broomfield, CO 80021 8 16 Phone: (800) SMI-MMIC 9 25 Temperture(C) 85 http://www.sirenza.com EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Measured 2.14GHz Evaluation Board Data (Vcc = 5.0V, Vdd=3.0V, Iq =115mA) S11 vs. Frequency, T= +85c S21 vs. Frequency, T= +85c 0.0 Atten. level (dB) 15.0 Atten. level (dB) -5.0 0 10.0 1 -15.0 2 -20.0 4 -25.0 8 -30.0 16 0 5.0 1 0.0 S21 (dB) S11 (dB) -10.0 2 -5.0 4 -10.0 8 -15.0 16 31 -35.0 -20.0 -40.0 1.70 1.80 1.90 2.00 2.10 2.20 2.30 31 -25.0 1.70 2.40 1.80 1.90 S22 vs. Frequency, T= +85c 2.10 2.20 2.30 2.40 T=+85c Attenuation Error vs. Frequency 0.4 0.0 0 1 2 -15.0 4 8 -20.0 16 -25.0 31 Error Relative to Insertion Loss and Desired Atten. Setting (dB) -5.0 -10.0 Atten. Level(dB) 0.2 Atten. Level(dB) S22 (dB) 2.00 Freq. (GHz) Freq. (GHz) 1 0.0 -0.2 2 -0.4 4 -0.6 -0.8 8 -1.0 16 -1.2 -1.4 31 -1.6 -30.0 -1.8 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 1.70 1.80 1.90 Freq. (GHz) 2.00 2.10 2.20 2.30 2.40 Freq. (GHz) Input IP3 vs Atten. Output IP3 vs Atten. 55 45 50 IIP3(dBm) OIP3(dBm) 40 35 30 25 45 40 35 30 25 20 20 0 5 10 15 20 25 30 0 Attenuation (dB) +25c -40c 10 Phone: (800) SMI-MMIC 10 15 20 25 Attenuation (dB) +25c +85c 303 South Technology Court Broomfield, CO 80021 5 -40c +85c http://www.sirenza.com EDS-104432 Rev 3 30 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA 850MHz, 2140MHz Evaluation Board Schematic For Vcc = 5.0V, Vdd = 3.0V, Iq = 115mA S-P VDD CLK R7 DATA LE VCC+ R6 VSS C1 1uF L1 NC NC NC C2 RF IN SVG-2066 NC Zo=50 Zo=50 NC EL1 EL2 LOT ID C4 C3 RF OUT 850MHz NC Zo=50 EL3 NC 2140MHz EL1 8.8° EL2 2.2° 22.1° 5.5° EL3 11.0° N/A C5 R1 R2 P8 P4 R5 R3 P2 R4 P0.5 P16 P1 850MHz, 2140MHz Evaluation Board Layout For Vcc = 5.0V, Vdd = 3.0V, Iq = 115mA Board material GETEK, 10mil thick, Dk=3.9, 2 oz. copper 1uF tantalum cap R7 C1 R6 L1 C3 C2 C4 R1 R2 R4 R3 R5 C5 Note: Parallel interface controls should be held high or low for proper serial mode operation. Logic on these pins determine power up state for serial mode. 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 11 http://www.sirenza.com EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Part Number Ordering Information Part Number Reel Size Devices/Reel SVG-2066 or SVG-2066Z 7” 1000 Part Symbolization The part will be symbolized with an “SVG-2066” marking designator on the top surface of the package. Package Outline Drawing (dimensions in mm): Recommended Land Pattern (dimensions in mm[in]): 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 12 http://www.sirenza.com EDS-104432 Rev 3