UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 FEATURES RAS access time: 35, 40, 50, 60 2 CAS Byte/Word Read/Write operation CAS - before – RAS refresh capability RAS only and Hidden refresh capability Early write or output enable controlled write Extended Data Out operation Package : 40 pin 400mil SOJ 40 / 44 pin 400mil TSOP-Ⅱ Single +5V+10% power supply TTL compatible inputs and outputs 512 refresh cycles /8ms Speed tRAC tCAA tPC tCAC tRC -35 35ns 18ns 14ns 11ns 70ns -40 40ns 20ns 15ns 12ns 75ns -50 50ns 24ns 19ns 14ns 90ns -60 60ns 30ns 27ns 15ns 110ns GENERAL DESCRIPTION The UT51C164 is high speed 5V EDO DRAMs organized as 256K bit X 16 I/O and fabricated with the CMOS process. The UT51C164 offers a combination of unique features including : EDO Page Mode operation for higher bandwidth with Page Mode cycle time as short as 14ns. All inputs are TTL compatible. Input and output capacitance is significantly lowered to increase performance and minimize loading. These features make the UT51C164 suited for wide variety of high performance computer systems and peripheral applications UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 PIN DESCRIPTION SYMBOL A0-A8 RAS DESCRIPTION Address Inputs Row Address Strobe UCAS Column Address Strobe / Upper Byte Control LCAS Column Address Strobe / Lower Byte Control WE OE DQ0-DQ15 VDD Vss NC Write enable Output enable Data Inputs, Data Outputs +5V Supply 0V Supply No Connect PIN CONFIGURATIONS UT51C164 40- pin SOJ V DD DQ0 DQ1 1 40 2 39 3 38 DQ2 4 37 DQ3 5 36 V DD DQ4 6 35 7 34 DQ5 8 33 DQ6 9 32 DQ7 10 31 NC 11 30 NC 12 29 WE 13 28 RAS 14 27 NC 15 26 A0 16 25 A1 17 24 A2 18 23 A3 19 22 V DD 20 21 UT51C164 40- pin TSOP - Ⅱ Vss DQ15 DQ14 DQ13 DQ12 Vss DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss VDD DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 NC NC WE RAS NC A0 A1 A2 A3 VDD 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 Vss DQ15 DQ14 DQ13 DQ12 Vss DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 FUNCTION BLOCK DIAGRAM V DD VBB GENERATOR 9 Refresh Counter Control Circuit V SS RAS LCAS UCAS WE OE A1 A0 .. . . A7 A8 Address Buffers & Predecoders V BB X0 – X8 Y0 – Row Control Circuit Y8 Row Decoder Cell Array 512 x 512 x 16 Sense Amp X512 CS Column Decoder x16 FSA & Write in Circuit x16 Input & Output Buffer x16 DQ[0,15] UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 ABSOLUTE MAXIMUM RATINGS PARAMETER Voltage on any pin relative to Vss Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature SYMBOL VT VDD IOUT PD TA TSTG VALUE -1.0 to +7 -1.0 to +7 50 1.0 0 to + 70 -55 to +125 UNIT V V mA W ºC ºC Notes: Permanent device damage may occur if absolute maximum ratings are exceed. RECOMMENDED DC OPERATING CONDITIONS (TA = 0℃ to 70ºC) PARAMETER Supply voltage Input high voltage Input low voltage Notes: 5.0V SYMBOL MIN 4.5 0 2.4 -0.3 VDD Vss VIH VIL MAX 5.5 0 VDD +1V 0.8 UNIT NOTES V V V V 1 1 1 1. All Voltage referred to Vss CAPACITANCE (TA = 25ºC, VDD= 5V±0.5V，f=1MHz) PARAMETER Input capacitance (A0-A8) Input Capacitance ( RAS , UCAS , LCAS , WE , OE ) Output capacitance(DQ0-DQ15) SYMBOL CIN1 CIN2 TYP 3 4 MAX 4 5 UNIT pF pF CDQ 5 7 pF UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 DC CHARACTERISTICS (TA = 0℃ to 70ºC, VDD = 5.0 V ± 0.5 V, Vss = 0 V) SYMBOL PARAMETER IDD1 Operating Current, VDD Supply IDD2 Standby Current (TTL Input) IDD3 RAS Only Current IDD4 EDO Page Current IDD5 CBR Refresh Current IDD6 VDD ILI ILO VIL VIH VOL VOH UT51C164 Min Max 190 180 170 160 SPEED (tRAC) -35 -40 -50 -60 UNIT mA tRC = tRC (min.) mA RAS = UCAS = LCAS =VIH mA tRC = tRC (min.) mA tPC = tPC (min.) mA tRC = tRC (min.) RAS ≧ VDD-0.2V CAS ≧ VDD-0.2V All other inputs≧ VSS - - 3 -35 -40 -50 -60 -35 -40 -50 -60 -35 -40 -50 -60 - 190 180 170 160 220 200 190 180 190 180 170 160 Standby Current (CMOS Input) - - 2 mA Power Supply Input Leakage Current - 4.5 -10 5.5 10 V uA - -10 10 uA - -1 2.4 2.4 0.8 V V V V Refresh Mode Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VDD +1 0.4 - TEST CONDITION VSS≦ VIN ≦VDD VSS≦ VOUT ≦VDD RAS = CAS = VIH IOI = 2mA IOH = 2mA Notes: IDD1, IDD3, IDD4, IDD5 are dependent on output loading and cycle rates. Specified values are obtained with the output open. IDD is specified as an average current. In IDD1, IDD3, and IDD5 address can be changed maximum once while RAS =VIL. In IDD4, address can be changed maximum once within one EDO page cycle time, tPC. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 AC CHARACTERISTICS (TA = 0℃ to 70°C) Test condition: VDD = 5.0V±0.5V, VIH / VIL=3V / 0V, VOH / VOL=2.0 / 0.8) SYMBOL PARAMETER 35 40 50 60 UNIT NOTE Min. Max. Min. Max. Min. Max. Min. Max. RAS Pulse Width 35 Read or Write Cycle Time 70 75 90 110 ns 3 tRAS tRC tRP RAS Precharge Time 25 25 30 40 ns 4 tCSH CAS Hold Time 35 40 50 60 ns 5 tCAS CAS Pulse Width 8 8 10 10 ns 6 RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time 13 0 0 6 0 6 0 0 7 0 7 0 0 9 0 9 0 0 10 0 10 ns ns ns ns ns 12 tRCD tRCS tASR tRAH tASC tCAH tRSH RAS to CAS Hold Time 10 12 14 15 ns 13 tCRP 5 5 5 5 ns 14 tRCH 0 0 0 0 ns *2 15 tRRH CAS to RAS Precharge Time Read Command Hold Time Reference CAS Read Command Hold Time Reference RAS 0 0 0 0 ns *2 16 tROH RAS Hold Time Referenced to OE 7 8 10 10 ns 17 tOAC Access Time from OE 11 12 14 15 ns *9 18 tCAC Access Time from CAS 11 12 14 15 ns *3,4,11 19 tRAC 40 50 60 ns *3,5,6 20 tCAA Access Time from RAS Access Time From Column Address 35 18 20 24 30 ns *3,4,7 21 tLZ OE or CAS to Low-Z Output ns *13 22 tHZ ns *13 23 tAR OE or CAS to High-Z Output Column Address Hold Time from RAS 24 tRAD 25 tT 26 tCWL 27 tWCS tWCH tWP 1 2 7 8 9 10 11 28 29 RAS to Column Address Delay Time Transition Time Write Command to CAS Lead Time Write Command Setup Time Write Command Hold time Write Pulse Width 75K 24 0 0 40 17 75K 28 0 5 25 0 50 19 75K 36 0 6 30 0 60 20 75K 45 0 8 40 0 10 50 ns ns *1 ns 10 17 12 20 14 26 15 30 ns *8 1.5 50 1.5 50 1.5 50 1.5 50 ns *12 8 10 10 10 ns 0 5 5 0 6 6 0 7 7 0 10 10 ns ns ns UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 *9,10 P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 AC CHARACTERISTICS ( continued ) SYMBOL PARAMETER Write Command Hold Time from RAS 30 tWCR 31 tRWL 32 33 tDS tDH 34 tWOH 35 36 tOED tRWC 37 tRRW 38 tCWD CAS to WE Delay in ReadModify-Write Cycle 39 tRWD 40 35 40 50 60 UNIT NOTE Min. Max. Min. Max. Min. Max. Min. Max. 25 30 40 50 ns 11 12 14 15 ns 0 5 0 6 0 7 0 10 ns ns *11 Write to OE Hold time 5 6 8 10 ns *11 OE to Data Delay Time 5 6 8 10 ns *11 110 130 170 ns 75 85 105 ns 28 30 34 40 ns *9 RAS to WE Delay in ReadModify-Write Cycle 54 58 68 85 ns *9 tCRW CAS pulse Width in RMW 46 48 52 65 ns 41 tAWD 35 38 42 58 ns 42 tPC Column Address to WE Delay Time EDO Page Mode Read or Write Cycle Time 14 15 19 27 ns 43 tCP 4 5 7 10 ns 44 tCAR 18 20 24 30 ns 45 tCAP 46 tDHR CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge Data in Hold Time Referenced to RAS 47 tCSR 48 tRPC 49 tCHR 50 tPCM CAS Hold Time in CBR Refresh EDO Page Mode Cycle Time in RMW 51 tCOH 52 tOES 53 tOEH OE Hold Time from WE in RMW Cycle 54 tOEP tREF OE Pulse Width Refresh Interval (512 Cycles) 55 Write Command to RAS Lead Time Data in Setup Time Data in Hold Time Read-Modify-Write Cycle Time 105 Read-Modify-Write Cycle Time 70 RAS Pulse Width 20 23 27 34 ns 25 30 40 50 ns CAS Setup Time in CBR Refresh 8 10 10 10 ns RAS to CAS Precharge 0 0 0 0 ns 8 9 12 15 ns 55 60 70 85 ns Output Hold After CAS Low 3 3 3 3 ns OE Low to CAS High Setup 3 4 6 8 ns 5 6 8 10 ns Time Time 8 10 8 14 8 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 18 8 *11 *9 *4 ns 8 ms *14 P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 Notes: 1. tRCD (Max.) is specified for reference only. Operation within tRCD (Max.) limits insures that tRAC (Max.) and tCAA (Max.) can be met. If tRCD is greater than the specified tRCD (Max.), the access time is controlled by tCAA and tCAC. 2. Either tRRH or tRCH must be satisfied for Read Cycle to occur. 3. Measured with a load equivalent to one TTL input and 50pF. 4. Access time is determined by the longest of tCAA , tCAC and tCAP . 5. Assumes that tRAD ≦ tRAD (Max.). If tRCD is greater than tRCD (Max.), tRAC will increase by the amount that tRCD exceeds tRCD (Max.) 6. Assumes that tRCD ≦ tRCD (Max.). If tRCD is greater than tRCD (Max.), tRAC will increase by the amount that tRAD exceeds tRAD (Max.) 7. Assumes that tRAD ≧ tRAD (Max.). 8. Operation within the tRAD (Max.) limits ensures that tRA can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.), the access time is controlled by tCAA and tCAC. 9. tWCS , tRWD , tAWD and tCWD are not restrictive operating parameters. 10. tWCS (min.) must be satisfied in an Early Write Cycle. 11. tDS and tDH are referenced to the latter occurrence of CAS or WE . 12. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3ns. 13. Assumes a tri-state test load (5pF and a 500Ohm Thevenin equivalent). 14.An initial pause of 200us is required after power-up followed by any 8 CBR or ROR cycles before device operation is achieved. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 TRUTH TABLE FUNCTION RAS H L L L LCAS H L L H Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word L L (Early-Write) Write: Lower Byte L L (Early-Write) Write: Upper Byte L H (Early-Write) Read-Write L L EDO Page-Mode H→L L Read EDO Page-Mode H→L L Write EDO Page –Mode H→L L Read-Write Hidden Refresh L→H→L L Read RAS Only L H Refresh CBR Refresh H→L L UCAS H L H L WE X H H H OE X L L L L L X H L X L L X L H→L H→L H H→L L X H→L H→L L→H L H L H X X L X X ADDRESS DQ(0-7) DQ(8-15) NOTE X ROW/COL ROW/COL ROW/COL ROW/COL High-Z High-Z DQ-OUT DQ-OUT High-Z High-Z DQ-OUT DQ-IN ROW/COL DQ-IN High-Z ROW/COL High-Z DQ-IN L→H ROW/COL DQ-OUT,DQ-IN COL DQ-OUT L *1,2 *2 COL DQ-IN *2 COL DQ-OUT,DQ-IN *1,2 ROW/COL DQ-OUT ROW High-Z X High-Z *2 Notes: 1. Byte Write cycles LCAS or UCAS active. 2. Byte Read cycles LCAS or UCAS active. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― Waveforms of Read Cycle t RAS(1) V RAS IH － V IL － UCAS, V IH － LCAS V IL － t RCD(6) t CSH(4) t t CAS(5) t RAD(24) t CAH(11) t ASC(10) ROW ADDRESS COLUMN ADDRESS t RRH(15) V IH － V IL － t ROH(16) t CAA(20) V IH － V IL － t OAC(17) t RAC(19) DQ t RCH(14) t CAR(24) tRCS (7) OE t CRP(13) RSH(12) t RAH(9) t ASR(8) WE t RP(3) t AR(23) t CRP(13) V IH － Address V IL － t RC(2) t CAC(18) t OES(52) V OH － V OL － t HZ(22) t HZ(22) VALID DATA - OUT t LZ(21) Don't care UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 Undefined P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― Waveforms of Early Write Cycle t RAS(1) V RAS IH － V IL － t CSH(4) t RCD(6) t RSH(12) t CRP(13) t CAS(5) UCAS, V IH － LCAS V IL － t RAH(9) t ASR(8) V IH － V IL － t RP(3) t AR(23) t CRP(13) Address t RC(2) t CAH(11) t ASC(10) ROW ADDRESS t CAR(44) COLUMN ADDRESS t RAD(24) t WCH(28) t CWL(26) WE V IH － V IL － t WCS (27) t WP(29) tWCR OE (30) t RWL (31) V IH － V IL － t DHR(46) t DS(32) DQ V IH － V IL － t DH(33) VALID DATA - IN HIGH-Z Don't Care UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 Undefined P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram Waveforms of OE-Contrilled Write Cycle t RC(2) t RAS(1) V RAS IH － V IL － t RP(3) t AR(23) t CRP(13) t CSH(4) t RCD(6) t RSH(12) t CRP(13) t CAS(5) UCAS, V IH － LCAS V IL － t RAD(24) t RAH(9) tASR(8) Address V IH － V IL － ROW ADDRESS t ASC(10) t CAH(11) t CAR(44) COLUMN ADDRESS tCWL (26) tRWL(31) WE tWP (29) V IH － V IL － tWOH (34) OE V IH － V IL － tOED (35) tDS (32) DQ V IH － V IL － tDH(33) VALID DATA -IN Don' t Care UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 12 Undefined P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― Waveforms - of Read -Modify-Write Cycle t RRW(37) RAS V IH － V IL － t CSH(4) t RCD(6) CRP(13) t RAH(9) t CAH(11) t ASR(8) OE V IH － V IL － t ROW ADDRESS t ACS V IH － V IL － t CRP(13) t RSH(12) t CRW(40) UCAS, V IH － LCAS V IL － WE t RP(3) t AR(23) t V － Address IH V IL － t RWC(36) ASC(10) COLUMN ADDRESS t RAD(24) tRWD (39) t CAA tCWD (38) tCWL(26) tAWD (41) tRWL(31) tWP(29) (20) tOAC (17) t OEH tCAC t RAC(19) DQ tOED (18) (53) (35) tDH (33) t HZ (22) t DS (32) V IH VOH－ V IL VOL－ VALID DATA-OUT t VALID DATA -IN LZ(21) Don't Care UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 13 Undefined P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― EDO Page Mode Read Cycle t RP(3) t RAS(1) t AR(23) V RAS IH － V IL － t RCD(6) ⌇ ⌇ t PC(42) t CRP(13) t RSH(12) t CP(43) t CAS(5) t CAS(5) UCAS, V IH － LCAS V IL － t CRP(13) t CAS(5) ⌇ ⌇ t CSH(4) t RAH(9) t ASR(8) t t ASC(10) CAH(11) t t ASC(10) CAR(44) t CAH(11) ⌇⌇ Address V IH － V IL － ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS ⌇⌇ t RCS(7) t t CAH(11) RCH(14) t RCS(7) t RCH(14) t RCS(7) ⌇⌇ WE V IH － V IL － t CAP(45) t t V IH － V IL － ⌇⌇ t OEP(54) t CAC(18) RAC(19) t CAC(18) t LZ(21) DQ ⌇⌇ t OES(52) t V OH － V OL － t RRH(15) t OAC(17) t OAC(17) OE CAA(20) CAA(20) t COH(5) VALID DATA OUT t CAC(18) t HZ(22) VALID DATA OUT t t HZ(22) t HZ(22) t HZ(22) VALID DATA OUT LZ Don' t Care UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 14 Undefined P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― EDO Page Mode Write Cycle tAR(23) RAS t RP(3) t RAS(1) V IH － V IL － ⌇⌇ t PC(42) t CRP(13) t RCD(6) t CAS(5) UCAS, V LCAS V IH － V IL － t CSH(4) t CAH (11) OE ROW ADDRESS － IH V IL － V V COLUMN ADDRESS ⌇⌇ t t CWL(26) t t WCH(28) t WP(29) t CAH (11) ⌇⌇ t CWL(26) CWL(26) WCS(27) t WCH(28) t WP(29) t WCS(27) ⌇⌇ ⌇⌇ t t RWL(31) WCH(28) t WP(29) ⌇⌇ IH － IL － VIH V t ASC (10) COLUMN ADDRESS COLUMN ADDRESS ⌇⌇ t DS (32) DQ ⌇⌇ t ASC (10) t CAH(11) t WCS(27) V t CRP(13) t CAS(5) t CAR(44) t RAH(9) t RAD(24) WE t CAS(5) IH － V IL － t ASR(8) Address t RSH(12) t CP(43) IL t DS (32) t DS(32) t DH (33) － VALID － DATA IN OPEN t DH (33) tDH (33) VALID VALID DATA IN DATA IN OPEN Don't care UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 15 Undefined P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― RAS EDO Page Mode Read-Write Cycle t RAS(1) V IH － V IL － t RP(3) t RSH(12) t CSH(4) t PCM(50) t RCD(6) UCAS, V IH － LCAS V IL － V IH － V IL － t ASC(10) t RAH(9) ROW ADD tCAH V IH － V IL － t ASC(10) tCWL(26) t CWD(38) t tCWL(26) t AWD(41) t AWD(41) tWP (29) tOAC(17) t RWL (31) CWL (26) t AWD(41) t WP (29) t WP (29) tOAC(17) tOAC(17) tOEH(35) V IH － V IL － t CAP (45) t OED(35) t HZ(22) t RAC(19) V I/OH － V I/OL － t CAR(44) (11) COLUMN ADDRESS t CWD(38) CWD(38) t CAA (20) DQ t CAH (11) COLUMN ADDRESS COLUMN ADDRESS t OE t CAS(5) t ASC(10) tCAH(11) t RWD(39) WE t CAS(5) t RAD(24) t ASR(8) Address t CRP(13) t CP(43) t CAS(5) t tCAC (18) DH(33) tCAP(45) tCAA(20) tCAA (20) t OED(35) t HZ(22) t CAC tDH(33) (18) tDS(32) OUT tDS (32) OUT IN t LZ(21) IN tLZ(21) t OED(35) tHZ(22) tCAC(18) tDH(33) t DS (32) OUT t IN LZ(21) Don' t Care UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 16 Undefined P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― Waveforms of RAS - Only Refresh Cycle t RC(2) t RAS(1) RAS t RP(3) V IH － V IL － tCRP(13) UCAS, V IH － LCAS V IL － tASR(8) Address V IH － V IL － tRAH(9) ROW ADD Note: WE, OE = Don't care Don't care UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 17 Undefined P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― Waveforms of CAS - before - RAS Refresh Counter Test Cycle t RP(3) t RAS(1) RAS V IH － V IL － t CSR(47) t CHR(49) t CP(43) t RSH(12) t CAS(5) UCAS, V IH － LCAS V IL － Address V IH － V IL － Read Cycle WE I/O t t RCS(7) t RCH(14) V IH － V IL － t LZ(21) V OH － V OL － t HZ(22) DOUT t RWL(31) Write Cycle WE OE V IH － V IL － V IH － V IL － RRH(15) t WCS(27) t t WCH(28) t DH(33) DS(32) DQ V IH － t CWL(26) D IN V IL － Don't Care UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 18 Undefined P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― Waveforms of CAS - before - RAS Refresh Cycle t RC(2) t RP(3) t RAS(1) t RP(3) V RAS IH － V IL － t CHR(49) t RPC(48) t CP(43) t CSR(47) UCAS, V IH － LCAS V IL － t HZ(22) DQ V OH － V OL － Note: WE, OE = A 0 - A 8 = Don't care Don't care UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 19 Undefined P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram Waveforms of Hidden Refresh Cycle (Read) ― t RC(2) V RAS IH － V IL － t RC(2) t RP(3) t RAS(1) t t RAS(1) RP(3) t AR(23) t RCD(6) t t CRP(13) t CHR(49) RSH(12) t CRP(13) UCAS, V IH － LCAS V IL － t RAD(24) t Address V IH － V IL － t ASC(10) ASR(8) t CAH(11) t RAH(9) ROW ADD COLUMN ADDRESS t RRH(15) t RCS(7) WE OE V IH － V IL － t CAA(20) t OAC(17) V IH － V IL － t t RAC(19) DQ CAC(18) t LZ(21) t V OH － V OL － HZ(22) t HZ(22) VALID DATA Don't Care UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 20 Undefined P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― Waveforms of Hidden Refresh Cycle (Write) t t RC(2) t RAS t VIH － VIL － t t t t tASR(8) t RSH(12) t RP(3) t CHR(49) t CRP(13) RAD(24) t CAH(11) RAH(9) ROW ADD COLUMN ADDRESS t t WCS(27) WE RC(2) AR(23) RCD(6) t ASC(10) t VIH － VIL － RAS(1) RAS(1) CRP(13) UCAS, VIH － LCAS VIL － Address t RP(3) WCH(28) VIH － VIL － － OE VIH VIL － t DQ VIH － VIL － DS(32) t DH(33) VALID DATA -IN t DHR(46) don't care UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 21 Undefined P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― Waveforms of EDO-Page-Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write) t t RAS RP V IH － RAS V － IL t t CRP t UCAS V IH － LCAS V IL － V IH － V IL － RAD t RAH ASR tASC ROW ADD V IH － V IL － OE CP t CAH t ASC t t PC CAS t CP t t CAH COLUMN ADDRESS RSH t CAS t CAR t CP ASC t CAH COLUMN ADDRESS t RCH RCS t t CAA t RAC V IH － V IL － t t CAS COLUMN ADDRESS t WE t PC t AR t t Address t CSH RCD t WCH WCS t CAA t CAC t CAP t CAC t DS t OE t DH t COH DQ V OH － VOL － VALID DATA -OUT VALID DATA -OUT VALID DATA -IN Don't care UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 22 Undefined P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 PACKAGE OUTLINE DIMENSION 40 pin 400mil SOJ Package Outline Dimension UNIT：MIL SYMBOLS A A1 A2 D E H MIN. 130 0.24 106 430 NOR. 134 110 1025 BSC. 400 BSC. 440 MAX. 138 114 450 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 23 P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 40 pin 400mil TSOP-Ⅱ Package Outline Dimension UNIT MM(BASE) SYMBOL A A1 A2 b t D E1 E e L L1 θ 1.20(MAX) 0.10± 0.05 1.00± 0.05 0.30~0.45 0.13(TYP) 18.41± 0.10 10.16± 0.10 11.76± 0.20 0.80(TYP) 0.50± 0.10 0.80(REF) 0° ~8° UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 24 P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 ORDERING INFORMATION PART NO. UT51C164JC-35 UT51C164JC-40 UT51C164JC-50 UT51C164JC-60 UT51C164MC-35 UT51C164MC-40 UT51C164MC-50 UT51C164MC-60 ACCESS TIME (ns) 35 40 50 60 35 40 50 60 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 25 PACKAGE 40-PIN SOJ 40-PIN SOJ 40-PIN SOJ 40-PIN SOJ 40-PIN TSOP-Ⅱ 40-PIN TSOP-Ⅱ 40-PIN TSOP-Ⅱ 40-PIN TSOP-Ⅱ P90005 UTRON UT51C164 256K X 16 BIT EDO DRAM Rev 1.4 REVISION HISTORY REVISION Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 DESCRIPTION Original. Add 40 pin TSOP-II Package. Add 3.3V range. Revised Datasheet name to be UT51C164/UT51L164. 1. Separated VDD=5V and VDD=3.3V version. 2. Revise symbols “RAS#、CAS#、OE#、WE#” to be “ RAS 、 CAS 、 OE 、 WE ”. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 26 DATE Apr 30 ,1999 Jun 7 ,1999 Jul 30,1999 Sep 22,2000 Jan 23,2002 P90005