MOSEL V53C16256SH

MOSEL VITELIC
PRELIMINARY
V53C16256SH
256K X 16 FAST PAGE MODE
CMOS DYNAMIC RAM WITH
SELF REFRESH
HIGH PERFORMANCE
40
50
Max. RAS Access Time, (tRAC)
40 ns
50 ns
Max. Column Address Access Time, (tCAA)
20 ns
24 ns
Min. Fast Page Mode Cycle Time, (tPC)
23 ns
28 ns
Min. Read/Write Cycle Time, (tRC)
75 ns
90 ns
Features
Description
■ 256K x 16-bit organization
■ Fast Page Mode for a sustained data rate
of 43 MHz
■ RAS access time: 40, 50 ns
■ Dual CAS Inputs
■ Low power dissipation
■ Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, and Self Refresh
■ Refresh Interval: 512 cycles/8 ms
■ Available in 40-pin 400 mil SOJ and
40/44L-pin 400 mil TSOP-II packages
■ Single 5.0V ±10% Power Supply
■ TTL Interface
■ Self Refresh: 512 cycles/8ms
The V53C16256SH is a 262,144 x 16 bit highperformance CMOS dynamic random access memory. The V53C16256SH offers Fast Page mode
with dual CAS inputs. An address, CAS and RAS input capacitances are reduced to one quarter when
the x4 DRAM is used to construct the same memory
density. The V53C16256SH has symmetric address and accepts 512 cycle 8ms interval.
All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 512 x 16 bits,
within a page, with cycle times as short as 23ns.
The V53C16256SH is best suited for graphics,
and DSP applications.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
Access Time (ns)
Power
K
T
40
50
Std.
Temperature
Mark
•
•
•
•
•
Blank
V53C16256SH Rev. 0.1 December 1998
1
V53C16256SH
MOSEL VITELIC
40-Pin Plastic SOJ
PIN CONFIGURATION
Top View
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
40/44 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
16256L-02
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
16256L-03
Pin Names
A0–A8
Address Inputs
RAS
Row Address Strobe
UCAS
Column Address Strobe Upper Byte Control
LCAS
Column Address Strobe Lower Byte Control
WE
Write Enable
OE
Output Enable
I/O1–I/O16
Data Input, Output
VCC
+3.3V Supply
VSS
0V Supply
NC
No Connect
V53C16256SH Rev. 0.1 December 1998
2
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
V53C16256SH
MOSEL VITELIC
Absolute Maximum Ratings*
Capacitance*
TA = 25°C, VCC = 5.0 V ± 10%, VSS = 0 V
Ambient Temperature
Under Bias ................................ –10°C to +80°C
Storage Temperature (plastic) ..... –55°C to +125°C
Voltage Relative to VSS .................–1.0 V to +7.0 V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.0 W
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Symbol
Parameter
Typ.
Max.
Unit
CIN1
Address Input
3
4
pF
CIN2
RAS, UCAS, LCAS,
WE, OE
4
5
pF
COUT
Data Input/Output
5
7
pF
* Note: Capacitance is sampled and not 100% tested
Block Diagram
256K x 16
OE
WE
UCAS
LCAS
RAS
RAS CLOCK
GENERATOR
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VCC
VSS
I/O 1
DATA I/O BUS
I/O 2
I/O 3
COLUMN DECODERS
I/O 4
I/O 5
Y0 -Y 8
SENSE AMPLIFIERS
REFRESH
COUNTER
512 x 16
A1
•
•
•
A7
A8
V53C16256SH Rev. 0.1 December 1998
I/O
BUFFER
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
X0 -X 8
ROW
DECODERS
A0
ADDRESS BUFFERS
AND PREDECODERS
9
I/O 6
512
MEMORY
ARRAY
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
16256L-04
3
V53C16256SH
MOSEL VITELIC
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC = 5V ± 5%, VSS = 0 V, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C16256SH
Min.
Typ.
Max.
Unit
Test Conditions
ILI
Input Leakage Current
(any input pin)
–10
10
µA
VSS ≤ VIN ≤ VCC
ILO
Output Leakage Current
(for High-Z State)
–10
10
µA
VSS≤ VOUT ≤ VCC
RAS, CAS at VIH
ICC1
VCC Supply Current,
Operating
40
180
mA
tRC = tRC (min.)
50
160
2
mA
RAS, CAS at VIH
other inputs ≥ VSS
40
180
mA
tRC = tRC (min.)
50
160
400
µA
RAS, LCAS, UCAS = 0.2V
A0 – A8 = VCC – 0.2V or 0.2V
40
170
mA
Minimum Cycle
50
150
ICC2
VCC Supply Current,
TTL Standby
ICC3
VCC Supply Current,
RAS-Only Refresh
ICCS
Self Refresh Current
ICC4
VCC Supply Current,
Fast Page Mode Operation
Notes
1, 2
2
1, 2
ICC5
VCC Supply Current,
Standby, Output Enabled
other inputs ≥ VSS
2
mA
RAS=VIH, CAS=VIL
ICC6
VCC Supply Current,
CMOS Standby
1
mA
RAS ≥ VCC – 0.2 V,
CAS ≥ VCC– 0.2 V,
All other inputs ≥ VSS
VCC
Supply Voltage
5.25
V
VIL
Input Low Voltage
–1
0.8
V
3
VIH
Input High Voltage
2.0
VCC+1
V
3
VOL
Output Low Voltage
0.4
V
IOL = 2.0 mA
VOH
Output High Voltage
V
IOH = –2.0 mA
V53C16256SH Rev. 0.1 December 1998
4.75
5.0
2.4
4
1
V53C16256SH
MOSEL VITELIC
AC Characteristics
TA = 0°C to 70°C, VCC = 5V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
40
#
Symbol
Parameter
1
tRAS
2
50
Min.
Max.
Min.
RAS Pulse Width
40
75
50
tRC
Read or Write Cycle Time
75
90
ns
3
tRP
RAS Precharge Time
25
30
ns
4
tCSH
CAS Hold Time
40
50
ns
5
tCAS
CAS Pulse Width
12
14
ns
6
tRCD
RAS to CAS Delay
17
7
tRCS
Read Command Setup Time
0
0
ns
8
tASR
Row Address Setup Time
0
0
ns
9
tRAH
Row Address Hold Time
7
9
ns
10
tASC
Column Address Setup Time
0
0
ns
11
tCAH
Column Address Hold Time
5
7
ns
12
tRSH (R)
RAS Hold Time (Read Cycle)
12
14
ns
13
tCRP
CAS to RAS Precharge Time
5
5
ns
14
tRCH
Read Command Hold Time Referenced to CAS
0
0
ns
5
15
tRRH
Read Command Hold Time Referenced to RAS
0
0
ns
5
16
tROH
RAS Hold Time Referenced to OE
8
10
ns
17
tOAC
Access Time from OE
12
14
ns
18
tCAC
Access Time from CAS
12
14
ns
6, 7
19
tRAC
Access Time from RAS
45
55
ns
6, 8, 9
20
tCAA
Access Time from Column
Address
20
24
ns 6, 7, 10
21
tLZ
OE or CAS to Low-Z Output
0
22
tHZ
OE or CAS to High-Z Output
0
23
tAR
Column Address Hold Time from RAS
30
24
tRAD
RAS to Column Address Delay Time
12
25
tRSH (W)
RAS or CAS Hold Time in Write Cycle
12
14
ns
26
tCWL
Write Command to CAS Lead Time
12
14
ns
27
tWCS
Write Command Setup Time
0
0
ns
28
tWCH
Write Command Hold Time
5
7
ns
29
tWP
Write Pulse Width
5
7
ns
30
tWCR
Write Command Hold Time from RAS
30
40
ns
31
tRWL
Write Command to RAS Lead Time
12
14
ns
32
tDS
Data in Setup Time
0
0
ns
V53C16256SH Rev. 0.1 December 1998
5
28
19
Max. Unit Notes
75K
36
0
6
0
8
40
20
14
ns
ns
4
ns
16
ns
16
ns
26
ns
11
12, 13
14
V53C16256SH
MOSEL VITELIC
AC Characteristics (Cont’d)
40
#
Symbol
Parameter
33
tDH
Data in Hold Time
34
tWOH
35
Min.
Max. Unit Notes
5
7
ns
14
Write to OE Hold Time
6
8
ns
14
tOED
OE to Data Delay Time
6
8
ns
14
36
tRWC
Read-Modify-Write Cycle Time
110
130
ns
37
tRRW
Read-Modify-Write Cycle RAS Pulse
Width
75
87
ns
38
tCWD
CAS to WE Delay
30
34
ns
12
39
tRWD
RAS to WE Delay in Read-Modify-Write
Cycle
58
68
ns
12
40
tCRW
CAS Pulse Width (RMW)
48
52
ns
41
tAWD
Col. Address to WE Delay
38
42
ns
42
tPC
Fast Page Mode Read or Write Cycle
Time
23
28
ns
43
tCP
CAS Precharge Time
5
7
ns
44
tCAR
Column Address to RAS Setup Time
20
24
ns
45
tCAP
Access Time from Column Precharge
46
tDHR
Data in Hold Time Referenced to RAS
30
40
ns
47
tCSR
CAS Setup Time CAS-before-RAS
Refresh
10
10
ns
48
tRPC
RAS to CAS Precharge Time
0
0
ns
49
tCHR
CAS Hold Time CAS-before-RAS
Refresh
8
12
ns
50
tPCM
Fast Page Mode Read-Modify-Write
Cycle Time
60
70
ns
51
tT
Transition Time (Rise and Fall)
3
52
tREF
Refresh Interval (512 Cycles)
53
tREF
Self Refresh
54
tRASS
RAS Pulse Width During Self Refresh
100
100
µs
18
55
tRPS
RAS Precharge Time During Self Refresh
100
100
ns
18
56
tCHS
CAS Hold Time Width During Self Refresh
100
100
ns
18
57
tCHD
CAS Low Time During Self Refresh
100
100
ns
18
V53C16256SH Rev. 0.1 December 1998
Min.
50
Max.
22
6
50
27
3
ns
12
7
50
ns
15
8
8
ms
17
8
8
ms
V53C16256SH
MOSEL VITELIC
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two
transitions per address cycle in Fast Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VCC.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to one TTL input and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.).
9. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD ≥ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
18.
One CBR refresh or complete set of row refresh cycles must be completed upon existing Self Refresh Mode.
V53C16256SH Rev. 0.1 December 1998
7
V53C16256SH
MOSEL VITELIC
Truth Table
RAS
LCAS
UCAS
WE
OE
ADDRESS
Standby
H
H
H
X
X
X
Read: Word
L
L
L
H
L
ROW/COL
Data Out
Read: Lower Byte
L
L
H
H
L
ROW/COL
Lower Byte, Data-Out
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte, Data-Out
Write: Word (Early-Write)
L
L
L
L
X
ROW/COL
Data-In
Write: Lower Byte (Early)
L
L
H
L
X
ROW/COL
Lower Byte, Data-In
Upper Byte, High-Z
Read: Upper Byte (Early)
L
H
L
L
X
ROW/COL
Lower Byte, High-Z
Upper Byte, Data-In
Read-Write
L
L
L
H→L
L→H
ROW/COL
Data-Out, Data-In
Fast Page-Mode Read
L
H→L
H→L
H
L
COL
Data-Out
2
Fast Page-Mode Write
L
H→L
H→L
L
X
COL
Data-In
2
Fast Page-Mode Read-Write
L
H→L
H→L
H→L
L→H
COL
Data-Out, Data-In
L→H→L
L
L
H
L
ROW/COL
L
H
H
X
X
ROW
CBR Refresh
H→L
L
L
X
X
High-Z
Self Refresh
H→L
H
H
H
H
High-Z
Function
Hidden Refresh Read
RAS-Only Refresh
Notes:
1. Byte Write cycles LCAS or UCAS active.
2. Byte Read cycles LCAS or UCAS active.
3. Only one of the two CAS must be active (LCAS or UCAS).
V53C16256SH Rev. 0.1 December 1998
8
I/O
Notes
High-Z
Data-Out
1, 2
1, 2
2
High-Z
3
V53C16256SH
MOSEL VITELIC
Waveforms of Read Cycle
RAS
t RAS (1)
t AR (23)
VIH
t RC (2)
t RP (3)
VIL
t CRP (13)
UCAS, LCAS
t RSH (R)(12)
t CAS (5)
VIH
VIL
t RAH (9)
VIH
ROW ADDRESS
VIL
t CAH (11)
t ASC (10)
COLUMN ADDRESS
t RCH (14)
t CAR (44)
t RCS (7)
WE
t CRP (13)
t RAD (24)
t ASR (8)
ADDRESS
t CSH (4)
t RCD (6)
t RRH (15)
VIH
VIL
t ROH (16)
t CAA (20)
OE
t OAC (17)
VIH
VIL
I/O
t CAC (18)
t RAC (19)
VOH
t HZ (22)
t HZ (22)
VALID DATA-OUT
VOL
16256L-05
t LZ (21)
Waveforms of Early Write Cycle
t RC (2)
t RAS (1)
RAS
t RP (3)
tAR (23)
VIH
V IL
t CSH (4)
tCRP (13)
t RCD (6)
t RSH (W)(25)
t CAS (5)
VIH
UCAS, LCAS
V IL
t CAR (44)
t CAH (11)
t RAH (9)
tASR (8)
ADDRESS
t CRP (13)
VIH
V IL
tASC (10)
ROW ADDRESS
COLUMN ADDRESS
t WCH (28)
t RAD (24)
t CWL (26)
WE
t WP(29)
tWCS (27)
VIH
V IL
t WCR (30)
t RWL (31)
OE
VIH
V IL
t DHR (46)
tDS (32)
I/O
VIH
V IL
tDH (33)
VALID DATA-IN
HIGH-Z
16256L-06
Don’t Care
V53C16256SH Rev. 0.1 December 1998
9
Undefined
V53C16256SH
MOSEL VITELIC
Waveforms of OE-Controlled Write Cycle
RAS
t AR (23)
V IH
t CSH (4)
t RCD (6)
t RSH (W)(12)
t CAS (5)
V IH
t CRP (13)
V IL
t RAD (24)
t RAH (9)
t ASR (8)
ADDRESS
t RP (3)
V IL
t CRP (13)
UCAS, LCAS
t RC (2)
t RAS (1)
V IH
ROW ADDRESS
V IL
t CAR (44)
t CAH (11)
t ASC (10)
COLUMN ADDRESS
t CWL (26)
t RWL (31)
t WP (29)
WE
V IH
V IL
t WOH (34)
OE
V IH
V IL
t OED (35)
I/O
t DH (33)
t DS (32)
V IH
VALID DATA-IN
V IL
16256L-07
Waveforms of Read-Modify-Write Cycle
t RWC (36)
tRRW (37)
RAS
t RP (3)
t AR (23)
VIH
VIL
t CSH (4)
t CRP (13)
UCAS, LCAS
t RCD (6)
t RSH (W)(25)
t CRW (40)
VIH
VIL
t
t RAH (9)
VIH
ROW
ADDRESS
VIL
COLUMN
ADDRESS
t RAD (24)
t RWD (39)
WE
OE
CAH (11)
t ASC (10)
t ASR (8)
ADDRESS
t CRP (13)
t AWD (41)
t CWD (38)
t RWL (31)
t WP (29)
VIH
VIL
t CAA (20)
t OAC (17)
VIH
VIL
t OED (35)
t CAC (18)
t RAC (19)
I/O
t CWL (26)
VIH
VOH
VIL
VOL
t DH (33)
t HZ (22)
t DS (32)
VALID
DATA-OUT
VALID
DATA-IN
t LZ (21)
16256L-08
Don’t Care
V53C16256SH Rev. 0.1 December 1998
10
Undefined
V53C16256SH
MOSEL VITELIC
Waveforms of Fast Page Mode Read Cycle
RAS
tPC (42)
tCP(43)
tCSH (4)
t RAH (9)
tCAR (44)
tASC (10)
t CAH (11)
tASC (10)
VIH
ROW
ADDRESS
COLUMN
ADDRESS
t CAH (11)
COLUMN
ADDRESS
COLUMN
ADDRESS
t RCH (14)
t CAH (11)
t RCS (7)
t RCS (7)
t RCS (7)
V IL
tCAA (20)
t CAA (20)
t CAP (45)
t OAC (17)
tRRH (15)
t OAC (17)
VIH
V IL
tHZ (22)
tRAC (19)
tCAC (18)
t LZ (21)
t CAC (18)
t (18)
CAC
t HZ (22)
VOH
tHZ (22)
tHZ (22)
VALID
DATA OUT
VOL
tHZ (22)
tHZ (22)
t LZ (21)
t LZ (21)
I/O
tRCH (14)
VIH
t OAC (17)
OE
t CRP (13)
t CAS (5)
tCAS (5)
V IL
V IL
WE
tRSH (R)(12)
t CAS (5)
VIH
tASR (8)
ADDRESS
RP (3)
V IL
t RCD (6)
tCRP (13)
CAS
t
t RAS (1)
tAR (23)
VIH
VALID
DATA OUT
VALID
DATA OUT
16256L-09
Waveforms of Fast Page Mode Write Cycle
tRP (3)
tAR (23)
RAS
t RAS (1)
VIH
V IL
t CRP (13)
tRCD (6)
UCAS, LCAS
t PC (42)
t CP(43)
t CAS (5)
VIH
t RSH (W)(25)
t CRP (13)
tCAS (5)
tCAS (5)
V IL
tCSH (4)
tRAH (9)
t CAR (44)
tASC (10)
t ASR (8)
ADDRESS
VIH
ROW
ADD
V IL
tASC (10)
tCAH (11)
tCAH (11)
COLUMN
ADDRESS
tRAD (24)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
OE
t WCH (28)
t WCH (28)
tRWL(31)
t WCH (28)
tWP(29)
t WP(29)
VIH
V IL
VIH
VIL
VIH
V IL
tDS (32)
tDH (33)
tDS (32)
t DH (33)
t DS (32)
I/O
tCWL (26)
t WCS (27)
t WP (29)
WE
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t CAH (11)
VALID
DATA IN
VALID
DATA IN
OPEN
tDH (33)
VALID
DATA IN
OPEN
16256L-10
Don’t Care
V53C16256SH Rev. 0.1 December 1998
11
Undefined
V53C16256SH
MOSEL VITELIC
Waveforms of Fast Page Mode Read-Write Cycle
RAS
tRAS (1)
VIH
V
IL
t CSH (4)
tRP (3)
tRCD (6)
tPCM (50)
t RSH (W)(25)
t CRP (13)
t CAS (5)
t CP(43)
t CAS (5)
V
IH
UCAS, LCAS
V
t CAS (5)
t RAD (24)
IL
tRAH (9)
t CAR (44)
tASC (10)
tASC (10)
tASR (8)
V
IH
ADDRESS
V
IL
tASC (10)
tCAH (11)
tCAH (11)
COLUMN
ADDRESS
ROW
ADD
t CAH (11)
COLUMN
ADDRESS
tRWD (39)
COLUMN
ADDRESS
tCWD (38)
t RCS (7)
t CWD (38)
tRWL(31)
tCWL (26)
t CWL (26)
t CWD (38)
t CWL (26)
V
IH
WE
V
IL
tAWD (41)
tAWD (41)
tAWD (41)
t WP(29)
t CAA (20)
t OAC (17)
tWP(29)
tWP(29)
t OAC (17)
t OAC (17)
V
IH
OE
V
IL
tCAP (45)
tCAP (45)
t CAA (20)
t CAA (20)
tOED (35)
tOED (35)
t CAC (18)
t RAC (19)
t CAC (18)
t HZ (22)
tHZ (22)
tDH (33)
t DH (33)
tDS (32)
tDS (32)
I/O
VI/OH
OUT
VI/OL
OUT
IN
tLZ (21)
t LZ (21)
t OED (35)
tCAC (18)
t HZ (22)
tDH (33)
tDS (32)
OUT
IN
tLZ (21)
IN
16256L-11
Waveforms of RAS-Only Refresh Cycle
tRC (2)
RAS
t RAS (1)
VIH
tRP (3)
V IL
t CRP (13)
UCAS, LCAS
VIH
V IL
tASR (8)
ADDRESS
VIH
V IL
tRAH (9)
ROW ADDR
16256L-12
NOTE: WE, OE = Don’t care
Don’t Care
V53C16256SH Rev. 0.1 December 1998
12
Undefined
V53C16256SH
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1)
RAS
VIH
V IL
t CSR (47)
UCAS, LCAS
ADDRESS
t RP (3)
t CHR (49)
t RSH (W)(25)
tCAS (5)
t CP(43)
VIH
V IL
VIH
V IL
READ CYCLE
WE
t RRH (15)
t RCH (14)
t RCS (7)
VIH
V IL
t ROH (16)
t OAC (17)
OE
VIH
V IL
t HZ (22)
t HZ (22)
t LZ (21)
I/O
VIH
DOUT
V IL
t RWL (31)
t CWL (26)
WRITE CYCLE
WE
OE
t WCH (28)
t WCS (27)
VIH
V IL
VIH
V IL
tDS (32)
I/O
t DH (33)
VIH
D IN
V IL
16256L-13
Waveforms of CAS-before-RAS Refresh Cycle
t RC (2)
t RP (3)
RAS
t RAS (1)
t RP (3)
V IH
V IL
t RPC (48)
t CP (43)
t CHR (49)
t CSR (47)
UCAS, LCAS
V IH
V IL
t HZ (22)
I/O
V OH
V OL
16256L-14
NOTE: WE, OE, A 0 –A 8 = Don’t care
Don’t Care
V53C16256SH Rev. 0.1 December 1998
13
Undefined
V53C16256SH
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
tRC (2)
RAS
VIH
tRSH (R)(12)
tCRP (13)
V IL
VIH
tRAD (24)
tASC (10)
t CAH (11)
COLUMN
ADDRESS
ROW
ADD
V IL
tRCS (7)
WE
t CHR (49)
VIH
tASR (8)
t RAH (9)
ADDRESS
t RP (3)
t RAS (1)
V IL
tRCD (6)
t CRP (13)
UCAS, LCAS
tRC (2)
t RP (3)
t RAS (1)
tAR (23)
t RRH (15)
VIH
V IL
t CAA (20)
t OAC (17)
OE
VIH
V IL
t CAC (18)
t LZ (21)
t RAC (19)
I/O
t HZ (22)
t HZ (22)
VOH
VALID DATA
VOL
16256L-15
Waveforms of Hidden Refresh Cycle (Write)
t RC (2)
RAS
VIH
t RSH (12)
VIH
t CAH (11)
ROW
ADD
COLUMN
ADDRESS
t WCH (28)
VIH
V IL
VIH
V IL
t DS (32)
VIH
I/O
t CRP (13)
tRAD (24)
tASC (10)
t WCS (27)
OE
t CHR (49)
V IL
V IL
WE
tRP (3)
VIH
tASR (8)
t RAH (9)
ADDRESS
t RAS (1)
V IL
t RCD (6)
t CRP (13)
UCAS, LCAS
t RC (2)
tRP (3)
t RAS (1)
tAR (23)
V IL
tDH (33)
VALID DATA-IN
t DHR (46)
16256L-16
Don’t Care
V53C16256SH Rev. 0.1 December 1998
14
Undefined
V53C16256SH
MOSEL VITELIC
Waveforms of CAS before RAS Refresh Cycle
tRP
tRASS
tRPS
VIH
RAS
VIL
tRPC
tCSR
tCHS
tCP
VIH
UCAS
LCAS
VIL
tWRP
tWRH
VIH
WE
OE
VIL
VIH
VIL
tCDD
I/O
(Inputs)
VIH
VIL
tODD
tOEZ
VOH
I/O
(Outputs) VOL
HI-Z
tOFF
V53C16256SH Rev. 0.1 December 1998
15
tCRP
V53C16256SH
MOSEL VITELIC
Functional Description
The V53C16256SH is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional
dynamic RAM. The V53C16256SH reads and
writes data by multiplexing an 18-bit address into a
9-bit row and a 9-bit column address. The row address is latched by the Row Address Strobe (RAS).
The column address “flows through” an internal address buffer and is latched by the Column Address
Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the
precise time that the CAS edge occurs, the delay
time from RAS to CAS has little effect on the access
time.
Fast Page Mode Operation
Fast Page Mode operation permits all 512 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining
RAS low while performing successive CAS cycles
retains the row address internally and eliminates the
need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through
latch while CAS is high. Thus, access begins from
the occurrence of a valid column address rather
than from the falling edge of CAS, eliminating tASC
and tT from the critical timing path. CAS latches the
address into the column address buffer and acts as
an output enable. During Fast Page Mode operation, Read, Write, Read-Modify-Write or ReadWrite-Read cycles are possible at random addresses within a row. Following the initial entry cycle into
Fast Page Mode, access is tCAA or tCAP controlled.
If the column address is valid prior to the rising edge
of CAS, the access time is referenced to the CAS
rising edge and is specified by tCAP. If the column
address is valid after the rising CAS edge, access
is timed from the occurrence of a valid address and
is specified by tCAA. In both cases, the falling edge
of CAS latches the address and enables the output.
Fast Page Mode provides a sustained data rate of
43 MHz for applications that require high data rates
such as bit-mapped graphics or high-speed signal
processing. The following equation can be used to
calculate the maximum data rate:
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time tRP/tCP has elapsed.
Read Cycle
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only
when tOAC, tRAC, tCAA and tCAC are all satisifed. As
a result, the access time is dependent on the timing
relationships between these parameters. For example, the access time is limited by tCAA when tRAC,
tCAC and tOAC are all satisfied.
512
Data Rate = ---------------------------------------t RC + 511 × t PC
Self Refresh
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and tOED must be satisfied.
V53C16256SH Rev. 0.1 December 1998
Self Refresh mode provides internal refresh control signals to the DRAM during extended periods of
inactivity. Device operation in this mode provides
additional power savings and design ease by elimination of external refresh control signals. Self Refresh mode is initialed with a CAS before RAS
(CBR) Refresh cycle, holding both RAS low (tRASS)
and CAS low (tCHD) for a specified period. Both of
these parameters are specified with minimum values to guarantee entry into Self Refresh operation.
Once the device has been placed in to Self Refresh
mode the CAS clock is no longer required to maintain Self Refresh operation.
16
V53C16256SH
MOSEL VITELIC
Table 1. V53C16256SH Data Output
The Self Refresh mode is terminated by returning
the RAS clock to a high level for a specified (tRPS)
minimum time. After termination of the Self Refresh
cycle normal accesses to the device may be initiated immediately, poviding that subsequest refresh
cycles utilize the CAS before RAS (CBR) mode of
operation.
Operation for Various Cycle Types
Data Output Operation
The V53C16256SH Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected
row address in the Memory Array. A RAS high transition disables data transfer and latches the output
data if the output is enabled. After a memory cycle
is initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled,
can be disabled by holding OE high. The OE signal
has no effect on any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE
goes low at a time in relationship to CAS that would
normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to
the WE low transition to allow Data In Setup Time
(tDS) to be satisfied.
Power-On
After application of the VCC supply, an initial
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement of
the V53C16256SH is dependent on the input levels
of RAS and CAS. If RAS is low during Power-On,
the device will go into an active cycle and ICC will exhibit current transients. It is recommended that RAS
and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
V53C16256SH Rev. 0.1 December 1998
17
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled. High
OE = High-Z I/Os
Read-Modify-Write
Cycles
Data from Addressed
Memory Cell
Fast Page Mode Read
Data from Addressed
Memory Cell
Fast Page Mode Write
Cycle (Early Write)
High-Z
Fast Page Mode ReadModify-Write Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
V53C16256SH
MOSEL VITELIC
Package Diagrams
40-Pin Plastic SOJ
Unit in inches [mm]
20
0.026 MIN
[0.660 MIN]
+0.004
0.025 –0.002
+0.102
0.635 –0.051
0.368 ± 0.010
[9.35 ± 0.254]
1
0.010
0.144 MAX
[3.66 MAX]
21
0.400 ±0.005
[10.16 ± 0.127]
40
0.440 ±0.005
[11.18 ± 0.127]
1.025 TYP. (1.035 MAX.)
[26.04 TYP. (26.29 MAX.)]
+ 0.004
– 0.002
+0.102
0.254 –0.051
0.04 [0.1]
0.050 ± 0.006
[1.27 ± 0.152]
0.018
+0.004
–0.002
+0.102
0.457 –0.051
40/44L-Pin TSOP-II
40
21
1
20
0°–5°
0.0315 BSC
[.8001 BSC]
0.012 – 0.016
[0.305 – 0.406]
0.039 – 0.047
[0.991 – 1.193]
0.002 – 0.008
[0.051 – 0.203]
BASE PLANE
SEATING PLANE
0.721 – 0.729
[18.31 – 18.52]
V53C16256SH Rev. 0.1 December 1998
18
Unit in inches [mm]
0.017 – 0.023
[0.432 – 0.584]
0.396 – 0.404
[10.06 – 10.26]
0.462 – 0.470
[11.73 – 11.94]
0.0047 – 0.0083
[0.119 – .211]
MOSEL VITELIC
WORLDWIDE OFFICES
V53C16256SH
U.S.A.
TAIWAN
JAPAN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
WBG MARINE WEST 25F
6, NAKASE 2-CHOME
MIHAMA-KU, CHIBA-SHI
CHIBA 261-71
PHONE: 81-43-299-6000
FAX: 81-43-299-6555
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 852-2665-4883
FAX: 852-2664-7535
1 CREATION ROAD I
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-578-3344
FAX: 886-3-579-2838
GERMANY
(CONTINENTAL
EUROPE & ISRAEL )
71083 HERRENBERG
BENZSTR. 32
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
IRELAND & UK
BLOCK A UNIT 2
BROOMFIELD BUSINESS PARK
MALAHIDE
CO. DUBLIN, IRELAND
PHONE: +353 1 8038020
FAX: +353 1 8038049
SINGAPORE
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231809
FAX: 65-3237013
U.S. SALES OFFICES
NORTHWESTERN
SOUTHWESTERN
CENTRAL & SOUTHEASTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
SUITE 200
5150 E. PACIFIC COAST HWY.
LONG BEACH, CA 90804
PHONE: 562-498-3314
FAX: 562-597-2174
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 972-690-1402
FAX: 972-690-0341
NORTHEASTERN
SUITE 436
20 TRAFALGAR SQUARE
NASHUA, NH 03063
PHONE: 603-889-4393
FAX: 603-889-9347
© Copyright 1998, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
12/98
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461