MOSEL VITELIC PRELIMINARY V53C806H HIGH PERFORMANCE 1M x 8 BIT FAST PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE 40 45 50 60 Max. RAS Access Time, (tRAC) 40 ns 45 ns 50 ns 60 ns Max. Column Address Access Time, (tCAA) 20 ns 22 ns 24 ns 30 ns Min. Fast Page Mode Cycle Time, (tPC) 23 ns 25 ns 28 ns 40 ns Min. Read/Write Cycle Time, (tRC) 75 ns 80 ns 90 ns 120 ns Features Description ■ 1M x 8-bit organization ■ Fast Page Mode for a sustained data rate of 43 MHz ■ RAS access time: 40, 45, 50, 60 ns ■ Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh capability ■ Refresh Interval: 1024 cycle/16 ms ■ Available in 28-pin 400 mil SOJ package ■ Single +5V ±10% Power Supply ■ TTL Interface The V53C806H is a ultra high speed 1,048,576 x 8 bit CMOS dynamic random access memory. The V53C806H offers a combination of features: Fast Page Mode for high data bandwidth, and Low CMOS standby current. All inputs and outputs are TTL compatible. Input and output capacitances are significantly lowered to allow increased system performance. Fast Page Mode operation allows random access of up to 1024 x 8 bits within a row with cycle times as fast as 23 ns. Because of static circuitry, the CAS clock is not in the critical timing path. The flow-through column address latches allow address pipelining while relaxing many critical system timing requirements. The V53C806H is ideally suited for graphics, digital signal processing and high-performance computing systems. Device Usage Chart Operating Temperature Range Package Outline K 40 45 50 60 Std. Temperature Mark 0°C to 70 °C • • • • • • Blank V53C806H Rev. 1.6 April 1998 Access Time (ns) 1 Power V53C806H MOSEL VITELIC V 5 3 C 8 FAMILY 0 6 H DEVICE PKG SPEED ( t RAC) K (SOJ) TEMP. PWR. BLANK (0¡C to 70¡C) BLANK (NORMAL) Description SOJ Pkg. Pin Count K 28 40 45 50 60 28-Pin SOJ PIN CONFIGURATION Top View VCC IO1 IO2 IO3 IO4 WE RAS 1 28 2 27 3 26 4 25 5 24 6 23 7 22 NC NC A0 A1 A2 A3 V CC 8 21 9 20 10 19 11 18 12 17 13 16 14 15 (40 ns) (45 ns) (50 ns) (60 ns) 808H-01 Pin Names V SS IO8 IO7 IO6 IO5 CAS OE A9 A8 A7 A6 A5 A4 VSS A0–A9 Address Inputs RAS Row Address Strobe CAS Column Address Strobe WE Write Enable OE Output Enable I/O1–I/O8 Data Input, Output VCC +5V Supply VSS 0V Supply NC No Connect 806H-02 Absolute Maximum Ratings* Capacitance* TA = 25°C, VCC = 5 V ± 10%, f = 1 MHz Ambient Temperature Under Bias..................................–10°C to +80°C Storage Temperature (plastic)......–55°C to +125°C Voltage Relative to VSS .................–1.0 V to +7.0 V Data Output Current ..................................... 50 mA Power Dissipation.......................................... 1.4 W *Note: Operation above Absolute Maximum Ratings can adversely affect device reliability. V53C806H Rev. 1.6 April 1998 Symbol Parameter Typ. Max. CIN1 Address Input 3 4 pF CIN2 RAS, CAS, WE, OE 4 5 pF COUT Data Input/Output 5 7 pF * Note: Capacitance is sampled and not 100% tested 2 Unit V53C806H MOSEL VITELIC Block Diagram 1M x 8 OE WE CAS RAS RAS CLOCK GENERATOR CAS CLOCK GENERATOR WE CLOCK GENERATOR OE CLOCK GENERATOR VCC VSS Y0 -Y9 DATA I/O BUS I/O1 COLUMN DECODERS I/O2 I/O3 I/O BUFFER SENSE AMPLIFIERS REFRESH COUNTER I/O7 I/O8 1024 x 8 • • • A8 A9 V53C806H Rev. 1.6 April 1998 X 0 -X9 ROW DECODERS A1 ADDRESS BUFFERS AND PREDECODERS 10 A0 1024 MEMORY ARRAY 1024 x 1024 x 8 806H-03 3 I/O4 I/O5 I/O6 V53C806H MOSEL VITELIC DC and Operating Characteristics TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, unless otherwise specified. Symbol Parameter ILI Input Leakage Current (any input pin) ILO Output Leakage Current (for High-Z State) ICC1 VCC Supply Current, Operating ICC2 VCC Supply Current, TTL Standby ICC3 VCC Supply Current, RAS-Only Refresh ICC4 VCC Supply Current, Fast Page Mode Operation Access Time V53C806H Min. Typ. Max. Unit Test Conditions Notes –10 10 mA VSS £ VIN £ VCC –10 10 mA VSS £ VOUT £ VCC RAS, CAS at VIH 40 220 mA tRC = tRC (min.) 45 210 50 200 60 190 4 mA RAS, CAS at VIH other inputs ³ VSS 40 220 mA tRC = tRC (min.) 2 45 210 50 200 60 190 40 110 mA Minimum cycle 1, 2 45 100 50 90 60 80 1, 2 ICC5 VCC Supply Current, Standby, Output Enabled 2.0 mA RAS = VIH, CAS = VIL other inputs ³ VSS ICC6 VCC Supply Current, CMOS Standby 2.0 mA RAS ³ VCC – 0.2 V, CAS ³ VCC– 0.2 V, All other inputs ³ VSS VCC Supply Voltage 4.5 5.5 V VIL Input Low Voltage –1 0.8 V 3 VIH Input High Voltage 2.4 VCC + 1 V 3 VOL Output Low Voltage 0.4 V IOL = 4.2 mA VOH Output High Voltage V IOH = –5 mA V53C806H Rev. 1.6 April 1998 5.0 2.4 4 1 V53C806H MOSEL VITELIC AC Characteristics TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V 40 # Symbol Parameter 1 tRAS 2 45 50 60 Min. Max. Min. Max. Min. Max. Min. Max. Unit RAS Pulse Width 40 75K 45 75K 50 75K 60 75K ns tRC Read or Write Cycle Time 75 80 90 110 ns 3 tRP RAS Precharge Time 25 25 30 40 ns 4 tCSH CAS Hold Time 40 45 50 60 ns 5 tCAS CAS Pulse Width 12 13 14 15 ns 6 tRCD RAS to CAS Delay 17 7 tRCS Read Command Setup Time 0 0 0 0 ns 8 tASR Row Address Setup Time 0 0 0 0 ns 9 tRAH Row Address Hold Time 7 8 9 10 ns 10 tASC Column Address Setup Time 0 0 0 0 ns 11 tCAH Column Address Hold Time 5 6 7 10 ns 12 tRSH (R) RAS Hold Time (Read Cycle) 12 13 14 15 ns 13 tCRP CAS to RAS Precharge Time 5 5 5 5 ns 14 tRCH Read Command Hold Time Referenced to CAS 0 0 0 0 ns 5 15 tRRH Read Command Hold Time Referenced to RAS 0 0 0 0 ns 5 16 tROH RAS Hold Time Referenced to OE 8 9 10 10 ns 17 tOAC Access Time from OE 12 13 14 17 ns 18 tCAC Access Time from CAS 12 13 14 17 ns 6, 7 19 tRAC Access Time from RAS 40 45 50 60 ns 6, 8, 9 20 tCAA Access Time from Column Address 20 22 24 30 ns 6, 7, 10 21 tLZ CAS to Low-Z Output 0 ns 16 22 tHZ Output buffer turn-off delay time 0 ns 16 23 tAR Column Address Hold Time from RAS 30 24 tRAD RAS to Column Address 12 28 18 32 0 6 0 13 36 0 7 35 20 19 0 14 43 0 8 40 23 20 0 10 45 26 15 Notes ns 4 ns 30 ns 11 Delay Time 25 tRSH (W) RAS or CAS Hold Time in Write Cycle 12 13 14 15 ns 26 tCWL Write Command to CAS Lead Time 12 13 14 15 ns 27 tWCS Write Command Setup Time 0 0 0 0 ns 28 tWCH Write Command Hold Time 5 6 7 10 ns 29 tWP Write Pulse Width 5 6 7 10 ns V53C806H Rev. 1.6 April 1998 5 12, 13 V53C806H MOSEL VITELIC AC Characteristics (Cont’d) 40 Max. Min. 50 Symbol Parameter 30 tWCR Write Command Hold Time from RAS 30 35 40 45 ns 31 tRWL Write Command to RAS Lead Time 12 13 14 15 ns 32 tDS Data in Setup Time 0 0 0 0 ns 14 33 tDH Data in Hold Time 5 6 7 10 ns 14 34 tWOH Write to OE Hold Time 6 7 8 10 ns 14 35 tOED OE to Data Delay Time 6 7 8 10 ns 14 36 tRWC Read-Modify-Write Cycle Time 110 115 130 170 ns 37 tRRW Read-Modify-Write Cycle RAS Pulse Width 75 80 87 105 ns 38 tCWD CAS to WE Delay 30 32 34 40 ns 12 39 tRWD RAS to WE Delay in Read-ModifyWrite Cycle 58 62 68 85 ns 12 40 tCRW CAS Pulse Width (RMW) 48 50 52 65 ns 41 tAWD Col. Address to WE Delay 38 41 42 58 ns 42 tPC Fast Page Mode Read or Write Cycle Time 23 25 28 40 ns 43 tCP CAS Precharge Time 5 6 7 8 ns 44 tCAR Column Address to RAS Setup Time 20 22 24 30 ns 45 tCAP Access Time from Column Precharge 46 tDHR Data in Hold Time Referenced to RAS 30 35 40 50 ns 47 tCSR CAS Setup Time CAS-before-RAS Refresh 10 10 10 10 ns 48 tRPC RAS to CAS Precharge Time 0 0 0 0 ns 49 tCHR CAS Hold Time CAS-before-RAS Refresh 8 10 12 15 ns 50 tPCM Fast Page Mode Read-Modify-Write Cycle Time 60 65 70 85 ns 51 tT Transition Time (Rise and Fall) 3 52 tREF Refresh Interval (1024 Cycles) 23 50 16 6 Max. Min. 60 # V53C806H Rev. 1.6 April 1998 Min. 45 25 3 50 16 Max. Min. 27 3 50 16 Max. 34 3 Unit ns 50 ns 16 ms Notes 12 7 15 V53C806H MOSEL VITELIC Notes: 1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two transitions per address cycle in Fast Page Mode. 3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) ³ VSS and VIH (max.) £ VCC. 4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. 5. Either tRRH or tRCH must be satisified for a Read Cycle to occur. 6. Measured with a load equivalent to two TTL inputs and 50 pF. 7. Access time is determined by the longest of tCAA, tCAC and tCAP. 8. Assumes that tRAD £ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). 9. Assumes that tRCD £ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds tRCD (max.). 10. Assumes that tRAD ³ tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns . 16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent). 17. An initial 200 ms pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval. V53C806H Rev. 1.6 April 1998 7 V53C806H MOSEL VITELIC Waveforms of Read Cycle RAS t RAS (1) t AR (23) VIH t RC (2) t RP (3) VIL t CRP (13) CAS t RSH (R)(12) t CAS (5) VIH VIL t RAH (9) VIH ROW ADDRESS VIL t CAH (11) t ASC (10) COLUMN ADDRESS t RCH (14) t CAR (44) t RCS (7) WE t CRP (13) t RAD (24) t ASR (8) ADDRESS t CSH (4) t RCD (6) t RRH (15) VIH VIL t ROH (16) t HZ (22) t CAA (20) OE t OAC (17) VIH VIL t CAC (18) t RAC (19) I/O t HZ (22) t HZ (22) VOH VALID DATA-OUT VOL t LZ (21) 806H-04 Waveforms of Early Write Cycle RAS t AR (23) V IH t CSH (4) t RCD (6) t RAH (9) V IH V IL ROW ADDRESS t ASC (10) t CWL (26) t WCH (28) t WP (29) t WCS (27) V IH V IL t RWL (31) V IH V IL t DS (32) I/O t CAR (44) t CAH (11) COLUMN ADDRESS t WCR (30) OE t CRP (13) V IL t RAD (24) WE t RSH (W)(25) t CAS (5) V IH t ASR (8) ADDRESS t RP (3) V IL t CRP (13) CAS t RC (2) t RAS (1) V IH V IL t DHR (46) t DH (33) VALID DATA-IN HIGH-Z 806H-05 Don’t Care V53C806H Rev. 1.6 April 1998 8 Undefined V53C806H MOSEL VITELIC Waveforms of OE-Controlled Write Cycle RAS t AR (23) V IH t CSH (4) t RCD (6) t RSH (W)(12) t CAS (5) V IH t CRP (13) V IL t RAD (24) t RAH (9) t ASR (8) ADDRESS t RP (3) V IL t CRP (13) CAS t RC (2) t RAS (1) V IH ROW ADDRESS V IL t CAR (44) t CAH (11) t ASC (10) COLUMN ADDRESS t CWL (26) t RWL (31) t WP (29) WE V IH V IL t WOH (34) OE V IH V IL t OED (35) I/O t DH (33) t DS (32) V IH VALID DATA-IN V IL 806H-06 Waveforms of Read-Modify-Write Cycle RAS t AR (23) VIH t CSH (4) t RCD (6) t t ASC (10) VIH VIL ROW ADDRESS CAH (11) COLUMN ADDRESS t AWD (41) t CWD (38) t RAD (24) OE t CRP (13) VIL t RAH (9) WE t RP (3) t RSH (W)(25) t CRW (40) VIH t ASR (8) ADDRESS t RWC (36) VIL t CRP (13) CAS tRRW (37) t RWL (31) t RWD (39) t RCS (17) t WP (29) VIH VIL t CAA (20) t OAC (17) VIH VIL t OED (35) t CAC (18) t RAC (19) I/O t CWL (26) t HZ (22) VIH VOH VALID DATA-OUT VIL VOL t DH (33) t DS (32) VALID DATA-IN t LZ (21) 806H-07 Don’t Care V53C806H Rev. 1.6 April 1998 9 Undefined V53C806H MOSEL VITELIC Waveforms of Fast Page Mode Read Cycle RAS tPC (42) tCP(43) tCSH (4) t RAH (9) tCAR (44) tASC (10) t CAH (11) tASC (10) VIH ROW ADDRESS COLUMN ADDRESS t CAH (11) COLUMN ADDRESS COLUMN ADDRESS t RCH (14) t CAH (11) t RCS (7) t RCS (7) t RCS (7) V IL tCAA (20) t CAA (20) t CAP (45) t OAC (17) tRRH (15) t OAC (17) VIH V IL tHZ (22) tRAC (19) tCAC (18) t LZ (21) t CAC (18) t CAC (18) t HZ (22) VOH tHZ (22) tHZ (22) VALID DATA OUT VOL tHZ (22) tHZ (22) t LZ (21) t LZ (21) I/O tRCH (14) VIH t OAC (17) OE t CRP (13) t CAS (5) tCAS (5) V IL V IL WE tRSH (R)(12) t CAS (5) VIH tASR (8) ADDRESS RP (3) V IL t RCD (6) tCRP (13) CAS t t RAS (1) tAR (23) VIH VALID DATA OUT VALID DATA OUT 806H-08 Waveforms of Fast Page Mode Write Cycle tRP (3) tAR (23) RAS t RAS (1) V IH V IL t CRP (13) tRCD (6) CAS tRSH (W)(25) t PC (42) t CP(43) t CAS (5) V IH tCRP (13) tCAS (5) tCAS (5) V IL tCSH (4) tRAH (9) tCAR (44) tASR (8) V IH ADDRESS ROW ADD V IL tASC (10) tCAH (11) tASC (10) tCAH (11) COLUMN ADDRESS tRAD (24) COLUMN ADDRESS t CWL (26) tWCS (27) tCWL (26) t WCS (27) tRWL(31) t WCH (28) t WCH (28) t WP(29) t WP (29) WE COLUMN ADDRESS t CWL (26) tWCS (27) t WCH (28) t CAH (11) tWP(29) V IH V IL OE VIH V IL I/O V IH V IL tDS (32) tDH (33) tDS (32) tDH (33) t DS (32) VALID DATA IN OPEN VALID DATA IN tDH (33) VALID DATA IN OPEN 806H-09 Don’t Care V53C806H Rev. 1.6 April 1998 10 Undefined V53C806H MOSEL VITELIC Waveforms of Fast Page Mode Read-Write Cycle RAS t RASP (37) VIH V IL t CSH (4) t RCD (6) t PCM (50) IH V t RSH (W)(25) t CRP (13) t CAS (5) t CP (43) t CAS (5) V CAS t RP (3) t CAS (5) t RAD (24) IL t RAH (9) t ASC (10) t ASR (8) V ADDRESS IH ROW ADD V IL t ASC (10) t CAH (11) t CAH (11) COLUMN ADDRESS t CAH (11) COLUMN ADDRESS t RWD (39) t RCS (7) t CAR (44) t ASC (10) t CWL (26) t CWD (38) COLUMN ADDRESS t CWD (38) t CWD (38) t RWL (31) t CWL (26) t CWL (26) V WE IH V IL t CAA (20) t OAC (17) t AWD (41) t AWD (41) t AWD (41) t WP (29) t WP (29) t WP (29) t OAC (17) t OAC (17) V OE IH V IL t CAA (20) t OED (35) t CAP (43) t CAP (43) t CAA (20) t OED (35) t CAC (18) t CAC (18) t RAC (19) t HZ (22) t HZ (22) t DH (33) t DH (33) t DS (32) t DS (32) I/O V I/OH OUT V I/OL OUT IN t LZ (21) t LZ (21) t OED (35) t CAC (18) t HZ (22) t DH (33) t DS (32) OUT IN IN 806H-10 t LZ (21) Waveforms of RAS-Only Refresh Cycle t RC (2) RAS t RAS (1) V IH t RP (3) V IL t CRP (13) CAS V IH V IL t ASR (8) ADDRESS V IH t RAH (9) ROWADDR V IL 806H-11 NOTE: WE, OE = Don’t care Don’t Care V53C806H Rev. 1.6 April 1998 11 Undefined V53C806H MOSEL VITELIC Waveforms of CAS-before-RAS Refresh Counter Test Cycle t RAS (1) t RP (3) V IH RAS V IL t CSR (47) t CHR (49) t RSH (W)(25) t CAS (5) t CP (43) V IH CAS V IL V IH ADDRESS V IL READ CYCLE t RRH (15) t RCH (14) t RCS (7) V IH WE V IL t ROH (16) t OAC (17) V IH OE V IL t HZ (22) t HZ (22) t LZ (21) V IH I/O DOUT V IL t RWL (31) t CWL (26) WRITE CYCLE t HZ (22) t WCH (28) t WCS (27) V IH WE V IL V IH OE V IL t DH (33) t DS (32) V IH I/O D IN V IL 806H-12 Waveforms of CAS-before-RAS Refresh Cycle t RC (2) t RP (3) RAS V IL t CP (43) CAS t RAS (1) t RP (3) V IH t RPC (48) t CSR (47) t CHR (49) V IH V IL t HZ (22) I/O V OH V OL 806H-13 NOTE: WE, OE, A 0 –A 9 = Don’t care Don’t Care V53C806H Rev. 1.6 April 1998 12 Undefined V53C806H MOSEL VITELIC Waveforms of Hidden Refresh Cycle (Read) t RC (2) RAS V IH t RC (2) tRP (3) t RAS (1) t AR (23) t RAS (1) t RP (3) V IL t RCD (6) t CRP (13) CAS t CRP (13) V IL V IH t RAD (24) t ASC (10) t CAH (11) COLUMN ADDRESS ROW ADD V IL t RCS (7) WE t CHR (49) V IH t ASR (8) t RAH (9) ADDRESS t RSH (R)(12) t RRH (15) V IH V IL t CAA (20) OE t HZ (22) t OAC (17) V IH V IL t CAC (18) t LZ (21) t RAC (19) I/O t HZ (22) V OH t HZ (22) VALID DATA V OL 806H-14 Waveforms of Hidden Refresh Cycle (Write) t RC (2) RAS V IH t RC (2) t RAS (1) t RP (3) V IL t RCD (6) t CRP (13) CAS t RP (3) t RAS (1) t AR (23) t RSH (12) t CHR (49) t CRP (13) V IH V IL t RAD (24) t ASC (10) t ASR (8) t RAH (9) ADDRESS V IH V IL ROW ADD COLUMN ADDRESS t WCH (28) t WCS (27) WE t CAH (11) V IH V IL V IH OE V IL t DS (32) I/O V IH V IL t DH (33) VALID DATA-IN t DHR (46) 806H-15 Don’t Care V53C806H Rev. 1.6 April 1998 13 Undefined V53C806H MOSEL VITELIC Functional Description Fast Page Mode Operation The V53C806H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C806H reads and writes data by multiplexing an 20-bit address into a 10-bit row and a 10-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address “flows through” an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time. Fast Page Mode operation permits all 1024 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer and acts as an output enable. During Fast Page Mode operation, Read, Write, Read-Modify-Write or ReadWrite-Read cycles are possible at random addresses within a row. Following the initial entry cycle into Fast Page Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA. In both cases, the falling edge of CAS latches the address and enables the output. Fast Page Mode provides a sustained data rate of 43 MHz for applications that require high data rates such as bit-mapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: Memory Cycle A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP/tCP has elapsed. Read Cycle A Read cycle is performed by holding the Write Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC, tRAC, tCAA and tCAC are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied. 1024 Data Rate = -------------------------------------------t RC + 1023 ´ t PC Write Cycle Data Output Operation A Write Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied. The V53C806H Input/Output is controlled by OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition enables the internal I/O path. A CAS high transition or RAS high transition, whichever occurs later, disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The OE signal V53C806H Rev. 1.6 April 1998 14 V53C806H MOSEL VITELIC Power-On has no effect on any data stored in the output latches. A WE low level can also disable the output drivers. During a Write cycle, if WE goes low at a time when the CAS is low, it is necessary to use OE to disable the output drivers prior to the WE low transition to allow Data In Setup Time (tDS) to be satisfied. To retain data, 1024 Refresh Cycles are required in each 16 ms period. There are two ways to refresh the memory: After application of the VCC supply, an initial pause of 200 ms is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the VCC current requirement of the V53C806H is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and ICC will exhibit current transients. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges. 1. By clocking each of the 1024 row addresses (A0 through A9) with RAS at least once every 16 ms. Any Read, Write, Read-Modify-Write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS Refresh Cycle. If CAS makes a transition from low to high to low after the previous cycle and before RAS falls, CAS-before-RAS refresh is activated. The V53C806H uses the output of an internal 10-bit counter as the source of row addresses and ignore external address inputs. Table 1. V53C806H Data Output Operation for Various Cycle Types CAS-before-RAS is a “refresh-only” mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. A CAS-before-RAS counter test mode is provided to ensure reliable operation of the internal refresh counter. Data Retention Mode The V53C806H offers a CMOS standby mode that is entered by causing the RAS clock to swing between a valid VIL and an “extra high” VIH within 0.2 V of VCC. While the RAS clock is at the extra high level, the V53C806H power consumption is reduced to the low ICC6 level. Overall ICC consumption when operating in this mode can be calculated as follows: ( t RC ) ´ ( I CC1 ) + ( t RX – t RC ) ´ ( I CC6 ) I = -----------------------------------------------------------------------------------------------t RX Where: tRC = Refresh Cycle Time tRX = Refresh Interval/1024 V53C806H Rev. 1.6 April 1998 15 Cycle Type I/O State Read Cycles Data from Addressed Memory Cell CAS-Controlled Write Cycle (Early Write) High-Z WE-Controlled Write Cycle (Late Write) OE Controlled. High OE = High-Z I/Os Read-Modify-Write Cycles Data from Addressed Memory Cell Fast Page Mode Read Data from Addressed Memory Cell Fast Page Mode Write Cycle (Early Write) High-Z Fast Read-Modify-Write Cycle Data from Addressed Memory Cell RAS-only Refresh High-Z CAS-before-RAS Refresh Cycle Data remains as in previous cycles CAS-only Cycles High-Z V53C806H MOSEL VITELIC Package Diagrams 28-Pin Plastic SOJ Unit in inches [mm] 1 14 +0.007 0.138 –0.006 0.028 +0.102 +0.004 0.711 –0.051 –0.002 3.51 0.043 MAX [1.09 MAX] 0.004 [0.102] 0.05 bsc [1.27 bsc] V53C806H Rev. 1.6 April 1998 0.015/0.020 [0.38/0.51] 0.025 MIN [.635 MIN] 16 +0.178 –0.154 0.370 ± 0.010 [9.40 ± 0.26] 15 0.400 ± 0.005 [10.16 ± .0.13] 28 0.440 ±0.005 [11.18 ± 0.12] 0.725 ± 0.005 [18.42 ± 0.12] V53C806H MOSEL VITELIC V53C806H Rev. 1.6 April 1998 17 MOSEL VITELIC WORLDWIDE OFFICES V53C806H U.S.A. TAIWAN JAPAN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 81-43-299-6000 FAX: 81-43-299-6555 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 852-2665-4883 FAX: 852-2664-7535 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-578-3344 FAX: 886-3-579-2838 GERMANY (CONTINENTAL EUROPE & ISRAEL ) 71083 HERRENBERG BENZSTR. 32 GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 IRELAND & UK BLOCK A UNIT 2 BROOMFIELD BUSINESS PARK MALAHIDE CO. DUBLIN, IRELAND PHONE: +353 1 8038020 FAX: +353 1 8038049 U.S. SALES OFFICES NORTHWESTERN SOUTHWESTERN CENTRAL & SOUTHEASTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 SUITE 200 5150 E. PACIFIC COAST HWY. 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