TI TLC5617AID

TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
D
D
D
D
D
D
D
D
D
D
Programmable Settling Time to 0.5 LSB
2.5 µs or 12.5 µs Typ
Two 10-Bit CMOS Voltage Output DACs in
an 8 Pin Package
Simultaneous Updates for DAC A
and DAC B
Single Supply Operation
3-Wire Serial Interface
High-Impedance Reference Inputs
Voltage Output Range . . . 2 Times the
Reference Input Voltage
Software Power Down Mode
Internal Power-On Reset
TMS320 and SPI Compatible
D
D
D
Low Power Consumption:
– 3 mW Typ in Slow Mode
– 8 mW Typ in Fast Mode
Input Data Update Rate of 1.21 MHz
Monotonic Over Temperature
applications
D
D
D
D
D
Battery Powered Test Instruments
Digital Offset and Gain Adjustment
Battery Operated/Remote Industrial
Controls
Machine and Motion Control Devices
Cellular Telephones
D PACKAGE
(TOP VIEW)
The TLC5617 and TLC5617A are dual 10-bit
voltage output digital-to-analog converters (DAC)
with buffered reference inputs (high impedance).
The DACs have an output voltage range that is
two times the reference voltage, and the DACs are
monotonic. The devices are simple to use,
running from a single supply of 5 V. A power-on
reset function is incorporated to ensure repeatable start-up conditions.
DIN
SCLK
CS
OUT A
1
8
2
7
3
6
4
5
VDD
OUT B
REFIN
AGND
Digital control of the TLC5617 is over a 3-wire CMOS compatible serial bus. The device receives a 16-bit word
for programming and producing the analog output. The digital inputs feature Schmitt triggers for high noise
immunity. Digital communication protocols include the SPI, QSPI, and Microwire standards.
Two versions of this device are available. The TLC5617 does not have any internal state machine and is
dependent on all external timing signals. The TLC5617A has an internal state machine that will count the
number of clocks from the falling edge of CS and then updates and disables the device from accepting further
data inputs. The TLC5617A is recommended for TMS320 and SPI processors and the TLC5617 is
recommended only for use in SPI or 3-wire serial port processors. The TLC5617A is backward compatible and
designed to work in TLC5617 designed systems.
The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications.
The TLC5617C is characterized for operation from 0°C to 70°C. The TLC5617I is characterized for operation
from – 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE†
(D)
0°C to 70°C
TLC5617CD
TLC5617ACD
– 40°C to 85°C
TLC5617ID
TLC5617AID
† Available in tape and reel as the TLC5617CDR
and the TLC5617IDR
DEVICE
COMPATIBILITY
TLC5617
SPI, QSPI, and Microwire
TLC5617A
TMS320Cxx, SPI, QSPI, and Microwire
functional block diagram
6
REFIN
AGND
_
DAC A
+
DAC
+
_
7
×2
5
Power-Up
Reset
R
OUT A
(Voltage Output)
R
10-Bit DAC Register Latch A
CS
SCLK
DIN
3
Control
Logic
(LSB)
2
1
(MSB)
12 Data Bits
4
Program
Bits
16-Bit Shift Register
Double
Buffer
Latch
10-Bit DAC Register Latch B
_
+
DAC
DACB
R
2
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4
+
_
×2
R
OUT B
(Voltage Output)
TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
5
Analog ground
CS
3
I
Chip select, active low
DIN
1
I
Serial data input
OUT A
4
O
DAC A analog output
OUT B
7
O
DAC B analog output
REFIN
6
I
Reference voltage input
SCLK
2
I
Serial clock input
VDD
8
Positive power supply
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Digital input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V
Reference input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V
Output voltage at OUT from external source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V
Continuous current at any terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Operating free-air temperature range, TA: TLC5617C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLC5617I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Supply voltage, VDD
High-level digital input voltage, VIH
Low-level digital input voltage, VIL
VDD = 5 V
VDD = 5 V
MIN
NOM
MAX
4.5
5
5.5
0.7 VDD
1
Load resistance, RL
2
Operating free-air
free air temperature,
temperature TA
TLC5617C
TLC5617I
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V
V
0.3 VDD
Reference voltage, Vref to REFIN terminal
UNIT
2.048 VDD – 1.1
V
V
kΩ
0
70
°C
– 40
85
°C
3
TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%,
Vref (REFIN)= 2.048 V (unless otherwise noted)
static DAC specifications
PARAMETER
TEST CONDITIONS
MIN
Resolution
Differential nonlinearity (DNL)
Zero-scale error (offset error at zero scale)
Zero-scale-error temperature coefficient
EG
Gain error
Gain error temperature coefficient
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
See Note 1
Power-supply
Power-su
ly rejection ratio
UNIT
±1
LSB
± 0.5
LSB
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
See Note 3
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
See Note 5
±3
See Note 4
3
LSB
ppm/°C
±3
See Note 6
1
LSB
ppm/°C
80
Slow
Gain
bits
± 0.1
See Note 2
Zero scale
PSRR
MAX
10
Integral nonlinearity (INL), end point adjusted
EZS
TYP
80
See Notes 7 and 8
Zero scale
dB
80
Fast
Gain
80
NOTES: 1. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
2. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal
1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin).
5. Gain error is the deviation from the ideal output (Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
6. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin).
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.
8. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change.
OUT A and OUT B output specifications
PARAMETER
VO
TEST CONDITIONS
Voltage output
RL = 10 kΩ
Output load regulation accuracy
VO(OUT) = 2V,
RL from 10 kΩ to 2 kΩ
VO(OUT A) or VO(OUT B) to VDD or AGND
IOSC
Output short circuit current
IO(sink)
IO(source)
Output sink current
Output source current
MIN
TYP
0
VO(OUT) > 0.25 V
VO(OUT) < 4.75 V
MAX
UNIT
VDD –0.4
0.5
V
LSB
20
mA
5
mA
5
mA
reference input (REFIN)
PARAMETER
VI
Ri
Input voltage
Ci
Input capacitance
TEST CONDITIONS
MIN
TYP
0
Input resistance
MAX
VDD – 2
10
UNIT
V
MΩ
5
pF
dB
Reference feedthrough
REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9)
– 80
Reference input
in ut bandwidth (f–3dB)
REFIN = 0.2
0 2 Vpp + 1.024
1 024 V dc
Slow
0.5
Fast
1
MHz
NOTE 9: Reference feedthrough is measured at the DAC output with an input code = 00 hex and a Vref(REFIN) input = 1.024 V dc + 1 Vpp
at 1 kHz.
4
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TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%,
Vref (REFIN)= 2.048 V (unless otherwise noted) (continued)
digital inputs (DIN, SCLK, CS)
PARAMETER
IIH
IIL
High-level digital input current
Ci
Input capacitance
TEST CONDITIONS
MIN
TYP
VI = VDD
VI = 0 V
Low-level digital input current
MAX
UNIT
±1
µA
±1
µA
8
pF
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.5
5
5.5
Slow
0.6
1
Fast
1.6
2.5
Supply voltage, VDD
IDD
VDD = 5.5 V,
No load
load,
All inputs = 0 V or VDD
Power supply current
Power down supply current
UNIT
V
mA
D13 = 0 (see Table 3)
µA
1
operating characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%,
Vref(REFIN) = 2.048 V (unless otherwise noted)
analog output dynamic performance
PARAMETER
SR
Output slew rate
TEST CONDITIONS
CL = 100 pF,
RL = 10 kΩ,
kΩ
Code 32 to Code 1024,
Vref(REFIN) = 2.048 V,
TA = 25°C
25°C,
VO from 10% to 90%
MIN
TYP
Slow
0.3
0.5
Fast
2.4
3
UNIT
V/µs
ts
Output settling time
To ± 0.5 LSB,,
RL = 10 kΩ,
CL = 100 pF,
See Note 10
Slow
12.5
Fast
2.5
ts(c)
( )
Output settling
g time,, code
to code
To ± 0.5 LSB,,
RL = 10 kΩ,
CL = 100 pF,
See Note 11
Slow
2
Fast
2
Glitch energy
DIN = All 0s to all 1s,
f(SCLK) = 100 kHz
CS = VDD,
Signal to noise + distortion
Vref(REFIN)
(
) = 1 Vpp at 1 kHz and 10 kHz + 1.024 V dc,
Input code = 10 0000 0000
S/(N+D)
MAX
µs
µs
5
Slow
78
Fast
81
nV–s
dB
NOTES: 10. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
11. Setting time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count.
digital input timing requirements
MIN
NOM
MAX
UNIT
tsu(DS)
th(DH)
Setup time, DIN before SCLK low
5
ns
Hold time, DIN valid after SCLK low
5
ns
tsu(CSS)
tsu(CS1)
Setup time, CS low to SCLK low
tsu(CS2)
tw(CL)
Setup time, SCLK ↑ to CS ↓, start of next write cycle
tw(CH)
5
ns
10
ns
5
ns
Pulse duration, SCLK low
25
ns
Pulse duration, SCLK high
25
ns
Setup time, SCLK ↑ to CS ↑, external end-of-write
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TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
CS
tsu(CSS)
tsu(CS1)
tw(CL)
tw(CH)
tsu(CS2)
SCLK
(see Note A)
ÎÎÎ
ÎÎÎ
tsu(DS)
DIN
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÏÏÏÏ
ÏÏ
ÏÏÏÏ ÏÏ
th(DH)
D15
D14
D13
D12
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
D11
DAC Data
Bits (12)
Program Bits (4)
DAC OUT
A/B
D0
ts
≤ Final Value ±0.5 LSB
NOTE A: SCLK must go high after the 16th falling clock edge.
Figure 1. Timing Diagram for the TLC5617A
PARAMETER MEASUREMENT INFORMATION
OUTPUT SINK CURRENT (FAST MODE)
vs
OUTPUT LOAD VOLTAGE
OUTPUT SOURCE CURRENT (FAST MODE)
vs
OUTPUT LOAD VOLTAGE
40
–60
VDD = 5 V,
Input Code = 4095
35
Output Source Current – mA
Output Sink Current – mA
–50
30
25
20
15
10
5
–5
0
0.5
1
1.5
2
2.5
3
3.5
4
–30
–20
–10
VCC = 5 V,
Input Code = 0
0
–40
4.5
0
0
0.5
Output Load Voltage – V
1.5
2
2.5
Figure 3
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3
3.5
Output Load Voltage – V
Figure 2
6
1
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4
4.5
TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
OUTPUT SOURCE CURRENT (SLOW MODE)
vs
OUTPUT LOAD VOLTAGE
25
–30
20
–25
Output Source Current – mA
Output Sink Current – mA
OUTPUT SINK CURRENT (SLOW MODE)
vs
OUTPUT LOAD VOLTAGE
15
10
5
0
–20
–15
–10
–5
VDD = 5 V,
Input Code = 0
–0
0
0.5
1
1.5
2
2.5
3
3.5
4
VDD = 5 V,
Input Code = 4095
0
4.5
0
0.5
Output Load Voltage – V
2
2.5
3
3.5
4
4.5
Figure 5
SUPPLY CURRENT
vs
TEMPERATURE
RELATIVE GAIN (FAST MODE)
vs
FREQUENCY
5
1.4
VDD = 5 V,
VREFIN = 2.048 V,
TA = 25°C
0
Fast Mode
1
–5
Relative Gain – dB
Supply Current – mA
1.5
Output Load Voltage – V
Figure 4
1.2
1
0.8
0.6
0.4
–15
–20
Slow Mode
–25
0.2
0
– 60 – 40 – 20
–10
0
20 40 60 80
Temperature – °C
100 120 140
VCC = 5 V,
VREFIN = 0.2 VPP + 2.048 Vdc,
TA = 25°C
–30
100
1000
10 K
f – Frequency – kHz
Figure 6
Figure 7
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TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
RELATIVE GAIN (SLOW MODE)
vs
FREQUENCY
TOTAL HARMONIC DISTORTION (SLOW MODE)
vs
FREQUENCY
5
95
THD – Total Harmonic Distortion – dB
0
Relative Gain – dB
–5
–10
–15
–20
–25
–30
VCC = 5 V,
VREFIN = 0.2 VPP + 2.048 Vdc,
TA = 25°C
–35
–40
100
85
80
75
70
65
10 K
1000
90
1
10
f – Frequency – kHz
Figure 8
Figure 9
SIGNAL-TO-NOISE RATIO (SLOW MODE)
vs
FREQUENCY
85
85
SNR – Signal-To-Noise Ratio – dB
THD+N – Total Harmonic Distortion + Noise – dB
TOTAL HARMONIC DISTORTION + NOISE (SLOW MODE)
vs
FREQUENCY
80
75
70
65
60
1
100
10
80
75
70
65
1
f – Frequency– kHz
10
f – Frequency– kHz
Figure 10
8
100
f – Frequency – kHz
Figure 11
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100
TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION (FAST MODE)
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE (FAST MODE)
vs
FREQUENCY
THD+N – Total Harmonic Distortion + Noise – dB
90
85
80
75
1
100
10
85
80
75
70
65
1
10
f – Frequency – kHz
f – Frequency – kHz
Figure 12
Figure 13
100
SIGNAL-TO-NOISE RATIO (FAST MODE)
vs
FREQUENCY
85
SNR – Signal-To-Noise Ratio – dB
THD – Total Harmonic Distortion – dB
95
80
75
70
65
1
10
100
f – Frequency – kHz
Figure 14
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TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
DNL – Differential Nonlinearity – LSB
TYPICAL CHARACTERISTICS
0.2
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
0
255
511
767
1023
Input Code
INL – Integral Nonlinearity – LSB
Figure 15. Differential Nonlinearity With Input Code
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
255
511
767
Input Code
Figure 16. Integral Nonlinearity With Input Code
10
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1023
TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
APPLICATION INFORMATION
general function
The TLC5617 uses a resistor string network buffered with an op amp to convert 10-bit digital data to analog
voltage levels (see functional block diagram and Figure 17). The output of the TLC5617 is the same polarity
as the reference input (see Table 1).
ǒ
The output code is given by: 2 V
Ǔ
CODE
REFIN 1024
An internal circuit resets the DAC register to all 0s on power up.
+
_
REFIN
Resistor
String
DAC
DIN
CS
+
_
×2
OUT
R
SCLK
R
AGND
VDD
5V
0.1 µF
Figure 17. TLC5617 Typical Operating Circuit
Table 1. Binary Code Table (0 V to 2 VREFIN Output), Gain = 2
INPUT†
1111
1111
11(00)
:
1000
0000
01(00)
1000
0000
00(00)
0111
1111
11(00)
:
0000
0000
01(00)
0000
0000
00(00)
ǒ
ǒ
2 V
Ǔ
Ǔ
OUTPUT
1023
REFIN 1024
:
513
2 V
REFIN 1024
512
V
2 V
REFIN 1024
REFIN
ǒ
ǒ
2 V
ǒ
Ǔ
+
Ǔ
511
REFIN 1024
2 V
Ǔ
:
1
REFIN 1024
0V
† A 10-bit data word with two sub-LSB 0s must be written since the DAC input
latch is 12 bits wide.
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TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
APPLICATION INFORMATION
buffer amplifier
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-kΩ load with a 100-pF
load capacitance. Settling time is a software selectable 12.5 µs or 2.5 µs typical to within ±0.5 LSB of the final
value.
external reference
The reference voltage input is buffered which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10 MΩ and the REFIN input capacitance is typically 5 pF, independent of input
code. The reference voltage determines the DAC full-scale output.
logic interface
The logic inputs function with CMOS logic levels. Most of the standard high-speed CMOS logic families may
be used.
serial clock and update rate
Figure 1 shows the TLC5617 timing. The maximum serial clock rate is
f(SCLK)max
+t
1
+ 20 MHz
)
t ǒ Ǔ
w CL min
wǒCHǓmin
ǒ ǒ Ǔ ǒ ǓǓ
The digital update rate is limited by the chip-select period, which is
tp(CS)
+ 16
t
w CH
) tw CL ) tsuǒCS1Ǔ
This equals 820-ns or 1.21-MHz update rate. However, the DAC settling time to 10 bits limits the update rate
for full-scale input step transitions.
12
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TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
APPLICATION INFORMATION
serial interface
When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most
significant bit first. The falling edge of the SCLK input shifts the data into the input register.
The rising edge of CS then transfers the data to the DAC register. All CS transitions should occur when the SCLK
input is low.
The 16 bits of data can be transferred with the sequence shown in Figure 18.
16 Bits
Program Bits
D15
D14
Fill Bits†
Data Bits
D13
D12
D11
MSB (Input Word)
10 Data Bits
MSB (Data)
D2
D1 = x
LSB (Data)
D0 = x
LSB (Input Word)
† Two extra (sub-LSB) bits (can be don’t care)
Figure 18. Input Data Word Format
Table 2 shows the function of program bits D15 – D12.
Table 2. Program Bits D15 – D12 Function
PROGRAM BIT
DEVICE FUNCTION
D15
D14
D13
D12
1
X
X
X
Write to latch A with serial interface register
g
data
and latch B updated with buffer latch data
0
X
X
0
Write to latch B and double buffer latch
0
X
X
1
Write to double buffer latch only
X
1
X
X
12.5 µs settling time
X
0
X
X
2.5 µs settling time
X
X
0
X
Powered-up operation
X
X
1
X
Powered-down mode
function of the latch control bits (D15 and D12)
Three data transfers are possible. All transfers occur immediately after CS goes high and are described in the
following sections.
latch A write, latch B update (D15 = high, D12 = X)
The serial interface register (SIR) data are written to latch A and the double buffer latch contents are written to
latch B. The double buffer contents are unaffected. This control bit condition allows simultaneous output updates
of both DACs.
Serial
Interface
Register
D12 = X
D15 = High
Double
Buffer
Latch
Latch A
To DAC A
Latch B
To DAC B
Figure 19. Latch A Write, Latch B Update
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APPLICATION INFORMATION
latch B and double-buffer 1 write (D15 = low, D12 = low)
The SIR data are written to both latch B and the double buffer. Latch A is unaffected.
Serial
Interface
Register
D12 = Low
D15 = Low
Double
Buffer
Latch
Latch A
To DAC A
Latch B
To DAC B
Figure 20. Latch B and Double-Buffer Write
double-buffer-only write (D15 = low, D12 = high)
The SIR data are written to the double buffer only. Latch A and B contents are unaffected.
Serial
Interface
Register
D12 = High
D15 = Low
Double
Buffer
Latch A
To DAC A
Latch B
To DAC B
Figure 21. Double-Buffer-Only Write
purpose and use of the buffer
Normally only one DAC output can change after a write. The double buffer allows both DAC outputs to change
after a single write. This is achieved by the two following steps.
1. A double-buffer-only write is executed to store the new DAC B data without changing the DAC A and B
outputs.
2. Following the previous step a write to latch A is executed. This writes the SIR data to latch A and also writes
the double-buffer contents to latch B. Thus both DACs receive their new data at the same time and so both
DAC outputs begin to change at the same time.
Unless a double-buffer-only write is issued, the latch B and double-buffer contents are identical. Thus, following
a write to latch A or B with another write to latch A does not change the latch B contents.
14
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operational examples
changing the latch A data from zero to full code
Assuming that latch A starts at zero code (e.g., after power up), the latch can be filled with 1s by writing (bit D15
on the left, D0 on the right)
1X0X 1111 1111 11XX
to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The other Xs can
be zero or one (don’t care).
The latch B contents and the DAC B output are not changed by this write unless the double-buffer contents are
different from the latch B contents. This can only be true if the last write was a double-buffer-only write.
changing the latch B data from zero to full code
Assuming that latch B starts at zero code (e.g., after power-up), the latch can be filled with 1s by writing (bit D15
on the left, D0 on the right).
0X00 1111 1111 11XX
to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The other Xs can
be zero or one (don’t care). The data (bits D0 to D11) are written to both the double buffer and latch B.
The latch A contents and the DAC A output are not changed by this write.
double-buffered change of both DAC outputs
Assuming that DACs A and B start at zero code (e.g., after power-up), if DAC A is to be driven to mid-scale and
DAC B to full-scale, and if the outputs are to begin rising at the same time, this can be achieved as follows:
First,
0d01 1111 1111 11XX
is written (bit D15 on the left, D0 on the right) to the serial interface. This loads the full-scale code into the double
buffer latch but does not change the latch B contents and the DAC B output voltage. The latch A contents and
the DAC A output are also unaffected by this write operation.
Changing from fast to slow mode or slow to fast mode changes the supply current which can glitch the outputs,
and so D14 (designated by d in the data word) should be set to maintain the speed made set by the previous
write. The other Xs can be ones or zeros (don’t care).
Next,
1X0X 1000 0000 00XX
is written (bit D15 on the left, D0 on the right) to the serial interface. Bit D14 can be zero to select slow mode
or one to select fast mode. The other Xs can be zero or one (don’t care). This writes the mid-scale code
(1000000000XX) to latch A and also copies the full-scale code from the double buffer to latch B. Both DAC
outputs thus begin to rise after the second write.
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APPLICATION INFORMATION
DSP serial interface
Utilizing a simple 3-wire serial interface, the TLC5617A can be interfaced to TMS320 compatible serial ports.
The 5617A has an internal state machine that counts 16 clocks after receiving a falling edge of CS and then
disable further clocking in of data until the next falling edge is received on CS. Therefore the CS can be
connected directly to the FS pins of the serial port and only the leading falling edge of the DSP will be used to
start the write process. The TLC5617A is designed to be used with the TMS320Cxx DSP in burst mode serial
port transmit operation.
VCC
FSR
FSX
CS
Analog
Output
OUT A
TLC5617
Analog
Output
OUT B
CLKX
SCLK
TMS320C32
DSP
CLKR
DX
DIN
REFIN
2.5 V dc
GND
To Source
Ground
Figure 22. Interfacing The TLC5617 To TMS320C32 DSP
SPI serial interface
Both the TLC5617 and TLC5617A are compatible with SPI, QSPI, or Microwire serial standards. The hardware
connections are shown in Figure 23 and Figure 24. The TLC5617A has an internal state machine that counts
16 clocks after the falling edge of CS and then internally disables the device. The internal edge is ORed together
with CS so that the rising edge can be provided to CS prior to the occurrence of the internal edge to also disable
the device.
general serial interface
The TLC5617 3-wire interface is compatible with the SPI, QSPI, and Microwire serial standards. The hardware
connections are shown in Figure 23 and Figure 24.
The SPI and Microwire interfaces transfer data in 8-bit bytes, therefore, two write cycles are required to input
data to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC
input register in one write cycle.
16
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APPLICATION INFORMATION
general serial interface (continued)
SK
SCLK
SO Microwire
Port
DIN
TLC5617
I/O
CS
Figure 23. Microwire Connection
SCK
SCLK
MOSI SPI/QSPI
Port
I/O
DIN
TLC5617
CS
CPOL = 1, CPHA = 0
Figure 24. SPI/QSPI Connection
linearity, offset, and gain error using single-end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage remains at zero until the input code value produces a sufficient positive output voltage to
overcome the negative offset voltage, resulting in the transfer function shown in Figure 25.
Output
Voltage
0V
DAC Code
Negative
Offset
Figure 25. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
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APPLICATION INFORMATION
linearity, offset, and gain error using single end supplies (continued)
For a DAC, linearity is measured between zero input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full-scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage. For the
TLC5617, the zero-scale (offset) error is plus or minus 3 LSB maximum. The code is calculated from the
maximum specification for the negative offset.
power-supply bypassing and ground management
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground
currents are well managed.
A 0.1-µF ceramic bypass capacitor should be connected between VDD and AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog and digital power
supplies.
Figures 26 shows the ground plane layout and bypassing technique.
Analog Ground Plane
1
8
2
7
3
6
4
5
0.1 µF
Figure 26. Power-Supply Bypassing
saving power
Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the output
load when the system is not using the DAC.
ac considerations/analog feedthrough
Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog
feedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied to
REFIN, and monitoring the DAC output.
18
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SLAS151B – JULY 1997 – REVISED MARCH 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
1
Gage Plane
7
A
0.010 (0,25)
0°– 8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
4040047 / D 10/96
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
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