SCDS176 − SEPTEMBER 2004
D Wide Bandwidth (BW = 500 MHz Typ)
D Low Crosstalk (XTALK = −30 dB Typ)
D Bidirectional Data Flow, With Near-Zero
D
D
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
E
ID0
ID1
YD
IC0
IC1
YC
IA0
IA1
YA
IB0
IB1
YB
1
16
15 E
14 ID0
2
3
13 ID1
12 YD
4
5
6
7
8
9
YC
S
IA0
IA1
YA
IB0
IB1
YB
GND
VCC
RGY PACKAGE
(TOP VIEW)
D, DBQ, DGV, OR PW PACKAGE
(TOP VIEW)
S
D
D
D
D
Propagation Delay
Low and Flat ON-State Resistance
(ron = 4 W Typ, ron(flat) = 1 W)
Switching on Data I/O Ports (0 to 5 V)
VCC Operating Range From 3 V to 3.6 V
Ioff Supports Partial-Power-Down Mode
Operation
Clamp Diodes
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
Suitable for Both 10 Base-T/100 Base-T
Signaling
GND
D
D Data and Control Inputs Have Undershoot
11 IC0
10 IC1
description/ordering information
The TI TS3L110 LAN switch is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable (E) input.
When E is low, the switch is enabled, and the I port is connected to the Y port. When E is high, the switch is
disabled, and the high-impedance state exists between the I and Y ports. The select (S) input controls the data
path of the multiplexer/demultiplexer.
ORDERING INFORMATION
QFN − RGY
SOIC − D
−40°C
−40
C to 85
85°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SSOP (QSOP) − DBQ
TSSOP − PW
TVSOP − DGV
Tape and reel
TS3L110RGYR
Tube
TS3L110D
Tape and reel
TS3L110DR
Tape and reel
TS3L110DBQR
Tube
TS3L110PW
Tape and reel
TS3L110PWR
Tape and reel
TS3L110DGVR
TOP-SIDE
MARKING
TK110
TS3L110
TK110
TK110
TK110
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
POST OFFICE BOX 655303
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1
SCDS176 − SEPTEMBER 2004
description/ordering information (continued)
This device can be used to replace mechanical relays in LAN applications. This device has low and flat ron, wide
bandwidth, and low crosstalk, making it suitable for 10 Base-T, 100 Base-T, and various other LAN applications.
The device can be used to route signals from a 10/100 Base-T ethernet transceiver to the RJ-45 LAN connectors
in laptops or in docking stations. The device is designed for low channel-to-channel skew and low crosstalk.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, E should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
E
INPUT/OUTPUT
YX
S
FUNCTION
L
L
H
IX0
IX1
YX = IX0
L
H
X
Z
Disconnect
YX = IX1
PIN DESCRIPTIONS
PIN NAME
IAn−IDn
S
Select input
E
Enable input
YA−YD
2
DESCRIPTION
Data I/Os
Data I/Os
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SCDS176 − SEPTEMBER 2004
logic diagram (positive logic)
2
4
IA0
YA
3
IA1
YB
7
5
IB0
6
IB1
9
11
YC
10
YD
12
14
13
S
IC0
IC1
ID0
ID1
1
15
Control
Logic
E
POST OFFICE BOX 655303
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3
SCDS176 − SEPTEMBER 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA
Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground, unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 7)
MIN
MAX
UNIT
VCC
VIH
Supply voltage
3
3.6
V
High-level control input voltage (E, S)
2
5.5
V
VIL
VI/O
Low-level control input voltage (E, S)
0
0.8
V
Input/output voltage
0
5.5
V
TA
Operating free-air temperature
−40
85
°C
NOTE 7: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303
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SCDS176 − SEPTEMBER 2004
electrical characteristics over recommended
VCC = 3.3 V + 0.3 V (unless otherwise noted)
PARAMETER
VIK
IIH
E, S
IIL
Ioff
E, S
operating
free-air
TEST CONDITIONS
temperature
range,
TYP†
MAX
UNIT
−1.8
V
±1
µA
±1
µA
1
µA
0.7
1.5
mA
2.5
3.5
pF
MIN
VCC = 3.6 V,
VCC = 3.6 V,
IIN = −18 mA
VIN = 5.5 V
VCC = 3.6 V,
VCC = 0,
VIN = GND
VO = 0 to 5.5 V ,
E, S
VCC = 3.6 V,
f = 1 MHz,
II/O = 0,
VIN = 0
I port
VI = 0,
f = 1 MHz,
Outputs open,
Switch OFF
3.5
5
Y port
VI = 0,
f = 1 MHz,
Outputs open,
Switch OFF
5.5
7
I or Y port
VI = 0,
f = 1 MHz,
Outputs open,
Switch ON
10.5
13
pF
ron
VCC = 3 V
1.25 V ≤ VI ≤ VCC,
II = −10 mA to −30 mA
4
8
Ω
ron(flat)‡
VCC = 3 V
VI = 1.25 V and VCC,
II = −10 mA to −30 mA
1
∆ron§
VCC = 3 V,
1.25 V ≤ VI ≤ VCC,
II = −10 mA to −30 mA
0.9
E, S
ICC
Cin
Cio(OFF)
Cio(ON)
VI = 0
Switch ON or OFF
pF
Ω
2
Ω
VI, VO, II, and IO refer to I/O pins. VIN refers to the control inputs.
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
‡ ron(flat) is the difference of ron in a given channel at specified voltages.
§ ∆ron is the difference of ron in a given device.
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V + 0.3 V, RL = 200 Ω, CL = 10 pF (unless otherwise noted) (see Figures 5 and 6)
FROM
(INPUT)
TO
(OUTPUT)
tpd¶
I or Y
Y or I
tPZH, tPZL
E or S
I or Y
0.5
tPHZ, tPLZ
tsk(p)#
E or S
I or Y
0.5
I or Y
Y or I
PARAMETER
MIN
TYP†
MAX
0.25
0.1
UNIT
ns
7
ns
5
ns
0.2
ns
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
¶ The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).
# Skew between opposite transitions of the same output |tPHL − tPLH|. This parameter is not production tested.
dynamic characteristics over recommended
VCC = 3.3 V + 0.3 V (unless otherwise noted)
PARAMETER
XTALK
OIRR
operating
TEST CONDITIONS
free-air
temperature
range,
TYP†
UNIT
MIN
MAX
RL = 100 Ω,
f = 250 MHz, see Figure 7
−26
RL = 100 Ω,
f = 250 MHz, see Figure 8
−28
dB
500
MHz
BW
RL = 100 Ω, see Figure 6
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
POST OFFICE BOX 655303
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dB
5
SCDS176 − SEPTEMBER 2004
OPERATING CHARACTERISTICS
0
0
Phase
−10
−1
−20
Gain
−30
−3
J
−40
−4
−5
Y
Phase (Deg)
Gain (dB)
−2
−50
−60
−6
−70
−7
1
10
100
700
Frequency (MHz)
J
Y
Phase at 627 MHz, −36 Degrees
Gain −3 dB at 627 MHz
Figure 1. Gain/Phase vs Frequency
20
120
0
100
Phase
J
80
Y
−40
60
Gain
−60
40
−80
20
−100
1
J
Y
10
Frequency (MHz)
100
Phase at 250 MHz, 88.2 Degrees
Gain −28.5 dB at 250 MHz
Figure 2. OFF Isolation vs Frequency
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0
700
Phase (Deg)
Gain (dB)
−20
SCDS176 − SEPTEMBER 2004
OPERATING CHARACTERISTICS
0
180
−10
160
−20
140
J
Y
−40
100
Phase
−50
80
−60
60
Phase (Deg)
120
Gain
−70
40
−80
20
−90
1
10
0
700
100
Frequency (MHz)
Phase at 250 MHz, 137.92 Degrees
Gain −26 dB at 250 MHz
Figure 3. Crosstalk vs Frequency
5
20
4
16
VO
3
12
2
8
rON
1
ON-State Resistance (Ω)
J
Y
Output Voltage (V)
Gain (dB)
−30
4
0
0
0
1
2
3
4
5
Input Voltage (V)
Figure 4. Output Voltage/ON-State Resistance vs Input Voltage
POST OFFICE BOX 655303
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7
SCDS176 − SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
FOR ENABLE AND DISABLE TIMES
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
Input Generator
VI
S1
RL
VO
2 × VCC
Open
GND
50 Ω
50 Ω
VG2
CL
(see Note A)
RL
TEST
VCC
S1
RL
VI
CL
V∆
tPLZ/tPZL
3.3 V ± 0.3 V
2 × VCC
200 Ω
GND
10 pF
0.3 V
tPHZ/tPZH
3.3 V ± 0.3 V
GND
200 Ω
VCC
10 pF
0.3 V
Output Control
(VIN)
2.5 V
1.25 V
1.25 V
Output
Waveform 1
S1 at 2 y VCC tPZL
(see Note B)
0V
tPLZ
VOH
VCC/2
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOL +0.3 V
VOL
tPHZ
VCC/2
VOH −0.3 V
VOH
VOL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
Figure 5. Test Circuit and Voltage Waveforms
8
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SCDS176 − SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
FOR SKEW
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
Input Generator
RL
VO
VI
S1
2 × VCC
Open
GND
50 Ω
50 Ω
VG2
CL
(see Note A)
RL
TEST
VCC
S1
RL
VIN
(see Note B)
CL
tsk(p)
3.3 V ± 0.3 V
GND
200 Ω
VCC or GND
10 pF
3.5 V
Data Input
2.5 V
1.5 V
tPLH
tPHL
VOH
0.5 V (VOH − VOL)
VOL
Data Output
tsk(p) = |tPHL − tPLH|
VOLTAGE WAVEFORMS
PULSE SKEW (tsk(p))
NOTES: A. CL includes probe and jig capacitance.
B. Switch is ON during the measurement of tsk(p), i.e., voltage at E = 0 and S = VCC or GND
Figure 6. Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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9
SCDS176 − SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
VBIAS
P1
P2
VCC
IA0
YA
CL = 10 pF
(see Note A)
RL = 100 Ω
S
DUT
VS
E
VE
NOTE A: CL includes probe and jig capacitance.
Figure 7. Test Circuit for Frequency Response (BW)
Frequency response is measured at the output of the ON channel. For example, when VS = 0, VE = 0, and YA is the
input, the output is measured at IA0. All unused analog I/O ports are left open.
HP8753ES setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBm
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCDS176 − SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
VBIAS
P1
P2
VCC
YA
IA0
S
RL = 100 Ω
CL = 10 pF
(see Note A)
RL = 100 Ω
CL = 10 pF
(see Note A)
50 Ω
(see Note B)
VS
E
DUT
VE
YB
IB0
NOTES: A. CL includes probe and jig capacitance.
B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.
Figure 8. Test Circuit for Crosstalk (XTALK)
Crosstalk is measured at the output of the nonadjacent ON channel. For example, when VS = 0,
VE = 0, and YA is the input, the output is measured at IB0. All unused analog input (Y) ports are connected to GND,
and output (I) ports are connected to GND through 50-Ω pulldown resistors.
HP8753ES setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBm
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SCDS176 − SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
VBIAS
P1
P2
VCC
IA0
YA
S
RL = 100 Ω
CL = 10 pF
(see Note A)
RL = 100 Ω
CL = 10 pF
(see Note A)
DUT
VS
IA1
E
VE
50 Ω
(see Note B)
NOTES: A. CL includes probe and jig capacitance.
B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.
Figure 9. Test Circuit for OFF Isolation (OIRR)
OFF isolation is measured at the output of the OFF channel. For example, when VS = VCC, VE = 0, and YA is the input,
the output is measured at IA0. All unused analog input (Y) ports are left open, and output (I) ports are connected to
GND through 50-Ω pulldown resistors.
HP8753ES setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBm
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
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