TI SN74ABT32501

SCBS229B − JUNE 1992 − REVISED NOVEMBER 1994
•
•
•
•
•
•
Members of the Texas Instruments
Widebus +  Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
UBT  (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
ESD Protection Exceeds 2000 V per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Latch-Up Performance Exceeds 500 mA
per JEDEC Standard JESD-17
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Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
High-Drive Outputs (− 32-mA IOH,
64-mA IOL )
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Packaged in 100-Pin Plastic Thin Quad
Flat (PZ) Package With 14 × 14-mm Body
Using 0.5-mm Lead Pitch
2A11
2A12
2A13
GND
2A14
2A15
2A16
2A17
2A18
2OEBA
2LEBA
2CLKBA
VCC
2CLKAB
2LEAB
2OEAB
2B18
2B17
2B16
2B15
2B14
GND
2B13
2B12
2B11
′ABT32501 . . . PZ PACKAGE
(TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
2A10
2A9
GND
2A8
2A7
2A6
2A5
GND
2A4
2A3
2A2
2A1
VCC
1A1
1A2
1A3
1A4
GND
1A5
1A6
1A7
1A8
GND
1A9
1A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2B10
2B9
GND
2B8
2B7
2B6
2B5
GND
2B4
2B3
2B2
2B1
VCC
1B1
1B2
1B3
1B4
GND
1B5
1B6
1B7
1B8
GND
1B9
1B10
1A11
1A12
1A13
GND
1A14
1A15
1A16
1A17
1A18
1OEBA
1LEBA
1CLKBA
VCC
1CLKAB
1LEAB
1OEAB
1B18
1B17
1B16
1B15
1B14
GND
1B13
1B12
1B11
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Widebus+, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.
Copyright  1994, Texas Instruments Incorporated
! "#$%&'( $#()(! (*#+&)#( $%++'( )! #* ,%-.$)#( ")'/ +#"%$! $#(*#+& #
!,'$*$)#(! ,'+ ' '+&! #* '0)! (!+%&'(! !)(")+" 1)++)(2/
+#"%$#( ,+#$'!!(3 "#'! (# ('$'!!)+.2 ($.%"' '!(3 #* )..
,)+)&''+!/
• DALLAS, TEXAS 75265
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POST OFFICE BOX 655303
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1
SCBS229B − JUNE 1992 − REVISED NOVEMBER 1994
description
These 36-bit UBTs combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and
clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Data flow for B to A is
similar to that of A to B, but uses OEBA, LEBA, and CLKBA.
Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs
are in the high-impedance state. The output enables are complementary (OEAB is active high, and OEBA is
active low).
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABT32501 is characterized for operation over the full military temperature range of −55°C to 125°C.
The SN74ABT32501 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE†
INPUTS
OEAB
LEAB
CLKAB
A
OUTPUT
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
↑
L
L
H
L
↑
H
H
H
L
H
X
B0‡
B0§
H
L
L
X
† A-to-B data flow is shown: B-to-A flow is similar, but
uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state input
conditions were established
§ Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was low before LEAB went low
2
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•
SCBS229B − JUNE 1992 − REVISED NOVEMBER 1994
logic diagram (positive logic)
1OEAB
1CLKBA
1LEBA
1OEBA
1CLKAB
1LEAB
1A1
41
37
36
35
39
40
14
CLK
62
LE
1B1
D
CLK
LE
D
To 17 Other Channels
2OEAB
2CLKBA
2LEBA
2OEBA
2CLKAB
2LEAB
2A1
85
89
90
91
87
86
12
CLK
64
LE
2B1
D
CLK
LE
D
To 17 Other Channels
•
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•
3
SCBS229B − JUNE 1992 − REVISED NOVEMBER 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . −0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT32501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT32501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W
Operating free-air temperature range, TA: SN54ABT32501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
SN74ABT32501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
SN54ABT32501
SN74ABT32501
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
−24
Low-level output current
48
64
mA
∆t /∆v
Input transition rise or fall rate
10
10
ns / V
∆t /∆VCC
Power-up ramp rate
High-level input voltage
2
0.8
Input voltage
0
Outputs enabled
200
TA
Operating free-air temperature
NOTE 3: Unused or floating pins (input or I/O) must be held high or low.
(*#+&)#( $#($'+(! ,+#"%$! ( ' *#+&)4' #+
"'!3( ,)!' #* "'4'.#,&'(/ )+)$'+!$ ")) )(" #'+
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$)(3' #+ "!$#((%' '!' ,+#"%$! 1#% (#$'/
4
2
•
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
−55
0
V
0.8
V
VCC
−32
V
−40
mA
µs / V
200
125
V
85
°C
SCBS229B − JUNE 1992 − REVISED NOVEMBER 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VCC = 4.5 V,
VCC = 4.5 V,
II = −18 mA
IOH = − 3 mA
VCC = 5 V,
IOH = − 3 mA
IOH = − 24 mA
VCC = 4.5 V
VOL
MIN
II
A or B ports
VCC = 0 to 5.5 V,
VCC = 2.1 V to 5.5 V,
II(hold)
A or B ports
VCC = 4.5 V
−1.2
3
3
UNIT
V
V
2
0.55
IOL = 64 mA
VI = VCC or GND
VI = 2 V
VO = 0.5 V to 2.7 V,
OE or OE = X
IOZH§
VCC = 2.1 V to 5.5 V,
OE ≥ 2 V,
IOZL§
Ioff
ICEX
IO#
0.55
0.55
VI = VCC or GND
VI = 0.8 V
VCC = 0 to 2.1 V
VCC = 2.1 V to 0
∆ICC||
−1.2
2.5
2
IOZPU‡
IOZPD‡
ICC
SN74ABT32501
TYP†
MAX
MIN
2.5
IOH = − 32 mA
IOL = 48 mA
VCC = 4.5 V
Control inputs
SN54ABT32501
TYP†
MAX
TEST CONDITIONS
±1
±1
± 20
± 20
100
100
−100
−100
V
A
µA
µA
A
± 50
± 50
µA
± 50
± 50
µA
VO = 2.7 V,
OE ≤ 0.8 V¶
10
10
µA
VCC = 2.1 V to 5.5 V,
OE ≥ 2 V,
VO = 0.5 V,
OE ≤ 0.8 V¶
−10
−10
µA
VCC = 0,
VCC = 5.5 V,
VI or VO ≤ 4.5 V
VO = 5.5 V Outputs high
± 100
± 100
µA
VCC = 5.5 V,
VO = 2.5 V
Outputs high
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
50
−50
−100
Outputs low
Outputs disabled
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
Ci
−180
−50
−100
50
µA
−180
mA
6
6
90
90
6
6
1
1
Control inputs VI = 2.5 V or 0.5 V
3.5
3.5
Cio
A or B ports
VO = 2.5 V or 0.5 V
11.5
11.5
† All typical values are at VCC = 5 V, TA = 25°C.
‡ This parameter is specified by characterization.
§ The parameters IOZH and IOZL include the input leakage current.
¶ For VCC between 2.1 V and 4 V, OE should be less than or equal to 0.5 V to ensure a low state.
# Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
|| This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
mA
mA
pF
pF
(*#+&)#( $#($'+(! ,+#"%$! ( ' *#+&)4' #+
"'!3( ,)!' #* "'4'.#,&'(/ )+)$'+!$ ")) )(" #'+
!,'$*$)#(! )+' "'!3( 3#).!/ '0)! (!+%&'(! +'!'+4'! ' +3 #
$)(3' #+ "!$#((%' '!' ,+#"%$! 1#% (#$'/
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
5
SCBS229B − JUNE 1992 − REVISED NOVEMBER 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT32501
fclock
MIN
MAX
0
150
Clock frequency
tw
Pulse duration
tsu
Setup time
th
Hold time
SN74ABT32501
MIN
MAX
0
150
LE high
3.3
3.3
CLK high or low
3.3
3.3
A or B before CLK↑
3.5
3.5
A or B before LE↓
1.6
1.6
A or B after CLK↑
0
0
1.6
1.6
A or B after LE↓
UNIT
MHz
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
LEAB or LEBA
B or A
CLKAB or CLKBA
B or A
OEAB or OEBA
B or A
OEAB or OEBA
tPLZ
† All typical values are at VCC = 5 V, TA = 25°C.
B or A
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
SN54ABT32501
TYP†
MAX
MIN
150
150
2.9
4.8
1.3
2.9
4.8
1.4
2.7
5.4
1.4
2.7
5.4
1.6
3.4
5.3
1.6
3.4
5.3
1.9
3.6
5.5
1.9
3.6
5.5
1.5
3.2
5.3
1.5
3.2
5.3
1.7
3.3
5.4
1.7
3.3
5.4
1.2
3.2
5.6
1.2
3.2
5.6
1.5
3.6
6
1.5
3.6
6
1.8
3.6
5.9
1.8
3.6
5.9
1.7
3.5
5.6
1.7
3.5
5.6
•
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•
UNIT
MHz
1.3
(*#+&)#( $#($'+(! ,+#"%$! ( ' *#+&)4' #+
"'!3( ,)!' #* "'4'.#,&'(/ )+)$'+!$ ")) )(" #'+
!,'$*$)#(! )+' "'!3( 3#).!/ '0)! (!+%&'(! +'!'+4'! ' +3 #
$)(3' #+ "!$#((%' '!' ,+#"%$! 1#% (#$'/
6
SN74ABT32501
TYP†
MAX
MIN
ns
ns
ns
ns
ns
SCBS229B − JUNE 1992 − REVISED NOVEMBER 1994
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
LOAD CIRCUIT FOR OUTPUTS
3V
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
Input
1.5 V
1.5 V
Data Input
0V
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
3V
1.5 V
Input
Output
Control
1.5 V
0V
1.5 V
1.5 V
VOL
tPLH
tPHL
Output
Waveform 2
S1 at Open
(see Note C)
VOH
Output
1.5 V
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note C)
VOH
Output
1.5 V
tPZL
tPHL
tPLH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
3.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH − 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
7
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