TI SN65LVDS151DAR

SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
A Member of the MuxIt 
SN65LVDS151DA
Serializer-Deserializer Building-Block Chip
Family
Supports Serialization of up to 10 Bits of
Parallel Data Input at Rates up to 200 Mbps
PLL Lock/Valid Input Provided to Enable
Link Data Transfers
Cascadable With Additional SN65LVDS151
MuxIt Serializer-Transmitters for Wider
Parallel Input Data Channel Widths
LVDS Compatible Differential Inputs and
Outputs Meet or Exceed the Requirements
of ANSI TIA/EIA-644-A
LVDS Inputs and Outputs ESD Protection
Exceeds 12 kV HBM
LVTTL Compatible Inputs for Lock/Valid,
Enables, and Parallel Data Inputs Are 5-V
Tolerant
Operates With 3.3 V Supply
Packaged in 32-Pin DA Thin Shrink
Small-Outline Package With 26 Mil Terminal
Pitch
(Marked as 65LVDS151)
VCC
GND
LCRI+
LCRI–
CI_EN
DI–9
DI–8
DI–7
DI–6
DI–5
DI–4
DI–3
DI–2
DI–1
DI–0
GND
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
CI–
CI+
LVI
MCI–
MCI+
GND
VCC
LCO+
LCO–
VCC
EN
LCO_EN
VCC5
GND
DO+
DO–
description
MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and
deserializers. The system allows for wide parallel data to be transmitted through a reduced number of
transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS)
data interface. The number of bits multiplexed per transmission line is user-selectable and allows for higher
transmission efficiencies than with existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A) low
voltage differential signaling technology for communications between the data source and data destination.
The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phase
locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152
receiver-deserializer.
The SN65LVDS151 consists of a 10-bit parallel-in/serial-out shift register, three LVDS differential transmission
line receivers, a pair of LVDS differential transmission line drivers, plus associated input buffers. It accepts up
to 10 bits of user data on parallel data inputs (DI–0 → DI–9) and serializes (multiplexes) the data for transmission
over an LVDS transmission line link. Two or more SN65LVDS151 units may be connected in series (cascaded)
to accommodate wider parallel data paths for higher serialization values. Data is transmitted over the LVDS
serial link at M times the input parallel data clock frequency. The multiplexing ratio M, or number of bits per data
clock cycle, is programmed on the companion SN65LVDS150 MuxIt programmable PLL frequency multiplier
with configuration pins (M1 → M5). The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt
programmable PLL frequency multiplier is between 4 and 40. Table 1 shows some of the combinations of LCRI
and MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MuxIt is a trademark of Texas Instruments.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
description (continued)
Data is parallel loaded into the SN65LVDS151 input latches on the first rising edge of the M-clock input (MCI)
signal following a rising edge of the link clock reference input (LCRI). The data is read out serially from the
SN65LVDS151 shift registers on the rising edges of the M-clock input (MCI). The lowest order bit of parallel input
data, DI – 0, is output from DO on the third rising edge of MCI following the rising edge of LCRI. The remaining
bits of parallel input data, DI-1 → DI-(M-1) are clocked out sequentially, in ascending order, by subsequent MCI
rising edges. The link clock output (LCO) signal rising edge is synchronized to the data output (DO) by an internal
circuit clocked by MCI. The LCO signal rising edge follows the first rising edge of MCI after the rising edge of
LCRI. Examples of operating waveforms for values of M = 4 and M = 10 are provided in Figure 1.
Both the LCRI and MCI signals are intended to be sourced from the SN65LVDS150 MuxIt programmable
frequency multiplier. They are carried over LVDS differential connections to minimize skew and jitter. The
SN65LVDS151 includes LVDS differential line drivers for both the serialized data output (DO) stream and the
link clock output (LCO). The cascade input (CI) is also an LVDS connection, and when it is used it is tied to the
DO output of the preceding SN65LVDS151.
An internal power-on reset (POR) and an enable input (EN) control the operation of the SN65LVDS151. When
VCC is below 1.5 V, or when EN is low, the device is in a low-power disabled state, and the DO and LCO
differential outputs are in a high-impedance state. When VCC is above 3 V and EN is high, the device and the
two differential outputs are enabled and operating to specifications. The link clock output enable input
(LCO_EN) is used to turn off the LCO output when it is not being used. Cascade input enable (CI_EN) is used
to turn off the CI input when it is not being used.
Serialized data bits are output from the DO output, starting in ascending order, from parallel input bit DI – 0. The
number of serialized data bits output per data clock cycle is determined by the multiplexing ratio M. For values
of M less than or equal to 10, the cascade input (CI±) is not used, and only the first M parallel input bits (DI – 0
thought DI – [M – 1]) are used. For values of M greater than 10, all ten parallel input bits (DI – 0 though DI – 9) are
used, and the cascade input is used to shift in the remaining data bits from additional SN65LVDS151 serializers.
Table 2 shows which input data bits are used as a function of the multiplier M.
Table 1. Example Combinations of LCRI and MCI Supported by the
SN65LVDS150 MuxIt Programmable PLL Frequency Multiplier
LCRI, MHz
2
MCI, MHz
M
MINIMUM
MAXIMUM
MINIMUM
MAXIMUM
4
5
50
20
200
10
5
20
50
200
20
5
10
100
200
40
5
5
200
200
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SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
description (continued)
Table 2. Input Data Bits Used as a Function of the Multiplier M
M=4
M=5
M=6
M=7
M=8
M=9
M = 10
M >10
1st bit output
2nd bit output
DI-0
DI-0
DI-0
DI-0
DI-0
DI-0
DI-0
DI-0
DI-1
DI-1
DI-1
DI-1
DI-1
DI-1
DI-1
DI-1
3rd bit output
4th bit output
DI-2
DI-2
DI-2
DI-2
DI-2
DI-2
DI-2
DI-2
DI-3
DI-3
DI-3
DI-3
DI-3
DI-3
DI-3
DI-3
5th bit output
6th bit output
Invalid
DI-4
DI-4
DI-4
DI-4
DI-4
DI-4
DI-4
Invalid
Invalid
DI-5
DI-5
DI-5
DI-5
DI-5
DI-5
7th bit output
8th bit output
Invalid
Invalid
Invalid
DI-6
DI-6
DI-6
DI-6
DI-6
Invalid
Invalid
Invalid
Invalid
DI-7
DI-7
DI-7
DI-7
9th bit output
10th bit output
Invalid
Invalid
Invalid
Invalid
Invalid
DI-8
DI-8
DI-8
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
DI-9
DI-9
11th + bits output
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
CI bits
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3
SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
block diagram
CI
DI–9
DI–8
DI–7
DI–4
Shift Register
DI–5
Input Latches
DI–6
DI–3
DI–2
DI–1
DI–0
LCRI
EN
LVI
DO
Control Logic
MCI
LCO
CI_EN
LCO_EN
† The CI input includes a 110 Ω termination resistor.
4
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SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
M=4
DI–n
Current Frame
Next Frame
Data
Clock
LCRI
MCI
LCO
DO
DI(3)
DI(0)
DI(1)
DI(2)
DI(3)
DI(0)
Current Frame
M = 10
DI–n
Current Frame
Next Frame
Data
Clock
LCRI
MCI
LCO
DO
DI(9)
DI(0)
DI(1)
DI(2)
DI(3)
DI(4)
DI(5)
DI(6)
DI(7)
DI(8)
DI(9)
DI(0)
Current Frame
Figure 1. Operating Waveform Examples
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5
SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
equivalent input and output schematic diagrams
VCC
VCC
300 kΩ
300 kΩ
LCRI–,
MCI–,
or CI–
Inputs
LCRI+,
MCI+,
or CI+
Inputs
4V
50 Ω
10 kΩ
4V
4V
110 Ω, (CI Input Only)
VCC5
VCC
DI-n
Inputs Only
EN, LVI,
CI_EN,
LCO_EN,
or DI-n
Inputs
400 Ω
6V
300 kΩ
6
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LCO+,
LCO–,
DO+,
or DO–
Outputs
SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
Terminal Functions
TERMINAL
NAME
CI+, CI–
CI_EN
DO–, DO+
EN
GND
NO.
I/O
TYPE
DESCRIPTION
31, 32
I
LVDS
Cascade input. This may be used to connect additional SN65LVDS151 units when the
multiplexing ratio M value is greater than 10. This input has an internal 110-Ω nominal
termination resistor.
5
I
LVTTL
Cascade input enable. Used to enable or disable the cascade input differential receiver. A
high-level input enables the CI input, a low-level input disables the CI input.
17, 18
O
LVDS
Data output. This is the data being transmitted to the destination end of the serial link, or
being supplied to another SN65LVDS151 unit in cascade.
22
I
LVTTL
Enable. Controls device operation. A high-level input enables the device; a low-level input
disables and resets the device. When initially enabled, all outputs are in a low-level
condition.
2, 16, 19, 27
NA
Circuit ground
25, 24
O
LVDS
Link clock output This is the data block synchronization clock being transmitted to the
destination end of the serial link.
LCO_EN
21
I
LVTTL
Link clock output enable. Used to disable the link clock output when it is not being used. A
high-level input enables the LCO output; a low-level input disables the LCO output.
LCRI+, LCRI–
3, 4
I
LVDS
Link clock reference input. This is the clock for latching in the parallel data; it comes from the
PLL frequency multiplier.
LVI
30
I
LVTTL
Lock/valid input. This is a signal required for proper Muxlt system operation. It is directly
connected to the LVO output of a SN65LVDS150. It is used to inhibit the operation of this
device until after the PLL has stabilized. A low level input forces a reset of the internal
latches and shift registers, and forces the DO and LCO outputs to a low level. A high level
input enables operation.
28, 29
I
LVDS
M-clock input. This is the high frequency multiplied clock input from the local PLL frequency
multiplier. It synchronizes the transmission of the link data
6-15
I
LVTTL
Parallel data inputs. Data is latched into the device on the first rising edge of MCI following a
rising edge of LCRI.
1, 23, 26
NA
Supply voltage
20
NA
5-V VCC tolerance bias. Tied to 5 V nominal when the LVTTL inputs are being driven by a
device powered from a 5-V supply, otherwise tied to local VCC
LCO+, LCO–
MCI+, MCI–
DI-9–DI-0
VCC
VCC5
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Voltage range: DI–0 through DI–9 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC5 +0.5 V
EN, CI_EN, LCO_EN, LVI inputs, VCC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
CI±, LCRI±, or MCI± Inputs, DO±, or LCO± outputs . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to 4 V
Electrostatic discharge, human body model (see Note 2):
MCI±, LCRI±, CI±, DO±, LCO±, and GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±12 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 kV
Charged-device model (see Note 3): All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114–B.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
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SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
DA
1453 mW
11.6 mW/°C
756 mW
recommended operating conditions
MIN
Supply voltage, VCC
3
High-level input voltage, VIH
2
DI – 0 – DI – 9,
9 EN,
EN LVI,
LVI LCO_EN,
LCO EN CI
CI_EN
EN
Low-level input voltage, VIL
UNIT
3.6
V
V
0.1
|V
ID
2
LCRI, MCI, CI
MAX
0.8
Magnitude of differential input voltage, |VID|
Common
mode in
ut voltage, VIC
Common-mode
input
NOM
3.3
Operating free-air temperature, TA
V
0.6
|
|V
V
ID
2
VCC–0.8
2.4 – 40
|
V
V
°C
85
timing requirements
PARAMETERS
TEST CONDITIONS
tsu(1)
th(1)
LCRI↑setup time before MCI↑
tsu(2)
th(2)
Data setup time, DI – 0 – DI – 9 before MCI↑ after LCRI↑
See Figure 2
LCRI hold time after MCI↑
See Figure 3
Data hold time, DI – 0 – DI – 9 valid after MCI↑ after LCRI↑
TA ≤ 25°C
TA = 85°C
tsu(3)
(3)
CI setup time before MCI↑
th(3)
CI hold time after MCI↑
tc
Clock cycle time
tw
High-level clock pulse width duration
ns
0.3
ns
0
ns
2
ns
ns
–1.1
See Figure 4
ns
LCRI
20
200
MCI
5
50
0.4 tc
0.6 tc
MCI, LCRI
0V
LCRI
0V
th(1)
0V
MCI
Figure 2. Clock Input Timing Requirements
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UNIT
0.5
–0.8
tsu(1)
8
MAX
2.5
LCRI
MCI
MIN
0V
ns
ns
SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
LCRI
0V
LCRI
tsu(1)
tsu(1)
MCI
DI–n
0V
0V
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
MCI
0V
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
th(2)
tsu(2)
1.4 V
1.4 V
DI–n
Figure 3. Data Input Timing Requirements
MCI
0V
MCI
0V
th(3)
tsu(3)
+100 mV
CI
–100 mV
+100 mV
CI
–100 mV
Figure 4. Cascade Input Timing Requirements
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9
SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
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PARAMETER
TEST CONDITIONS
VITH+
VITH–
Positive-going differential input voltage threshold
|VOD(SS)|
Steady-state differential output voltage magnitude
∆|VOD(SS)|
Change in steady-state differential output voltage
magnitude between logic states
VOC(SS)
Steady-stade common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output voltage
between logic states
VOC(PP)
Peak-to-peak change common-mode output voltage
Negative-going differential input voltage threshold
See Figure 5
See Figure 8
247
IID
II
Differential input current
mV
50
mV
1.125
1.375
–50
50
mV
50
150
mV
22
30
0.5
1
RL = 100 Ω,
340
35
(II+ – II–)
(LCRI, MCI inputs)
VIC = 0.05 V to 2.35 V,
VID = ±0.1 V
LCRI MCI inputs
LCRI,
VI = 0 V
VI = 2.4 V
–1.2
CI input
VI =0 V
VI = 2.4 V
– 2.4
IIH
IIL
High-level input current
EN, LVI, DI–n, LCO_EN
Low-level input current
EN, LVI, DI–n, LCO_EN
IOS
Short circuit output current
Short-circuit
DO LCO
DO,
IOZ
High-impedance output current
CI input
IO(OFF)
Power-off output current
CI
Input capacitance
LCRI, MCI inputs
† All typical values are at TA = 25°C and with VCC = 3.3 V.
10
POST OFFICE BOX 655303
65
3
4.4
mA
–2
2
µA
–2
– 20
–4
– 40
LCRI, MCI inputs
Power off output current
Power-off
20
VCC = 0 V ,
V
mA
VID = 0.4 V,
VIC = 2.2 V or 0.2 V
II(OFF)
mV
–50
(II+ – II–) (CI input)
Input current
UNIT
100
mV
f(MCI) = 200 MHz,
f(LCRI) = 20 MHz,
RL = 100 Ω,
DI–n= 1010101010
Supply current
MAX
454
Disabled
ICC
TYP†
–100
RL = 100 Ω,
Ω VID = ±100 mV
mV,
See Figures 6 and 7
Enabled,
MIN
36V
VI = 3.6
40
VIH = 2 V
VIL = 0.8 V
µA
A
µA
A
µA
20
µA
10
µA
VO+ or VO – = 0 V
VOD = 0 V
–10
10
–10
10
VO = 0 V or VCC
–5
5
µA
VCC = 1.5 V , VI = 3.6 V
VID = (0.4sin(4E6πt) + 0.5) V
–5
5
µA
• DALLAS, TEXAS 75265
3
mA
pF
SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
switching characteristics over recommended operating conditions (unless otherwise noted)
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PARAMETER
TEST CONDITIONS
td(1)
Propagation delay time
time, MCI↑ to DO↑
TA ≤ 25°C
TA = 85°C
td(2)
Propagation delay time
time, MCI↑ to DO↓
TA ≤ 25°C
TA = 85°C
td(3)
Propagation delay time
time, MCI↑ to LCO↑
TA ≤ 25°C
TA = 85°C
tr
tf
Differential output signal rise time
tsk(p)
tsk(pp)
Pulse skew (| tPHL – tPLH|), DO
tsk(ω)
tPZL
Multiple-frequency skew, LCO↑ to DO↑ or DO↓
tPLZ
tPHZ
Propagation delay time, low-level to high-impedance
Differential output signal fall time
RL = 100 Ω, CL = 10 pF,
F,
See Figure
9
g
MIN
TYP
MAX
3
5
5.8
3
5
6.1
3
5
5.8
3
5
6.1
3
5
5.8
3
5
6.1
0.3
ns
ns
ns
0.8
1.5
ns
RL = 100 Ω, CL = 10 pF,
F,
See Figure
10
g
0.3
0.8
1.5
ns
–250
0
250
ps
0
2.3
ns
See Figure 11
–250
0
250
ps
3
20
ns
3
10
ns
4
10
ns
Part-to-part output skew, Do
Propagation delay time, high-impedance to low-level
EN input
i
t to
t DO,
DO
LCO output
output, See Figure 12
Propagation delay time, high-level to high-impedance
POST OFFICE BOX 655303
UNIT
• DALLAS, TEXAS 75265
11
SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
PARAMETER MEASUREMENT INFORMATION
+
VID
–
VI+
(VI+ + VI–)/2
VIC
VI–
Figure 5. Receiver Voltage Definitions
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Table 3. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED
VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
VI+
1.25 V
VI–
1.15 V
VID
100 mV
VIC
1.2 V
1.15 V
1.25 V
–100 mV
1.2 V
2.4 V
2.3 V
100 mV
2.35 V
2.3 V
2.4 V
–100 mV
2.35 V
0.1 V
0V
100 mV
0.05 V
0V
0.1 V
–100 mV
0.05 V
1.5 V
0.9 V
600 mV
1.2 V
0.9 V
1.5 V
–600 mV
1.2 V
2.4 V
1.8 V
600 mV
2.1 V
1.8 V
2.4 V
–600 mV
2.1 V
0.6 V
0V
600 mV
0.3 V
0V
0.6 V
–600 mV
0.3 V
+
IO+
IO–
VOD
VO+
–
VO–
VOC
(VO+ + VO–)/2
Figure 6. Driver Voltage and Current Definitions
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
PARAMETER MEASUREMENT INFORMATION
3.74 kΩ
+
VOD
+
_
100 Ω
0 V ≤ Vtest ≤ 2.4 V
–
3.74 kΩ
Figure 7. VOD Test Circuit
49.9 Ω ±1% (2 PLCS)
VOC(PP)
+
VOC(SS)
VOC
–
50 pF
VOC
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
Pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP)
is made on test equipment with a –3 dB bandwidth of at least 5 GHz.
Figure 8. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
0V
MCI
td(1)
DO
td(2)
0V
DO
td(3)
LCO
0V
MCI
0V
td(3)
0V
LCO
0V
Figure 9. Output Timing Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
PARAMETER MEASUREMENT INFORMATION
0.4 V
MCI
DI (0–9)
LCRI
0V
–0.4 V
+
VOD
Logic
tPLH
100 Ω ±1%
tPHL
100%
80%
–
MCI
CL = 10 pF
(2 PLCS)
VOD(H)
DO, LCO
0V
DUT
VOD(L)
20%
0%
tr
tf
NOTE A: All input pulses are supplied by generators having the following characteristics: tr or tf ≤ 1 ns, MCI pulse repetition rate (PRR) = 50 Mpps,
MCI Pulse width = 10 ± 0.2 ns, LCRI pulse repetition rate (PRR) = 5 Mpps, LCRI pulse width = 100 ±20 ns. CL includes instrumentation
and fixture capacitance within 0,06 m of the D.U.T.
Figure 10. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
0V
LCO
tsk(ϖ)
DO
0V
Figure 11. LCO to DO Multiple-Frequency Skew Waveforms
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
PARAMETER MEASUREMENT INFORMATION
±1%
+
DI (0–9)
VOD
Logic
LCRI
–
MCI
50 Ω
±1%
+
_
1.2 V
CL = 10 pF
(2 PLCS)
DUT
2V
1.4 V
Input
0.8 V
≅ 0.34 V
0.1 V
0V
VOD
tPHZ
0V
–0.1 V
≅ –0.34 V
VOD
tPLZ
tPZL
Figure 12. Enable/Disable Time Waveforms
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
vs
FREQUENCY
I CC – Average Supply Current – mA
40
VCC = 3.3 V,
TA = 25°C
35
30
25
20
15
10
5
0
0
50
100
150
200
f – Frequency – Hz
Figure 13. Average Supply Current vs Frequency
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SN65LVDS151
MuxIt SERIALIZER-TRANSMITTER
SLLS444A – DECEMBER 2000
MECHANICAL INFORMATION
DA (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
38 PINS SHOWN
0,30
0,19
0,65
38
0,13 M
20
6,20
NOM
8,40
7,80
0,15 NOM
Gage Plane
1
19
0,25
A
0°–8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
30
32
38
A MAX
11,10
11,10
12,60
A MIN
10,90
10,90
12,40
DIM
4040066 / D 11/98
NOTES: A.
B.
C.
D.
16
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LVDS151DA
ACTIVE
TSSOP
DA
32
SN65LVDS151DAR
ACTIVE
TSSOP
DA
SN65LVDS151DARG4
ACTIVE
TSSOP
DA
46
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
32
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
32
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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