SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 D D D D D D D D D D SN65LVDS150 PW PACKAGE (Marked as 65LVDS150) A Member of the MuxIt SerializerDeserializer Building-Block Chip Family Pin Selectable Frequency Multiplier Ratios Between 4 and 40 Input Clock Frequencies From 5 to 50 MHz Multiplied Clock Frequencies up to 400 MHz Internal Loop Filters and Low PLL-Jitter of 20 ps RMS Typical at 200 MHz LVDS Compatible Differential Inputs and Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644-A LVTTL Compatible Inputs Are 5 V Tolerant LVDS Inputs and Outputs ESD Protection Exceeds 12 kV HBM Operates From a Single 3.3 V Supply Packaged in 28-Pin Thin Shrink Small-Outline Package With 26 mil Terminal Pitch VCC CRI+ CRI– VT GND M1 M2 M3 M4 M5 BSEL GND LCRO– LCRO+ 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 NC NC NC VCC GND NC GND NC MCO+ MCO– GND EN LCRO_EN LVO NC – No internal connection description The MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of differential transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS) data interface. The number of bits multiplexed per transmission line is user selectable, allowing for higher transmission efficiencies than with other existing fixed ratio solutions. Muxlt utilizes the LVDS (TIA/EIA-644) low voltage differential signaling technology for communications between the data source and data destination. The MuxIt family initially includes three devices supporting simplex communications; The SN65LVDS150 Phase Locked Loop-Frequency Multiplier, The SN65LVDS151 Serializer-Transmitter, and The SN65LVDS152 Receiver-Deserializer. The SN65LVDS150 is a PLL based frequency multiplier designed for use with the other members of the MuxIt family of serializers and deserializers. The frequency multiplication ratio is pin selectable over a wide range of values from 4 through 40 to accommodate a broad spectrum of user needs. No external filter components are needed. A PLL lock indicator output is available which may be used to enable link data transfers. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Muxlt is a trademark of Texas Instruments. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 description (continued) The design of the SN65LVDS150 allows it to be used at either the transmit end or the receive end of the MuxIt serial link. The differential clock reference input (CRI) is driven by the system’s parallel data clock when at the source end of the link, or by the link clock when at the destination end of the link. The differential clock reference input may be driven by either an LVDS differential signal, or by a single ended clock of either polarity. For single-ended use the nonclocked input is biased to the logic threshold voltage. A VCC/2 threshold reference, VT, is provided on a pin adjacent the differential CRI pins for convenience when the input is used in a single-ended mode. The multiplied clock output (MCO) is an LVDS differential signal used to drive the high-speed shift registers in either the SN65LVDS151 serializer-transmitter or the SN65LVDS152 receiver-deserializer. The link clock reference output (LCRO) is an LVDS differential signal provided to the SN65LVDS151 serializer-transmitter for transmission over the link. An internal power on reset and an enable input (EN) control the operation of the SN65LVDS150. When VCC is below 1.5 V, or when EN is low, the device is in a low power disabled state and the MCO and LCRO differential outputs are in a high-impedance state. When VCC is above 3 V and EN is high, the device and the two differential outputs are enabled and operating to specifications. The link clock reference output enable input (LCRO_EN) is used to turn off the LCRO output when it is not being used. A band select input (BSEL) is used to optimize the VCO performance as a function of M-clock frequencies and M multiplier that is being used: The fmax parameter in the switching characteristic table includes details on the MCO frequency and choices of BSEL and M. block diagram CRI+ Frequency Phase Detector CRI– VCO LVO MCO+ MCO– BSEL Ref. Gen. VT Divide by M M1 M2 M3 M4 M5 EN LCRO+ LCRO– LCRO_EN 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 frequency multiplier value table MULTIPLIER (m) M1 M2 M3 M4 4 L L L L L † L L L L H 6 L L L H L † L L L H H 8 L L H L L M5 9 L L H L H 10 L L H H L † L L H H H 12 L H L L L 13 L H L L H 14 L H L H L 15 L H L H H 16 L H H L L 17 L H H L H 18 L H H H L 19 L H H H H 20 H L L L L 22 H L L L 24 H L L 26 H L L 28 H L H 30 H L H 32 H L 34 H 36 H 38 H H 40 H H † H † † † † H = high level, RECOMMENDED fIN (MHz) BSEL = 0 BSEL = 1 fIN < 12.50 NA 12.50 ≤ fIN fIN < 8.33 NA 8.33 ≤ fIN fIN < 12.50 fIN < 11.11 12.50 ≤ fIN fIN < 10.00 NA NA NA 11.11 ≤ fIN 10.00 ≤ fIN NA fIN < 8.3 fIN < 7.7 8.3 ≤ fIN fIN < 7.14 fIN < 6.67 7.14 ≤ fIN fIN < 6.25 fIN < 5.88 6.25 ≤ fIN fIN < 5.56 fIN < 5.26 5.56 ≤ fIN 5.00 ≤ fIN H fIN = 5.00 NA H L NA 5.00 ≤ fIN H H NA 5.00 ≤ fIN L L NA 5.00 ≤ fIN L H NA 5.00 ≤ fIN H H L NA 5.00 ≤ fIN L H H H NA 5.00 ≤ fIN H L L L NA 5.00 ≤ fIN L L H NA 5.00 ≤ fIN L H L NA 5.00 ≤ fIN H L H H NA NA H H H L L NA NA H H H L H NA NA H H H H L NA NA H H H H H NA NA L= low level 7.7 ≤ fIN 6.67 ≤ fIN 5.88 ≤ fIN 5.26 ≤ fIN 5.00 ≤ fIN † = Reserved POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 equivalent input and output schematic diagrams VCC VCC 300 kΩ 300 kΩ 50 Ω MCO+, MCO–, LCRO+, LCRO– Output 10 kΩ CRI+ Input CRI– Input 4V 4V 4V VCC BSEL, LCRO_EN Only M1–M5, LCRO_EN, BSEL, or EN Input VCC 300 kΩ 50 Ω 400 Ω LVO Output 5V 6V 300 kΩ Mn, EN, Only 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 Terminal Functions TERMINAL I/O TYPE DESCRIPTION 11 I LVTTL Band select. Used to optimize VCO performance for minimum M-clock jitter: See recommended fmax in the frequency multiplier value table. CRI+, CRI– 2, 3 I LVDS Clock reference input. This is the reference clock signal for the PLL frequency multiplier. EN 17 I LVTTL Enable input. Used to disable the device to a low power state. A high level input enables the device, a low level input disables the device. 5, 12, 18, 22, 24 I NA 13, 14 O LVDS Link clock reference output. This is the data block synchronization clock signal from the PLL frequency multiplier. LCRO_EN 16 I LVTTL LCRO enable. Used to turn off the LCRO outputs when they are not used. A high level input enables the LCRO output; a low level input disables the LCRO output. LVO 15 O LVTTL Lock/valid output. This is signal required for proper Muxlt system operation. It is to be directly connected to the LVI inputs of SN65LVDS151 or SN65LVDS152 devices. It is used to inhibit the operation of those devices until after the PLL has stabilized. It remains at a low level following a reset until the PLL has become phase locked. A low to high-level transition indicates phase lock has occurred. M1–M5 6–10 I LVTTL Multiplier value selection inputs. These inputs determine the frequency multiplication ratio M. MCO–, MCO+ 19,20 O LVDS M-clock output. This is the high frequency multiplied clock output from the PLL frequency multiplier. It is used by the companion serializer or deserializer devices to synchronizes the transmission or reception of data NC 21, 23, 26–28 NA These pins are not connected and may be left open. 1, 25 NA Supply voltage 4 NA Voltage reference. A VCC/2 reference supplied for the unused CRI input when operated in a single-ended mode. NAME BSEL GND LCRO–, LCRO+ VCC VT NO. Circuit ground absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Voltage range: EN, BSEL, LCRO_EN, or M1–M5 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V CRI input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V LCRO±, MCO± outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Electrostatic discharge: Human body model (CRI±, LCRO±, MCO±,and GND (see Note 2) . . . . . . . . ±12 kV All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 kV Charged-device model (all pins) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65_C to 150_C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages, except differential I/O bus voltages, are with respect to the network ground terminal. 2. Tested in accordance with JEDEC Standard 22, Test method A114-B. 3. Tested in accordance with JEDEC Standard 22, Test method C101. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 85°C POWER RATING PW 1207 mW 9.6 mW/°C 628 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 recommended operating conditions MIN Supply voltage, VCC NOM 3 High-level input voltage, VIH Magnitude of differential input voltage, |VID| V 0.1 |V ID 2 CRI Operating free-air temperature, TA V 0.8 CRI Common-mode input voltage, VIC UNIT 3.6 2 EN LCRO EN M1 – M5 EN, BSEL BSEL, LCRO_EN, Low-level input voltage, VIL MAX 3.3 V 0.6 | 2.4 * V |V ID 2 | VCC – 0.8 85 – 40 V °C timing requirements MIN Input clock cycle time, tc(1) High-level input clock pulse width duration, tw(1) Input clock frequency, CRI, f(clock) 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 20 TYP 200 ns 0.4 tc(1) 0.6 tc(1) 5 50 MHz SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 electrical characteristics over recommended operating conditions (unless otherwise noted) ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ * ÁÁÁ ) ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ PARAMETER VIT+ TEST CONDITIONS Positive-going differential input threshold voltage MIN TYP† MAX UNIT 100 mV See Figure 1 and Table 1 VIT– Negative-going differential input threshold voltage |VOD(SS)| Steady-state differential output voltage magnitude RL = 100 Ω, See Figure 3 247 ∆|VOD(SS)| Change in steady-state differential output voltage magnitude between logic states VID = ±100 mV, See Figures 2 and 3 VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak change common-mode output voltage –100 mV 454 mV –50 50 mV 1.125 1.375 –50 50 mV 150 mV See Figure 4 340 50 VOH VOL High-level output voltage (LVO) Low-level output voltage (LVO) IOH = –8 mA IOL = 8 mA 2.4 V(T) Threshold reference bias voltage –100 µA ≤ IO ≤ 100 µA ICC Supply y current Enabled, RL = 100 Ω, CRI± open 25 70 Disabled 2.5 6 II Input current (CRI inputs) VI = 0 VI = 2.4 V I(ID) Differential input current (IIA – IIB) (CRI inputs) VIC = 0.05 V or 2.35 V, VID = ±0.1 V II(OFF) Power-off input current (CRI inputs) VCC = 0 V, M1–M5, EN Low level input current Low-level IOS Short-circuit output current MCO LCRO MCO, VO+ or = VO– = 0 V VOD = 0 V IOZ High-impedance output current MCO, LCRO IO(OFF) Power-off output current CI Input capacitance (CRI inputs) † All typical values are at TA = 25°C and with VCC = 3.3 V. CC 2 0.15 –2 –2 VI = 3.6 V IIL BSEL, LCRO_EN V 0.15 – 20 High level input current High-level M1–M5, EN CC 2 – 1.2 IIH BSEL, LCRO_EN V 0.4 V VIH = 2 V VIL = 0 0.8 8V V V V mA µA 2 µA 20 µA 20 –10 10 –20 µA µA –10 10 –10 10 VO = 0 V or VCC –5 5 µA VCC = 1.5 V , VO = 3.6 V VID =[(0.4sin(4E6πt) = 0.5] V –5 5 µA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 mA pF 7 SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 switching characteristics over recommended operating conditions (unless otherwise noted) ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PARAMETER MCO output clock period jjitter‡ t(lock) TEST CONDITIONS p–p EN = 1, LCRO_EN = 1, fI = 5 MHz rms Lock (stabilization time)§ tw(2) Multiplied clock output pulse width tr tf Differential output signal rise time (MCO, LCRO) t((OS)) td fmax Differential output signal fall time (MCO, LCRO) CRI↑ ↑ to MCO↑ ↑ offset time MCO↑ before b f LCRO↑ , titime delay fI = 5 MHz, M = 40 fI = 5 MHz, M = 4 fI = 10 MHz, M = 10 fI = 5 MHz, M = 40 Maximum MCO output frequency RL = 100 Ω, Ω See Figure 6 RL = 100 Ω, Ω See Figure 6 CL = 10 pF, pF CL = 10 pF, pF TYP† MAX 200 BSEL = 1, M = 40, RL = 100 Ω,, CL = 10 pF,, See Figure 5 fI = 5 MHz, M = 4 fI = 10 MHz, M = 10 MIN ps 20 0.2 1 0.3 0.6 0.6tc( 2) 1.5 0.3 0.6 1.5 –2.5 0 2.5 0.4tc(2) –1.5 0 1.5 –1.65 0 1.65 0.5 2.5 6 0.5 2.5 6 0.5 2.5 4.5 BSEL =1, M = 4, 6 200 BSEL =1, M ≠ 4, 6 400 BSEL =0, M = 4, 6 50 UNIT ms ns ns ns MHz BSEL =0, M ≠ 4, 6 100 † All typical values are at TA = 25°C and with VCC = 3.3 V. ‡ Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 10,000 cycles with a source having less than 10 psec jitter rms. § Lock time is measured from the application of the clock reference input signal to the assertion of a high-level lock/valid output. PARAMETER MEASUREMENT INFORMATION + VID – (VI+ + VI–)/2 VI+ VIC VI– Figure 1. Receiver Input Voltage Definitions 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 PARAMETER MEASUREMENT INFORMATION ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMONMODE INPUT VOLTAGE V(IA) 1.25 V V(IB) 1.15 V VID 100 mV VIC 1.2 V 1.15 V 1.25 V –100 mV 1.2 V 2.4 V 2.3 V 100 mV 2.35 V 2.3 V 2.4 V –100 mV 2.35 V 0.1 V 0V 100 mV 0.05 V 0V 0.1 V –100 mV 0.05 V 1.5 V 0.9 V 600 mV 1.2 V 0.9 V 1.5 V –600 mV 1.2 V 2.4 V 1.8 V 600 mV 2.1 V 1.8 V 2.4 V –600 mV 2.1 V 0.6 V 0V 600 mV 0.3 V 0V 0.6 V –600 mV 0.3 V IO+ + IO– VOD VO+ – VO– VOC (VO++VO–)/2 Figure 2. Driver Output Voltage and Current Definitions 3.75 kΩ + VOD + _ 100 Ω 0 V ≤ Vtest ≤ 2.4 V – 3.75 kΩ Figure 3. VOD Test Circuit 49.9 Ω ±1% (2 PLCS) VOC(PP) + VOC(SS) VOC – 50 pF VOC NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, Pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 5 GHz. Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 PARAMETER MEASUREMENT INFORMATION + 100% 80% Output VOD(H) 100 Ω ±1% VOD 0V – VOD(L) CL = 10 pF (2 PLCS) 20% 0% tf tr NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, Pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 5. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal CRI 0V t(OS) 0V MCO td LCRO 0V Figure 6. Output Timing Waveform Definitions TYPICAL CHARACTERISTICS JITTER vs MCO FREQUENCY SUPPLY CURRENT vs MCO FREQUENCY 400 80 M = 20 70 350 M=4 60 MCO Jitter – psp–p I CC – Supply Current – mA M = 10 M=4 50 40 M = 40 30 300 250 200 100 10 50 50 100 150 200 250 300 350 400 M = 20 150 20 0 0 M = 10 0 0 M = 40 50 MCO Frequency – MHz Figure 7 Figure 8 NOTE: M = Multiplying Value (see Page 3) 10 100 150 200 250 300 MCO Frequency – MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 350 400 SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 TYPICAL CHARACTERISTICS basic applications examples Parallel data path width between 4 and 10 bits, only one LVDS data link required. Data and Clock Input GND – + + DI0–DI9 CI LCRI EN SN65LVDS151 MuxIt Serializer-Transmitter LCO DO EN EN LCO – + – LCRO + M5 M4 M3 M2 M1 VT + CRI SN65LVDS150 MuxIt PLL Frequency Multiplier MCI LVI + – – – CI + LVO LCRO EN EN MCO – – VCC BSEL + VCC LVDS Serial Link, 1 Data + Clock GND + CO – – EN CO EN + – LCI + + DI LCRO LVI SN65LVDS150 MuxIt PLL Frequency Multiplier LCRO LVO EN EN MCO BSEL SN65LVDS152 MuxIt Receiver-Deserializer DO0–DO9 DCO MCI + – – M5 M4 M3 M2 M1 VT – – + CRI + GND Data and Clock Output (a) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 TYPICAL CHARACTERISTICS Parallel data path width between 11 and 20 bits, aggregate data rate low enough to allow transmission over one LVDS data link, sharing of PLL-FM between serializer-transmitter and receiver-deserializer chips at each end. Data and Clock Input VCC GND – + – DI0–DI9 CI LCRI EN SN65LVDS151 MuxIt Serializer-Transmitter LCO EN EN LCO DO – + – MCI + + DI0–DI9 CI LCRI EN SN65LVDS151 MuxIt Serializer-Transmitter ST–A LVI CI + – LCO EN EN LCO DO + – + – + – MCI + + – CRI SN65LVDS150 MuxIt PLL Frequency Multiplier ST–B LVO CI M5 M4 M3 M2 M1 VT LCRO EN EN MCO – + – VCC LCRO LVI + – BSEL + – GND VCC LVDS Serial Link, 1 Data + Clock GND + CO VCC – – EN CO EN + – LCI DI SN65LVDS152 MuxIt Receiver-Deserializer DO0–DO9 DCO + RD–A MCI + LVI + CO – – EN CO EN + – LCI DI SN65LVDS152 MuxIt Receiver-Deserializer DO0–DO9 DCO RD–B MCI + – + LVI – + LCRO M5 M4 M3 M2 M1 VT SN65LVDS150 MuxIt PLL Frequency Multiplier LCRO LVO EN EN MCO BSEL – – GND Data and Clock Output 12 POST OFFICE BOX 655303 (b) • DALLAS, TEXAS 75265 + – + CRI SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 TYPICAL CHARACTERISTICS Parallel data path width between 11 and 20 bits, aggregate data rate requires transmission over two separate LVDS data links, sharing of PLL-FM between serializer-transceiver and receiver-deserializer chips at each end. Data and Clock Input GND GND – + – DI0–DI9 CI LCRI EN SN65LVDS151 ST–A MuxIt Serializer-Transmitter LCO EN EN LCO DO – + – MCI LVI + + – CI LCRI EN SN65LVDS151 ST–B MuxIt Serializer-Transmitter LCO EN EN LCO DO – + DI0–DI9 CI + + – + GND – MCI LVI + + – LCRO M5 M4 M3 M2 M1 VT + CRI SN65LVDS150 MuxIt PLL Frequency Multiplier LCRO LVO EN EN CI + – – MCO – – VCC BSEL + VCC LVDS Serial Link, 2 Data + Clock GND + CO GND – – EN CO EN + – LCI DI SN65LVDS152 MuxIt Receiver-Deserializer DO0–DO9 DCO + RD–A MCI + LVI + – – CO EN CO EN + – LCI + DI SN65LVDS152 RD–B MuxIt Receiver-Deserializer DO0–DO9 DCO MCI + – LVI + – – LCRO M5 M4 M3 M2 M1 VT + CRI SN65LVDS150 MuxIt PLL Frequency Multiplier LCRO LVO EN EN MCO BSEL – – + GND Data and Clock Output POST OFFICE BOX 655303 (c) • DALLAS, TEXAS 75265 13 SN65LVDS150 MuxIt PLL FREQUENCY MULTIPLIER SLLS443 – DECEMBER 2000 MECHANICAL INFORMATION PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. 14 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 11-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LVDS150PW ACTIVE TSSOP PW 28 50 None CU NIPDAU Level-2-220C-1 YEAR SN65LVDS150PWR ACTIVE TSSOP PW 28 2000 None CU NIPDAU Level-2-220C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. 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