ETC NRF2401

PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
Q5)
Single chip 2.4 GHz Transceiver
)($785(6
$33/,&$7,216
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
True single chip GFSK transceiver in a small
24-pin package (QFN24 5x5mm)
Data rate 0 to1Mbps
Only 2 external components
Multi channel operation
• 125 channels
• Channel switching time <200µs.
• Support frequency hopping
Data slicer / clock recovery of data
Address and CRC computation
DuoCeiver™ for simultaneous dual receiver
topology
ShockBurst™ mode for ultra-low power
operation and relaxed MCU performance
Power supply range: 1.9 to 3.6 V
Low supply current (TX), typical 10.5mA peak
@ -5dBm output power
Low supply current (RX), typical 18mA peak in
receive mode
100% RF tested
No need for external SAW filter
World wide use
•
•
•
•
•
•
•
•
•
•
•
Wireless mouse, keyboard, joystick
Keyless entry
Wireless data communication
Alarm and security systems
Home automation
Home automation
Surveillance
Automotive
Telemetry
Intelligent sports equipment
Industrial sensors
Toys
*(1(5$/'(6&5,37,21
nRF2401 is a single-chip radio transceiver for the world wide 2.4 - 2.5 GHz ISM
band. The transceiver consists of a fully integrated frequency synthesizer, a power
amplifier, a crystal oscillator and a modulator. Output power and frequency channels
are easily programmable by use of the 3-wire serial interface. Current consumption is
very low, only 10.5mA at an output power of -5dBm and 18mA in receive mode.
Built-in Power Down modes makes power saving easily realizable.
48,&.5()(5(1&('$7$
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Minimum supply voltage
Maximum output power
Maximum data rate
Supply current in transmit @ -5dBm output power
Supply current in receive mode
Temperature range
Sensitivity
Supply current in Power Down mode
9DOXH
8QLW
1.9
0
1000
10.5
18
-40 to +85
-90
1
V
dBm
kbps
mA
mA
°C
dBm
µΑ
Table 1 nRF2401 quick reference data
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
7\SH1XPEHU
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NRF2401 IC
NRF2401-EVKIT
24 pin QFN 5x5
Evaluation kit (2 test PCB, 2 configuration PCB, SW)
A
1.0
Table 2 nRF2401 ordering information
VSS=0V
VSS=0V
VSS=0V
VSS=0V
VDD=3V
VSS=3V
VDD=3V
DVDD
%/2&.',$*5$0
XC1
PWR_UP
DuoCeiverTM
VSS=0V
ShockBurstTM
XC2
DEMOD
CE
DR2
Data
Channel 2
DOUT2
CLK2
DR1
Data
Channel 1
DATA
CLK1
3-wire
interface
Clock
Recovery,
DataSlicer
ADDR
Decode
CRC
Code/Decode
FIFO
In/Out
IF BPF
VSS_PA=0V
VDD_PS=1.8V
LNA
Frequency
Synthesiser
ANT1
GFSK
Filter
PA
400Ω
ANT2
CS
IREF
22kΩ
Figure 1 nRF2401 with external components.
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
3,1)81&7,216
3LQ
1DPH
3LQIXQFWLRQ
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1
2
3
4
5
6
7
CE
DR2
CLK2
DOUT2
CS
DR1
CLK1
Digital Input
Digital Output
Digital I/O
Digital Output
Digital Input
Digital Output
Digital I/O
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DATA
DVDD
VSS
XC2
XC1
VDD_PA
ANT1
ANT2
VSS_PA
VDD
VSS
IREF
VSS
VDD
VSS
PWR_UP
VDD
Digital I/O
Power
Power
Analog Output
Analog Input
Power Output
RF
RF
Power
Power
Power
Analog Input
Power
Power
Power
Digital Input
Power
Chip Enable Activates RX or TX mode
RX Data Ready at Data Channel 2 (ShockBurst™ only)
Clock Output/Input for RX Data Channel 2
RX Data Channel 2
Chip Select Activates Configuration Mode
RX Data Ready at Data Channel 1 (ShockBurst™ only)
Clock Input (TX) & Output/Input (RX) for Data Channel 1
3-wire interface
RX Data Channel 1/TX Data Input/ 3-wire interface
Positive Digital Supply output for decoupling purposes
Ground (0V)
Crystal Pin 2
Crystal Pin 1
Power Supply (+1.8V) to Power Amplifier
Antenna interface 1
Antenna interface 2
Ground (0V)
Power Supply (+3V DC)
Ground (0V)
Reference current
Ground (0V)
Power Supply (+3V DC)
Ground (0V)
Power Up
Power Supply (+3V DC)
Table 3 nRF2401 pin function
3,1$66,*10(17
VDD PWR_UP
VSS
VDD
VSS
IREF
24
22
21
20
19
23
18
VSS
17
VDD
3
16
VSS_PA
4
15
ANT2
CS
5
14
ANT1
DR1
6
13
VDD_PA
CE
1
DR2
2
CLK2
DOUT2
Q5)
QFN24 5x5
7
8
9
10
11
12
CLK1
DATA
DVDD
VSS
XC2
XC1
Figure 2. nRF2401 pin assignment (top view) for a QFN24 5x5 package.
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
(/(&75,&$/63(&,),&$7,216
Conditions: VDD = +3V, VSS = 0V, TA = - 40ºC to + 85ºC
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1RWHV
0LQ
7\S
0D[
8QLWV
1.9
-40
3.0
+27
3.6
+85
V
ºC
VDD- 0.3
Vss
VDD
0.3
V
V
VDD- 0.3
Vss
VDD
0.3
V
V
1)
2)
2400
4
2524
20
3)
>0
250
MHz
MHz
kHz
kbps
kbps
MHz
2SHUDWLQJFRQGLWLRQV
VDD
TEMP
Supply voltage
Operating Temperature
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VIH
VIL
HIGH level input voltage
LOW level input voltage
'LJLWDORXWSXWSLQ
VOH
VOL
HIGH level output voltage (IOH=-0.5mA)
LOW level output voltage (IOL=0.5mA)
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fOP
fXTAL
∆f
RGFSK
RGFSK
FCHANNEL
Operating frequency
Crystal frequency
Frequency deviation
Data rate ShockBurst™
Data rate Direct Mode
Channel spacing
±156
1000
1000
1
7UDQVPLWWHURSHUDWLRQ
PRF
PRFC
PRFCR
PBW
PRF2
PRF3
IVDD
IVDD
IVDD
IVDD
IVDD
Maximum Output Power
RF Power Control Range
RF Power Control Range Resolution
20dB Bandwidth for Modulated Carrier
2nd Adjacent Channel Transmit Power 2MHz
3rd Adjacent Channel Transmit Power 3MHz
Supply current @ 0dBm output power
Supply current @ -20dBm output power
Average Supply current @ -5dBm output
power, ShockBurst™
Average Supply current in stand-by mode
Average Supply current in power down
4)
0
20
5)
5)
6)
13
8.8
0.8
dBm
dB
dB
kHz
dBm
dBm
mA
mA
mA
7)
12
1
µA
µA
16
+4
±3
1000
-20
-40
5HFHLYHURSHUDWLRQ
IVDD
Supply current one channel 250kbps
18
mA
IVDD
Supply current one channel 1000kbps
19
mA
IVDD
Supply current two channels 250kbps
23
mA
IVDD
Supply current two channels 1000kbps
25
mA
RXSENS Sensitivity at 0.1%BER (@250kbps)
-90
dBm
RXSENS Sensitivity at 0.1%BER (@1000kbps)
-80
dBm
C/ICO
C/I Co-channel
6
dB
C/I1ST
1st Adjacent Channel Selectivity C/I 1MHz
-1
dB
C/I2ND
2nd Adjacent Channel Selectivity C/I 2MHz
-16
dB
C/I3RD
3rd Adjacent Channel Selectivity C/I 3MHz
-26
dB
RXB
Blocking Data Channel 2
-41
dB
1) Usable band is determined by local regulations
2) The crystal frequency may be chosen from 5 different values (4, 8, 12, 16, and 20MHz) which are specified in
the configuration word, see Table 8. 16MHz are required for 1Mbps operation.
3) Data rate must be either 250kbps or 1000kbps.
4) De-embedded Antenna load impedance = 400 Ω
5) De-embedded Antenna load impedance = 400 Ω. Effective data rate 250kbps or 1Mbps.
6) De-embedded Antenna load impedance = 400 Ω. Effective data rate 10kbps.
7) Current if 4 MHz crystal is used.
Table 4 nRF2401 RF specifications
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
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nRF2401 uses the QFN 24LD 5x5 package. Dimensions are in mm.
3DFNDJH7\SH
QFN24
(5x5 mm)
0LQ
W\S
0D[
$
$
$
E
0.8
0.0
0.75
1
0.05
1
0.25
0.3
0.35
'
5 BSC
(
5 BSC
H
-
.
/
0.65 BSC
3.47
3.57
3.67
3.47
3.57
3.67
0.35
0.4
0.45
Figure 3 nRF2401 package outline.
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
$EVROXWH0D[LPXP5DWLQJV
6XSSO\YROWDJHV
VDD ............................- 0.3V to + 3.6V
VSS .................................................. 0V
,QSXWYROWDJH
VI .......................- 0.3V to VDD + 0.3V
2XWSXWYROWDJH
VO ......................- 0.3V to VDD + 0.3V
7RWDO3RZHU'LVVLSDWLRQ
PD (TA=85°C).............................. 90mW
7HPSHUDWXUHV
Operating Temperature…. - 40°C to + 85°C
Storage Temperature….… - 40°C to + 125°C
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GDPDJHWRWKHGHYLFH
$77(17,21
Electrostatic Sensitive Device
Observe Precaution for handling.
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
*ORVVDU\RI7HUPV
7HUP
'HVFULSWLRQ
CLK
CRC
CS
CE
DR
GFSK
ISM
MCU
OD
PWR_DWN
PWR_UP
RX
ST_BY
TX
Clock
Cyclic Redundancy Check
Chip Select
Chip Enable
Data Ready
Gaussian Frequency Shift Keying
Industrial-Scientific-Medical
Micro controller
Overdrive
Power Down
Power Up
Receive
Standby
Transmit
Table 5 Glossary
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
02'(62)23(5$7,21
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The nRF2401 can be set in the following main modes depending on three control
pins:
0RGH
Active (RX/TX)
Configuration
Stand by
Power down
PWR_UP
CE
CS
1
1
1
0
1
0
0
X
0
1
0
X
Table 6 nRF2401 main modes
For a complete overview of the nRF2401 I/O pins in the different modes please refer
to Table 7.
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The nRF2401 has two active (RX/TX) modes:
•
•
ShockBurst™
Direct Mode
The device functionality in these modes is decided by the content of a configuration
word. This configuration word is presented in configuration section.
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
6KRFN%XUVWŒ
The ShockBurst™ technology uses on-chip FIFO to clock in data at a low data rate
and transmit at a very high rate thus enabling extremely power reduction.
When operating the nRF2401 in ShockBurst™, you gain access to the high data rates
(1 Mbps) offered by the 2.4 GHz band without the need of a costly, high-speed micro
controller (MCU) for data processing.
By putting all high speed signal processing related to RF protocol on-chip, the
nRF2401 offers the following benefits:
•
•
•
Highly reduced current consumption
Lower system cost (facilitates use of less expensive micro controller)
Greatly reduced risk of ‘on-air’ collisions due to short transmission time
The nRF2401 can be programmed using a simple 3-wire interface where the data rate
is decided by the speed of the micro controller.
By allowing the digital part of the application to run at low speed while maximizing
the data rate on the RF link, the nRF ShockBurst™ mode reduces the average current
consumption in applications considerably.
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When the nRF2401 is configured in ShockBurst™, TX or RX operation is conducted
in the following way (10 kbps for the example only).
Q5)
Continuous 10kbps
ELW
0&8
FIFO
ShockBurstTM
1Mbps
Figure 4 Clocking in data with MCU and sending with ShockBurst technology
Without ShockBurstTM, running at speed dictated by 10Kbs MCU
10mA periode
10mA period
0
20
40
60
10Kbs MCU with ShockBurstTM
80
100
140
120
160
180
200
220
Time mS
Figure 5 Current consumption with & without ShockBurst technology
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240
PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
NO
nRF2401 in
ShockBurstTM
TX (CE=hi)?
YES
Data content of registers:
uController
Loading ADDR
and PAYLOAD
data
ADDR
PAYLOAD
Maximum 256 bits
nRF2401
Calculating CRC
ADDR
PAYLOAD
CRC
NO
CE=Low?
YES
nRF2401
Adding Preamble
nRF2401
Sending
ShockBurstTM
Package
(250 or 1000kbps)
YES
Preamble
ADDR
PAYLOAD
CRC
Input FIFO not Empty
NO
Sending
completed?
Figure 6 Flow Chart ShockBurst™ Transmit of nRF2401
Q5)6KRFN%XUVWŒ7UDQVPLW
MCU interface pins: CE, CLK1, DATA
1. When the application MCU has data to send, set CE high. This activates
RF2401 on-board data processing.
2. The address of the receiving node (RX address) and payload data is
clocked into the nRF2401. The application protocol or MCU sets the speed
<1Mbps (ex: 10kbps).
3. MCU sets CE low, this activates a nRF2401 ShockBurst™ transmission.
4. nRF2401 ShockBurst™:
• RF front end is powered up
• RF package is completed (preamble added, CRC calculated)
• Data is transmitted at high speed (250 kbps or 1 Mbps configured
by user).
• nRF2401 return to stand-by when finished
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
nRF2401 in
ShockBurstTM
RX?
NO
YES
Data content of registers:
nRF2401
Detects
PREAMBLE and
Incoming Data
Preamble
ADDR
PAYLOAD
CRC
NO
Correct
ADDR?
ADDR
PAYLOAD
CRC
ADDR
PAYLOAD
CRC
ADDR
PAYLOAD
CRC
YES
nRF2401
Receives Data
and
Checking CRC
NO
nRF2401
Checks:
Correct CRC?
YES
nRF2401
Set Data Ready
(DR1/2) high
PAYLOAD
uController
Clocks out
Payload
PAYLOAD
NO
nRF2401
Register
Empty?
YES
nRF2401
Sets Data Ready
(DR1/2) low
Output Register Empty
Figure 7 Flow Chart ShockBurst™ Receive of nRF2401
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
Q5)6KRFN%XUVWŒ5HFHLYH
MCU interface pins: CE, DR1, CLK1 and DATA (one RX channel receive)
1. Correct address and size of payload of incoming RF packages are set when
nRF2401 is configured to ShockBurst™ RX.
2. To activate RX, set CE high.
3. After 200 µs settling, nRF2401 is monitoring the air for incoming
communication.
4. When a valid package has been received (correct address and CRC found),
nRF2401 removes the preamble, address and CRC bits.
5. nRF2401 then notifies (interrupts) the MCU by setting the DR1 pin high.
6. MCU may (or may not) set the CE low to disable the RF front end (low
current mode).
7. The MCU will clock out just the payload data at a suitable rate (ex. 10
kbps).
8. When all payload data is retrieved nRF2401 sets DR1 low again, and is
ready for new incoming data package if CE is kept high during data
download. If the CE was set low, a new start up sequence can begin, see
Figure 16.
'LUHFW0RGH
In direct mode the nRF2401 works like a traditional RF device. Data must be at
1Mbps, or 250kbps at low data rate setting, for the receiver to detect the signals.
'LUHFW0RGH7UDQVPLW
MCU interface pins: CE, DATA
1. When application MCU has data to send, set CE high
2. The nRF2401 RF front end is now immediately activated, and after 200 µs
settling time, data will modulate the carrier directly.
3. All RF protocol parts must hence be implemented in MCU firmware
(preamble, address and CRC).
'LUHFW0RGH5HFHLYH
MCU interface pins: CE, CLK1, and DATA
1. Once the nRF2401 is configured and powered up (CE high) in direct RX
mode, DATA will start to toggle due to noise present on the air.
2. CLK1 will also start to toggle as nRF2401 is trying to lock on to the
incoming data stream.
3. Once a valid preamble arrives, CLK1 and DATA will lock on to the
incoming signal and the RF package will appear at the DATA pin with the
same speed as it is transmitted.
4. To enable the demodulator to re-generate the clock, the preamble must be
8 bits toggling hi-low, starting with low if the first data bit low.
5. In this mode no data ready (DR) signals is available. Address and
checksum verification must also be done in the receiving MC.
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
'XR&HLYHUŒ6LPXOWDQHRXV7ZR&KDQQHO5HFHLYH0RGH
In both ShockBurst™ & Direct modes the nRF2401 can facilitate simultaneous
reception of two parallel independent frequency channels at the maximum data rate.
This means:
• nRF2401 can receive data from two 1 Mbps transmitters (ex: nRF2401 or
nRF2402) 8 MHz (8 frequency channels) apart through one antenna
interface.
• The output from the two data channels is fed to two separate MCU
interfaces.
• Data channel 1: CLK1, DATA, and DR1
• Data channel 2: CLK2, DOUT2, and DR2
• DR1 and DR2 are available only in ShockBurst™.
The nRF2401 DuoCeiver™ technology provides 2 separate dedicated data channels
for RX and replaces the need for two, stand alone receiver systems.
Q5)
7[5[
Q5)
7[5[
Q5)
7[5[
Figure 8 Simultaneous 2 channel receive on nRF2401
There is one absolute requirement for using the second data channel. For the nRF2401
to be able to receive at the second data channel the frequency channel must be 8MHz
higher than the frequency of data channel 1. The nRF2401 must be programmed to
receive at the frequency of data channel 1. No time multiplexing is used in nRF2401
to fulfil this function. In direct mode the MCU must be able to handle two
simultaneously incoming data packets if it is not multiplexing between the two data
channels. In ShockBurst™ it is possible for the MCU to clock out one data channel at
a time while data on the other data channel waits for MCU availability, without any
lost data packets, and by doing so reduce the needed performance of the MCU.
FRF1
Clock
Recovery,
DataSlicer
ADDR,
CRC
Check
DR1
CLK1
DATA
Data(FRF1)
FRF2=FRF1+8MHz
Clock
Recovery,
DataSlicer
ADDR,
CRC
Check
DR2
CLK2
DOUT2
Data(FRF2)
Figure 9 DuoCeiverTM with two simultaneously independent receive channels.
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
&RQILJXUDWLRQ0RGH
In configuration mode a configuration word of up to 15 bytes is downloaded to
nRF2401. This is done through a simple 3-wire interface (CS, CLK1 and DATA). For
more information on configuration please refer to the nRF2401 Device configuration
chapter on page16.
6WDQG%\0RGH
Stand by mode is used to minimize average current consumption while maintaining
short start up times. In this mode, part of the crystal oscillator is active. Current
consumption is dependent on crystal frequency (Ex: 12 µA @ 4 MHz, 32 µA @ 16
MHz). The configuration word content is maintained during stand by.
3RZHU'RZQ0RGH
In power down the nRF2401 is disabled with minimal current consumption, typically
less than 1µA. Entering this mode when the device is not active minimizes average
current consumption, maximizing battery lifetime. The configuration word content is
maintained during power down.
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
3LQFRQILJXUDWLRQIRUWKHGLIIHUHQWPRGHVRIQ5)
,13873,16
Q5)
02'(6
3:5B83
&(
%,',53,16
&6
Power down
0
0
X
1
0
0
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
0
0
Stand by
Configuration
TX ShockBurst™
TX Direct
RX ShockBurst™
in one channel
RX ShockBurst™
in two channels
RX Direct
in one channel
RX Direct
in two channels
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In
X
In
X
In
CLK
In
CLK
In
Set to 0
In
CLK
In
CLK
Out
CLK
Out
CLK
In
X
In
X
In
CONFIG DATA
In
DATA
In
DATA
Out
DATA
Out
DATA
Out
DATA
Out
DATA
In
X
In
X
In
CLK
In
X
In
CLK
In
CLK
In
CLK
Out
0
Out
CLK
Table 7 Pin configuration of nRF2401.
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2873873,16
'5
'5
'287
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DR1
0
0
DR1
DR2
DATA
0
DR1
0
DR2
0
DATA
PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
'(9,&(&21),*85$7,21
All configuration of the nRF2401 is done via a 3-wire interface to a single
configuration register. The configuration word can be up to 15 bytes long for
ShockBurst™ use and up to 2 bytes long for direct mode.
&RQILJXUDWLRQIRU6KRFN%XUVWŒRSHUDWLRQ
The configuration word in ShockBurst™ enables the nRF2401 to handle the RF
protocol. Once the protocol is completed and loaded into nRF2401 only one byte,
bit[7:0], needs to be updated during actual operation.
The configuration blocks dedicated to ShockBurst™ is as follows:
• Payload section width: Specifies the number of payload bits in a RF package.
This enables the nRF2401 to distinguish between payload data and the CRC
bytes in a received package.
• Address width: Sets the number of bits used for address in the RF package.
This enables the nRF2401 to distinguish between address and payload data.
• Address (RX Channel 1 and 2): Destination address for received data.
• CRC: Enables nRF2401 on-chip CRC generation and de-coding.
NOTE:
These configuration blocks, with the exception of the CRC, are dedicated for the
packages that a nRF2401 is to receive.
In TX mode, the MCU must generate an address and a payload section that fits the
configuration of the nRF2401 that is to receive the data.
When using the nRF2401 on-chip CRC feature ensure that CRC is enabled and uses
the same length for both the TX and RX devices.
PRE-AMBLE
ADDRESS
PAYLOAD
CRC
Figure 10 Data packet set-up
&RQILJXUDWLRQIRU'LUHFW0RGHRSHUDWLRQ
For direct mode operation only the two first bytes (bit[15:0]) of the configuring word
are relevant.
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
&RQILJXUDWLRQ:RUGRYHUYLHZ
*HQHUDOGHYLFHFRQILJXUDWLRQ
6KRFN%XUVWŒFRQILJXUDWLRQ
%LW
1XPEHU
SRVLWLRQ RIELWV
1DPH
)XQFWLRQ
143:120
24
TEST
Reserved for testing
119:112
8
DATA2_W
Length of data payload section RX channel 2
111:104
8
DATA1_W
Length of data payload section RX channel 1
103:64
40
ADDR2
Up to 5 byte address for RX channel 2
63:24
40
ADDR1
Up to 5 byte address for RX channel 1
23:18
6
ADDR_W
Number of address bits (both RX channels).
17
1
CRC_L
8 or 16 bit CRC
16
1
CRC_EN
Enable on-chip CRC generation/checking.
15
1
RX2_EN
Enable two channel receive mode
14
1
CM
Communication mode (Direct or ShockBurst™)
13
1
RFDR_SB
RF data rate (1Mbps requires 16MHz crystal)
12:10
3
XO_F
Crystal frequency
9:8
2
RF_PWR
RF output power
7:1
7
RF_CH#
Frequency channel
0
1
RXEN
RX or TX operation
Table 8 Table of configuration words.
The configuration word is shifted in MSB first on positive CLK1 edges. New
configuration is enabled on the falling edge of CS.
NOTE.
On the falling edge of CS, the nRF2401 updates the number of bits actually shifted in
during the last configuration.
Ex:
If the nRF2401 is to be configured for 2 channel RX in ShockBurst™, a total of 120
bits must be shifted in during the first configuration after VDD is applied.
Once the wanted protocol, modus and RF channel are set, only one bit (RXEN) is
shifted in to switch between RX and TX.
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
&RQILJXUDWLRQ:RUG'HWDLOHG'HVFULSWLRQ
The following describes the function of the 144 bits (bit 143 = MSB) that is used to
configure the nRF2401.
General Device Configuration: bit[15:0]
ShockBurst™ Configuration: bit[119:0]
Test Configuration: bit[143:120]
MSB
D143
D142
D141
1
0
0
TEST
D140
D139
D138
Reserved for testing
0
1
1
D137
D136
1
0
MSB
D135
0
TEST
D134
D133
0
D119
0
D111
0
D132
0
1
D130
0
D129
D128
DATA1_W
D110
D109
D108
D107
D106
D105
Data width channel#1 in # of bits excluding addr/crc
0
1
0
0
0
0
D101
0
0
0
D62
….
…
D61
0
….
0
…
D127
Reserved for testing
0
0
0
DATA2_W
D118
D117
D116
D115
D114
D113
Data width channel#2 in # of bits excluding addr/crc
0
1
0
0
0
0
D102
0
D131
0
D103
D63
D13
OD
0
D125
D124
D123
D122
D121
D120
Close PLL in TX
0
0
1
1
1
0
0
Default
0
D104
Default
0
ADDR1
D31
D30
D29
D28
Channel#1 Address RX (up to 40bit)
1
1
1
0
D67
D66
D65
D64
0
1
1
1
D27
D26
D25
D24
0
1
1
1
Default
Default
Default
Default
LSB
RF-Programming
D12
D11
D10
D9
D8
XO Frequency
RF Power
0
1
1
1
1
D7
D6
0
0
D5
D4
D3
Channel selection
0
0
0
D2
D1
1
0
D0
RXEN
0
Table 9 Configuration data word
The MSB bit should be loaded first into the configuration register.
Default configuration word: h8E08.1C20.2000.0000.00E7.0000.0000.E721.0F04.
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Revision: 1.0
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Default
D112
CRC
D17
D16
CRC Mode 1 = 16bit, 0 = 8bit
CRC 1 = enable; 0 = disable
0
1
D14
BUF
0
D126
ADDR2
D71
D70
D69
D68
Channel#2 Address RX (up to 40bit)
1
1
1
0
ADDR_W
D23
D22
D21
D20
D19
D18
Address width in # of bits (both channels)
0
0
1
0
0
0
D15
Two Ch.
0
Default
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
6KRFN%XUVWŒFRQILJXUDWLRQ
The section B[119:16] contains the segments of the configuration register dedicated to
ShockBurst™ operational protocol. After VDD is turned on ShockBurst™
configuration is done once and remains set whilst VDD is present. During operation
only the first byte for frequency channel and RX/TX switching need to be changed.
3//B&75/
3//B&75/
'
'
3//
0
0
1
1
0
1
0
1
Open TX/Closed RX
Open TX/Open RX
Closed TX/Closed RX
Closed TX/Open RX
Table 10 PLL setting.
Bit 121-120:
PLL_CTRL: Controls the setting of the PLL for test purposes. With closed
PLL in TX no deviation will be present.
'$7$[B:
'$7$B:
119
118
117
111
110
109
116
115
114
113
112
106
105
104
'$7$B:
108
107
Table 11 Number of bits in payload.
Bit 119 – 112:
DATA2_W: Length of RF package payload section for receive-channel 2.
Bit 111 – 104:
DATA1_W: Length of RF package payload section for receive-channel 1.
NOTE:
The total number of bits in a ShockBurst™ RF package may not exceed 256!
Maximum length of payload section is hence given by:
'$7$[ _ : (ELWV ) = 256 − $''5 _ : − &5&
Where:
ADDR_W: length of RX address set in configuration word B[23:18]
CRC: check sum, 8 or 16 bits set in configuration word B[17]
PRE: preamble, 4 or 8 bits are automatically included
Shorter address and CRC leaves more room for payload data in each package.
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Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
$''5[
$''5
103
102
101
….
71
70
63
62
61
….
31
30
69
68
67
66
65
64
28
27
26
25
24
ADDR1
29
Table 12 Address of receiver #2 and receiver #1.
Bit 103 – 64:
ADDR2: Receiver address channel 2, up to 40 bit.
Bit 63 – 24: ADDR1
ADDR1: Receiver address channel 1, up to 40 bit.
NOTE!
Bits in ADDRx exceeding the address width set in ADDR_W are redundant
and can be set to logic 0.
$''5B:&5&
$''5B:
23
22
21
20
19
18
&5&B/
&5&B(1
17
16
Table 13 Number of bits reserved for RX address + CRC setting.
Bit 23 – 18:
ADDR_W: Number of bits reserved for RX address in ShockBurst™
packages.
NOTE:
Maximum number of address bits is 40 (5 bytes). Values over 40 in
ADDR_W are not valid.
Bit 17:
CRC_L:
Bit: 16:
CRC_EN:
CRC length to be calculated by nRF2401 in ShockBurst™.
Logic 0: 8 bit CRC
Logic 1: 16 bit CRC
Enables on-chip CRC generation (TX) and verification (RX).
Logic 0: On-chip CRC generation/checking disabled
Logic 1: On-chip CRC generation/checking enabled
NOTE:
An 8 bit CRC will increase the number of payload bits possible in each
ShockBurst™ data packet, but will also reduce the system integrity.
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Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
*HQHUDOGHYLFHFRQILJXUDWLRQ
This section of the configuration word handles RF and device related parameters.
Modes:
5;B(1
&0
5)'5B6%
15
14
13
;2B)
12
5)B3:5
11
10
9
8
Table 14 RF operational settings.
Bit 15:
RX2_EN:
Logic 0: One channel receive
Logic 1: Two channels receive
NOTE:
In two channels receive, the nRF2401 receives on two, separate
frequency channels simultaneously. The frequency of receive channel
1 is set in the configuration word B[7-1], receive channel 2 is always 8
channels (8 MHz) above receive channel 1.
Bit 14:
Communication Mode:
Logic 0: nRF2401 operates in direct mode.
Logic 1: nRF2401 operates in ShockBurst™ mode
Bit 13:
RF Data Rate:
Logic 0: 250 kbps
Logic 1: 1 Mbps
NOTE:
Utilizing 250 kbps instead of 1Mbps will improve the receiver
sensitivity by 10 dB. 1Mbps requires 16MHz crystal.
Bit 12-10:
XO_F:
Selects the nRF2401 crystal frequency to be used:
'
0
0
0
0
1
;2)5(48(1&<6(/(&7,21
'
'
&U\VWDO)UHTXHQF\>0+]@
0
0
1
1
0
0
1
0
1
0
4
8
12
16
20
Table 15 Crystal frequency setting.
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
Bit 9-8:
RF_PWR: Sets nRF2401 RF output power in transmit mode:
5)28738732:(5
'
'
3>G%P@
0
0
1
1
0
1
0
1
-20
-10
-5
0
Table 16 RF output power setting.
5)FKDQQHOGLUHFWLRQ
5)B&+
7
6
5
4
3
5;(1
2
1
0
Table 17 Frequency channel + RX / TX setting.
Bit 7 – 1:
RF_CH#: Sets the frequency channel the nRF2401 operates on.
The channel frequency in WUDQVPLW is given by:
&KDQQHO5) = 2400 0+] + 5) _ &+ # ⋅ 1.0 0+]
RF_CH #: between 2400MHz and 2527MHz may be set.
The channel frequency in GDWDFKDQQHO is given by:
&KDQQHO5) = 2400 0+] + 5) _ &+ # ⋅ 1.0 0+] (Receive at PIN#8)
RF_CH #: between 2400MHz and 2524MHz may be set.
NOTE:
The channels above 83 can only be utilized in certain territories (ex: Japan)
The channel frequency in GDWDFKDQQHO is given by:
&KDQQHO5) = 2400 0+] + 5) _ &+ # ⋅ 1.0 0+] +8MHz (Receive at PIN#4)
RF_CH #: between 2408MHz and 2524MHz may be set.
Bit 0:
Set active mode:
Logic 0: transmit mode
Logic 1: receive mode
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
'$7$3$&.$*('(6&5,37,21
PRE-AMBLE
ADDRESS
PAYLOAD
CRC
Figure 11 Data Package Diagram
The data packet for both ShockBurst™ mode and direct mode communication is
divided into 4 sections. These are:
35($0%/(
•
•
•
•
$''5(66
•
•
•
3$</2$'
•
•
•
•
&5&
•
•
The preamble field is required in ShockBurst™ and Direct modes
Preamble is 8 (or 4) bits in length and is dependent of the first data bit in
direct mode.
PREAMBLE
1st ADDR-BIT
01010101
0
10101010
1
Preamble is automatically added to the data packet in ShockBurst™ and
thereby gives extra space for payload.
In ShockBurst™ mode the preamble is stripped from the received output
data, in direct mode the preamble is transparent to the output data.
The address field is required in ShockBurst™ mode.
8 to 40 bits length.
Address automatically removed from received packet in ShockBurst™
mode. In Direct mode MCU must handle address.
The data to be transmitted
In Shock-Burst mode payload size is 256 bits minus the following:
(Address: 8 to 40 bits. + CRC 8 or 16 bits).
In Direct mode the payload size is defined by 1Mbps for 4ms: 4000 bits
minus the following: (Preamble: 8 (or 4) bits. + Address: 8 to 40 bits. +
CRC: 0, 8 or 16 bits).
The CRC is optional in ShockBurst™ mode,
and is not used in Direct mode.
8 or 16 bits length
The CRC is stripped from the received output data.
Table 18 Data package description
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Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
,03257$177,0,1*'$7$
The following timing applies for operation of nRF2401.
Q5)7LPLQJ,QIRUPDWLRQ
Q5)WLPLQJ
0D[
PWR_DWN Î ST_BY mode
PWR_DWNÎ Active mode (RX/TX)
ST_BY Î TX ShockBurst™
ST_BY Î TX Direct Mode
ST_BY Î RX mode
Minimum delay from CS to data.
Minimum delay from CE to data.
Minimum delay from DR1/2 to clk.
Maximum delay from clk to data.
Delay between edges
Setup time
Hold time
Delay to finish internal GFSK data
Minimum input clock high
Set-up of data in Direct Mode
Minimum clock high in Direct Mode
Minimum clock low in Direct Mode
0LQ
3ms
3ms
195µs
202µs
202µs
5µs
5µs
50ns
50ns
50ns
500ns
500ns
1/data rate
500ns
50ns
300ns
230ns
1DPH
Tpd2sby
Tpd2a
Tsby2txSB
Tsby2txDM
Tsby2rx
Tcs2data
Tce2data
Tdr2clk
Tclk2data
Td
Ts
Th
Tfd
Thmin
Tsdm
Thdm
Tldm
Table 19 Switching times for nRF2401
When the nRF2401 is in power down it must always settle in stand-by (Tpd2sby)
before it can enter configuration or one of the active modes.
PWR_UP
CS
CE
CLK1
DATA
Tpd2sby
Figure 12 Timing diagram for power down (or VDD off) to stand by mode
for nRF2401.
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
PWR_UP
CS
CE
CLK1
DATA
Tpd2a
Figure 13 Power down (or VDD off) to active mode
Note that the configuration word will be lost when VDD is turned off and that the
device then must be configured before going to one of the active modes. If the device
is configured one can go directly from power down to the wanted active mode.
1RWH
CE and CS may not be high at the same time. Setting one or the other decides
whether configuration or active mode is entered.
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
&RQILJXUDWLRQPRGHWLPLQJ
When one or more of the bits in the configuration word needs to be changed the
following timing apply.
W
PWR_UP
CS
CE
CLK1
DATA
Td
CS
CE
Thmin
CLK1
MSB
Tcs2data
DATA
Ts
Th
Figure 14 Timing diagram for configuration of nRF2401
If configuration mode is entered from power down, CS can be set high after Tpd2sby
as shown in Figure 12.
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
6KRFN%XUVWŒ0RGHWLPLQJ
6KRFN%XUVWŒ7;
W
PWR_UP
CS
CE
CLK1
DATA
.
ANT1/ANT2
Tsby2txSB
Td
Toa
CS
THmin
CE
CLK1
Tce2data
DATA
Ts
Th
Figure 15 Timing of ShockBurst™ in TX
The package length and the data rate give the delay Toa (time on air), as shown in the
equation.
72$ = 1 / GDWDUDWH ⋅ (# GDWDELWV + 1)
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
6KRFN%XUVWŒ5;
W
PWR_UP
CS
CE
DR1/2
CLK1/2
DATA/DOUT2
.
ANT1/ANT2
Td
Tsby2rx
CE
DR1/2
Thmin
CLK1/2
Tclk2data
Td
Tdr2clk
DATA/
DOUT2
Figure 16 Timing of ShockBurst™ in RX
The CE may be kept high during downloading of data, but the cost is higher current
consumption (18mA) and the benefit is no start-up time (200µs) after the DR1 goes
low.
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
'LUHFW0RGH
'LUHFW0RGH7;
W
PWR_UP
CS
CE
CLK1
DATA
ANT1/ANT2
Td
Tsby2txDM
ToaDM
Tfd
Figure 17 Timing of direct mode TX
In TX direct mode the input data will be sampled by nRF2401 and therefore no clock
is needed. The clock must be stable at low level during transmission due to noise
considerations. The exact delay Tsby2txDM is given by the equation:
7VE\ 2W['0 = 194XV + 1 / );2 ⋅ 14 + 2.25XV
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
'LUHFW0RGH5;
W PWR_UP
CS
CE
CLK1/2
DATA/DOUT2
ANT1/ANT2
Td
Tsby2rx
CE
Thdm
Tldm
CLK1/2
DATA/DOUT2
Tsdm
Figure 18 Timing of direct mode RX
Tsby2rx describes the delay from the positive edge of CE to the start detection of
(demodulated) incoming data.
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Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
3(5,3+(5$/5),1)250$7,21
$QWHQQDRXWSXW
The ANT1 & ANT2 output pins provide a balanced RF output to the antenna. The
pins must have a DC path to VDD, either via a RF choke or via the center point in a
dipole antenna. The load impedance seen between the ANT1/ANT2 outputs should be
in the range 200-700Ω. A de-embedded load impedance i.e. impedance seen at drain
terminals of the output transistors of 400Ω is recommended for maximum output
power (0dBm). Lower load impedance (for instance 50 Ω) can be obtained by fitting a
simple matching network.
2XWSXW3RZHUDGMXVWPHQW
3RZHUVHWWLQJELWVRI
FRQILJXULQJZRUG
5)RXWSXWSRZHU
'&FXUUHQW
FRQVXPSWLRQ
11
0 dBm ±3dB
13.0 mA
10
-5 dBm ±3dB
10.5 mA
01
-10 dBm ±3dB
9.4 mA
00
-20 dBm ±3dB
8.8 mA
Conditions: VDD = 3.0V, VSS = 0V, TA = 27ºC, Load impedance = 400 Ω.
Table 20 RF output power setting for the nRF2401.
&U\VWDO6SHFLILFDWLRQ
Tolerance includes initially accuracy and tolerance over temperature and aging.
)UHTXHQF\
&/
4
8
12
16
20
12pF
12pF
12pF
12pF
12pF
(65
150 Ω
100 Ω
100 Ω
100 Ω
100 Ω
&PD[
7ROHUDQFH
7.0pF
7.0pF
7.0pF
7.0pF
7.0pF
±30ppm
±30ppm
±30ppm
±30ppm
±30ppm
Table 21 Crystal specification of the nRF2401
To achieve a crystal oscillator solution with low power consumption and fast start-up
time, it is recommended to specify the crystal with a low value of crystal load
capacitance. Specifying CL=12pF is OK, but it is possible to use up to 16pF.
Specifying a lower value of crystal parallel equivalent capacitance, Co is also good,
but this can increase the price of the crystal itself. Typically Co=1.5pF at a crystal
specified for Co_max=7.0pF.
Nordic VLSI ASA
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March 2003
PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
3&%OD\RXWDQGGHFRXSOLQJJXLGHOLQHV
A well-designed PCB is necessary to achieve good RF performance. Keep in mind
that a poor layout may lead to loss of performance, or even functionality, if due care is
not taken. A fully qualified RF-layout for the nRF2401 and its surrounding
components, including matching networks, can be downloaded from ZZZQYOVLQR.
A PCB with a minimum of two layers including a ground plane is recommended for
optimum performance. The nRF2401 DC supply voltage should be decoupled as close
as possible to the VDD pins with high performance RF capacitors, see Table 22. It is
preferable to mount a large surface mount capacitor (e.g. 4.7µF tantalum) in parallel
with the smaller value capacitors. The nRF2401 supply voltage should be filtered and
routed separately from the supply voltages of any digital circuitry.
Long power supply lines on the PCB should be avoided. All device grounds, VDD
connections and VDD bypass capacitors must be connected as close as possible to the
nRF2401 IC. For a PCB with a topside RF ground plane, the VSS pins should be
connected directly to the ground plane. For a PCB with a bottom ground plane, the
best technique is to have via holes as close as possible to the VSS pads. One via hole
should be used for each VSS pin.
Full swing digital data or control signals should not be routed close to the crystal or
the power supply lines.
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
$33/,&$7,21(;$03/(
Q5)ZLWKVLQJOHHQGHGPDWFKLQJQHWZRUN
xxx
VDD
C5
1nF
R2
22K
PWR_UP
CE
DR2
CLK2
DOUT2
CS
DR1
CLK1
DATA
CE
DR2
CLK2
DOUT2
CS
DR1
nRF2401
C9
18
17
16
15
14
13
AVSS
AVDD
VSS_PA
ANT2
ANT1
VDD_PA
L1
3.6nH
C3
22pF
xxx
RF I/O
L2
22nH
1.0pF
7
8
9
10
11
12
U1
nRF2401
QFN24/5X5
1.0pF
C8
C4
2.2nF
CLK 1
DA TA
DV DD
AV SS
XC2
XC1
1
2
3
4
5
6
AV DD
PWR_UP
T E ST
AV DD
A VSS
IREF
24
23
22
21
20
19
C6
10nF
X1
C7
33nF
16 MHz
R1
1M
xxx
C1
22pF
C2
22pF
Figure 19 nRF2401 schematic for RF layouts with single end 50Ω antenna
&RPSRQHQW
C1
C2
C3
C4
C5
C6
C7
R1
R2
U1
X1
'HVFULSWLRQ
Capacitor ceramic, 50V, NPO
Capacitor ceramic, 50V, NPO
Capacitor ceramic, 50V, NPO
Capacitor ceramic, 50V, X7R
Capacitor ceramic, 50V, X7R
Capacitor ceramic, 50V, X7R
Capacitor ceramic, 50V, X7R
Resistor
Resistor
Q5) transceiver
Crystal, CL = 12pF,
ESR < 100 ohm
6L]H
9DOXH
7ROHUDQFH
8QLWV
0603
0603
0603
0603
0603
0603
0603
0603
0603
QFN24 / 5x5
LxWxH =
4.0x2.5x0.8
22
22
22
2.2
1.0
10
33
1.0
22
nRF2401
161)
±5%
±5%
±5%
±10%
±10%
±10%
±10%
±1%
±1%
pF
pF
pF
nF
nF
nF
nF
MΩ
KΩ
+/- 30 ppm
MHz
0603
0603
0603
0603
3.6
22
1.0
1.0
± 5%
± 5%
± 0.25 pF
± 0.25 pF
nH
nH
pF
pF
Inductor, wire wound 2)
Inductor, wire wound 2)
Ceramic capacitor, 50V, NP0
Ceramic capacitor, 50V, NP0
L1
L2
C8
C9
Table 22 Recommended components (BOM) in nRF2401 withantenna matching
network
Q5) can operate at several crystal frequencies, please refer to page 31.
Wire wound inductors are recommended, other can be used if their self-resonant frequency (SFR) is
> 2.7 GHz
1)
2)
Nordic VLSI ASA
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PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
3&%OD\RXWH[DPSOH
Figure 20 shows a PCB layout example for the application schematic in Figure 19.
A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane
on the bottom layer. Additionally, there are ground areas on the component side of the
board to ensure sufficient grounding of critical components. A large number of via
holes connect the top layer ground areas to the bottom layer ground plane.
No components in bottom layer
Top silk screen
Top view
Bottom view
Figure 20 nRF2401 RF layout with single ended connection to 50Ω antenna and 0603
size passive components
Nordic VLSI ASA
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March 2003
PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
'(),1,7,216
'DWDVKHHWVWDWXV
Objective product specification
Preliminary product
specification
Product specification
This datasheet contains target specifications for product development.
This datasheet contains preliminary data; supplementary data may be
published from Nordic VLSI ASA later.
This datasheet contains final product specifications. Nordic VLSI ASA
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
/LPLWLQJYDOXHV
Stress above one or more of the limiting values may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or at any other conditions above those given in the
Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may
affect device reliability.
$SSOLFDWLRQLQIRUPDWLRQ
Where application information is given, it is advisory and does not form part of the specification.
Table 23. Definitions
Nordic VLSI ASA reserves the right to make changes without further notice to the
product to improve reliability, function or design. Nordic VLSI does not assume any
liability arising out of the application or use of any product or circuits described
herein.
/,)(6833257$33/,&$7,216
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Nordic VLSI ASA customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Nordic VLSI ASA
for any damages resulting from such improper use or sale.
Preliminary Product Specification: Revision Date: 27.03.2003.
Datasheet order code: 270303-nRF2401.
All rights reserved ®. Reproduction in whole or in part is prohibited without the prior
written permission of the copyright holder.
Nordic VLSI ASA
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March 2003
PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
<285127(6
Nordic VLSI ASA
Revision: 1.0
-
Vestre Rosten 81, N-7075 Tiller, Norway
Page 36 of 37
-
Phone +4772898900
-
Fax +4772898989
March 2003
PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
1RUGLF9/6,$6$±:RUOG:LGH'LVWULEXWRUV
)RU<RXUQHDUHVWGHDOHUSOHDVHVHHKWWSZZZQYOVLQR
0DLQ2IILFH
Vestre Rosten 81, N-7075 Tiller, Norway
Phone: +47 72 89 89 00, Fax: +47 72 89 89 89
9LVLWWKH1RUGLF9/6,$6$ZHEVLWHDWKWWSZZZQYOVLQR
Nordic VLSI ASA
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-
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Page 37 of 37
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March 2003