ETC NRF2402

PRODUCT SPECIFICATION
nRF2402
nRF2402G
Single chip 2.4 GHz Transmitter
FEATURES
APPLICATIONS
•
•
True single chip GFSK transmitter in a
small 16-pin package (QFN16 4x4)
• Adjustable output power up to 0dBm
• Data rate 0 to 1Mbps
• Low Bill of Material
• Multi Channel operation
• 128 channels
• Support frequency hopping
• Channel switching time <200µs.
• Power supply range: 1.9 to 3.6 V
• CRC computation
• ShockBurst™ mode for ultra-low power
operation
• Low supply current, typical 10mA peak
@ -5dBm output power
• 100% RF tested
• World wide use
Wireless mouse, keyboard, joystick
Keyless entry
Wireless data communication
Alarm and security systems
Home Automation
Remote control
Surveillance
Automotive
Telemetry
Intelligent sports equipment
Industrial sensors
Toys
•
•
•
•
•
•
•
•
•
•
•
GENERAL DESCRIPTION
nRF2402/nRF2402G is a single-chip radio transmitter for the world wide 2.4 - 2.5 GHz ISM
band. The transmitter consists of a fully integrated frequency synthesizer, a power amplifier,
a crystal oscillator and a modulator. Output power and frequency channel is easily
programmable by use of the 3-wire interface. Current consumption is very low, only 10 mA
at an output power of -5dBm. Built-in ShockBurst™ and Power Down modes makes power
saving easily realizable.
QUICK REFERENCE DATA
Parameter
Value
Unit
Minimum supply voltage
Maximum output power
Maximum GFSK data rate
Supply current GFSK transmitter @ -5dBm output power
Supply current in Power Down mode
1.9
0
1000
10
200
V
dBm
kbps
mA
nΑ
Table 1 nRF2402/nRF2402G quick reference data
Type Number
Description
Version
NRF2402
NRF2402G
16 pin QFN 4x4, punch/saw
16 pin QFN 4x4, punch, green
A
A
Table 2 nRF2402/nRF2402G ordering information
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
BLOCK DIAGRAM
VSS (15)
VSS (5)
VDD (13)
VDD (8)
XC1 (7)
ShockBurstTM
CE (1)
FIFO
In
PWR_UP (16)
Frequency
Synthesiser
XC2 (6)
CRC
Code
ANT1 (10)
PA
ANT2 (11)
GFSK
Filter
DIN (4)
3-wire
Interface
CLK (3)
VSS_PA (9)
3-wire
Programming
Interface
VDD_PA (12)
IREF (14)
CS (2)
22kΩ
Figure 1 nRF2402/nRF2402G with external components.
PIN FUNCTIONS
Pin
Name
Pin function
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CE
CS
CLK
DIN
VSS
XC2
XC1
VDD
VSS_PA
ANT1
ANT2
VDD_PA
VDD
IREF
VSS
PWR_UP
Input
Input
Input
Input
Power
Output
Input
Power
Power
Power/RF
Power/RF
Power Output
Power
Input
Power
Input
Chip Enable Activates TX mode
Chip Select Activates Configuration Mode
Clock Input TX Data and 3-wire Interface
TX Data Input / Configuration Data Input
Ground (0V)
Crystal pin 2
Crystal pin 1
Power Supply (1.9-3.6V)
Ground (0V)
Antenna output 1
Antenna output 2
Power Supply (+1.8V) output to internal Power Amplifier
Power Supply (1.9-3.6V)
Reference current
Ground (0V)
Power Up
Table 3 nRF2402/nRF2402G pin functions
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
PIN ASSIGNMENT
PWR_UP
16
CE
1
CS
2
VSS
IREF
VDD
15
14
13
nRF2402/
nRF2402G
QFN16 4x4
12
VDD_PA
11
ANT2
ANT1
CLK
3
10
DIN
4
9
5
VSS
6
7
8
XC2
XC1
VDD
VSS_PA
Figure 2. nRF2402/nRF2402G pin assignment (top view).
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
ELECTRICAL SPECIFICATIONS
Conditions: VDD = +3V, VSS = 0V, TA = - 40ºC to + 85ºC
Symbol Parameter (condition)
VDD
TEMP
Notes
Min.
Typ.
Max.
Units
1.9
-40
3.0
+27
3.6
+85
V
ºC
0.7·VDD
Vss
VDD
0.3·VDD
V
V
VDD- 0.3
Vss
VDD
0.3
V
V
1)
2)
2400
4
2527
20
3)
>0
250
MHz
MHz
kHz
kbps
kbps
MHz
Operating conditions
Supply voltage
Operating Temperature
VIH
VIL
Digital input pin
HIGH level input voltage
LOW level input voltage
VOH
VOL
HIGH level output voltage (IOH=-0.5mA)
LOW level output voltage (IOL=0.5mA)
Digital output pin
fOP
fXTAL
∆f
RGFSK
RGFSK
FCHANNEL
P RF
P RFC
P RFCR
P BW
P RF2
P RF3
IVDD
IVDD
IVDD
IVDD
IVDD
General RF conditions
Operating frequency
Crystal frequency
Frequency deviation
GFSK data rate ShockBurst™
GFSK data rate Direct Mode
Channel spacing
±156
1000
1000
1
Transmitter operation
Maximum Output Power
RF Power Control Range
RF Power Range Control Resolution
20dB Bandwidth for Modulated Carrier
2nd Adjacent Channel Transmit Power 2MHz
3rd Adjacent Channel Transmit Power 3MHz
Supply current @ 0dBm output power
Supply current @ -5dBm output power
Supply current @ -10dBm output power
Supply current @ -20dBm output power
Average Supply current @ -5dBm output
power, ShockBurst™
Supply current in stand-by mode
Supply current in power down
4)
16
0
20
+4
±3
1000
-20
-40
5)
5)
5)
5)
6)
11.5
10.0
8.5
7.0
500
dBm
dB
dB
kHz
dBc
dBc
mA
mA
mA
mA
µA
IVDD
12
µA
IVDD
200
nA
NOTES:
1) Usable band is determined by local regulations
2) The crystal frequency may be chosen from 5 different values (4, 8, 12, 16, and 20MHz) which are specified in the
configuration word, see Table 8. 16MHz is required for 1Mbps operation.
3) Data rate must be either 250kbps or 1000kbps.
4) Antenna load impedance = 100Ω+j175Ω
5) Antenna load impedance = 100Ω+j175Ω. Effective data rate 250kbps or 1Mbps.
6) Antenna load impedance = 100Ω+j175Ω. Effective data rate 10kbps.
Table 4 nRF2402/nRF2402G electrical specifications
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
PACKAGE OUTLINE, PUNCH TYPE
nRF2402G uses the GREEN QFN16 4x4 package, with matt tin plating.
Package Type
Green QFN16
(4x4 mm)
Min
typ.
Max
A
0.8
0.9
A1
0.0
0.02
0.05
A2
0.65
0.69
b
0.25
0.3
0.35
D/E
D1/E1
e
4 BSC
3.75
BSC
0.65 BSC
J
2.02
2.12
2.22
K
2.02
2.12
2.22
L
0.45
0.55
0.65
Figure 3 nRF2402G Punch package outline.
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R
0.51
0.61
0.71
PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
PACKAGE OUTLINE, SAW TYPE
nRF2402, uses the QFN16 4x4 package, only available with SnPb plating. Dimensions are in mm.
Package Type
QFN16
(4x4 mm)
Min
typ.
Max
A
0.8
A1
0.0
A2
0.75
1
0.05
1
b
0.23
0.3
0.38
D
E
e
4 BSC
4 BSC
0.65 BSC
J
0.75
K
0.7
2.25
2.25
L
0.45
0.55
0.75
Figure 4 nRF2402 Saw package outline, dimensions in mm.
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P
45°
REF
PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
ABSOLUTE MAXIMUM RATINGS
Supply voltages
VDD ............................ - 0.3V to + 3.6V
VSS ...................................................0V
Input voltage
VI ....................... - 0.3V to VDD + 0.3V
Output voltage
VO ...................... - 0.3V to VDD + 0.3V
Total Power Dissipation
PD (TA =85°C) ..............................35mW
Temperatures
Operating Temperature…. - 40°C to + 85°C
Storage Temperature…... - 40°C to + 125°C
Note: Stress exceeding one or more of the limiting values may cause permanent damage to
the device.
ATTENTION!
Electrostatic Sensitive Device
Observe Precaution for handling.
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
GLOSSARY OF TERMS
Term
CLK
CRC
CS
CE
GFSK
ISM
MCU
OD
PWR_DWN
PWR_UP
RX
ST_BY
TX
Description
Clock
Cyclic Redundancy Check
Chip Select
Chip Enable
Gaussian Frequency Shift Keying
Industrial- Scientific -Medical
Micro Controller Unit
Overdrive
Power Down
Power Up
Receive
Standby
Transmit
Table 5 Glossary
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
MODES OF OPERATION
Overview of Operational Modes
The nRF2402/nRF2402G can be set in the following main modes depending on three control
pins:
Mode
Active
Configuration
Stand By
Power Down
PWR_UP
1
1
1
0
CE
1
0
0
X
CS
0
1
0
X
Table 6 Overview of Operational Modes of nRF2402/nRF2402G.
Active Modes
The nRF2402/nRF2402G has two transmit modes:
•
•
ShockBurst™
Direct Mode
The device functionality in these modes is determined by the content of a configuration word.
This configuration word is presented in the configuration section.
ShockBurst™
The ShockBurst™ technology uses on-chip FIFO to clock in data at a low data rate and
transmit at a very high rate thus enabling extreme reduction in power consumption.
When operating the nRF2402/nRF2402G (in co-operation with nRF2401/nRF24E1) in
ShockBurst™, you gain access to the high data rates (1 Mbps) offered by the 2.4 GHz band
without the need of a costly, high-speed micro controller (MCU) for data processing.
By putting all high speed signal processing related to RF protocol on-chip, the
nRF2402/nRF2402G offers the following benefits:
•
•
•
Highly reduced current consumption
Lower system cost (facilitates use of less expensive micro controller)
Greatly reduced risk of ‘on-air’ collisions due to short transmission time
The nRF2402/nRF2402G can be programmed using a simple 3-wire interface where the data
rate is decided by the speed of the micro controller.
By allowing the digital part of the application to run at low speed while maximizing the data
rate on the RF link, the nRF ShockBurst™ mode reduces the average current consumption in
applications considerably.
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
ShockBurst™ principle
When the nRF2402/nRF2402G is configured in ShockBurst™, TX operation is conducted in
the following way (10 kbps for this example only).
nRF2402/
nRF2402G
Continuous 10kbps
8-bit
MCU
FIFO
ShockBurstTM
1Mbps
Fig
ure 5 Clocking in data with MCU and sending with ShockBurst technology
Without ShockBurstTM, running at speed dictated by 10kbps MCU
10mA
periode
10mA periode
0
20
40
60
10kbps MCU with ShockBurstTM
80
100
120
140
160
180
200
220
240
Time mS
Figure 6 Current consumption with and without ShockBurst technology
nRF2402/nRF2402G ShockBurst™ Transmit:
MCU interface pins: CE, CLK, DIN
1. When the application MCU has data to send, set CE high. This activates RF2402
on-board data processing.
2. The address of the receiving node (RX address) and payload data is clocked into
the nRF2402/nRF2402G. The application protocol or MCU sets the speed (ex:
10kbps).
3. MCU sets CE low, this activates a nRF2402/nRF2402G ShockBurst™
transmission.
4. nRF2402/nRF2402G ShockBurst™:
• RF front end is powered up
• RF package is completed (preamble added, CRC calculated)
• Data is transmitted at high speed (250 kbps or 1 Mbps configured by user).
• nRF2402/nRF2402G returns to stand-by when finished
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
NO
nRF2402 in
ShockBurstTM
TX (CE=hi)?
YES
Data content of registers:
uController
Loading ADDR
and PAYLOAD
data
ADDR
PAYLOAD
Maximum 256 bits
nRF2402
Calculating CRC
ADDR
PAYLOAD
CRC
NO
CE=Low?
YES
nRF2402
Adding Preamble
nRF2402
Sending
ShockBurstTM
Package
(250 or 1000kbps)
YES
Preamble
ADDR
PAYLOAD
CRC
Input FIFO not Empty
NO
Sending
completed?
Figure 7 Flow Chart ShockBurst™ Transmit of nRF2402/nRF2402G with CRC and
preamble.
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
Direct Mode
In direct mode the nRF2402/nRF2402G works like a traditional RF device. The data rate
must be 1Mbps ±200ppm, or 250kbps ±200ppm at low data rate setting, for the receiver
(nRF2402/nRF24E1) to detect the signals.
MCU interface pins: CE, DIN
1. When application MCU has data to send, set CE high
2. The nRF2402/nRF2402G RF front end is now immediately activated, and after
200 µs settling time, signal on the DIN pin will modulate the carrier directly.
3. All RF protocol parts must hence be implemented in MCU firmware (preamble,
address and CRC).
Configuration Mode
In configuration mode a configuration word of up to 20 bits is downloaded to
nRF2402/nRF2402G. This is done through a simple 3-wire interface (CS, CLK and DIN).
For more information on configuration please refer to the nRF2402/nRF2402G device
configuration chapter, page13.
Power Down Mode
Power down mode is used to achieve very low current consumption. Effectively the chip is
disabled with minimal leakage current consumption, typically less than 200nA. Operating in
this mode when not transmitting data significantly increases battery lifetime.
Stand-By Mode
Stand by mode is used to achieve low current consumption. In this mode only a part of the
crystal oscillator is running (12µA) to guarantee a short start-up time. Operating in this mode
when not transmitting data increases battery lifetime while keeping start up delays short.
Pin configuration for the different modes of nRF2402/nRF2402G
nRF2402/nRF2402G
MODES
Pin Name
Power down
Stand by
Configuration
TX ShockBurst™
TX Direct
INPUT PINS
PWR_UP
CE
CS
CLK
DIN
0
1
1
1
1
0
0
0
1
1
X
0
1
0
0
X
X
CLK
CLK
Set to 0∗
X
X
CONFIG DATA
TX DATA
TX DATA
Table 7 Pin configuration of nRF2402/nRF2402G.
∗
CLK not used in direct mode.
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
DEVICE CONFIGURATION
All configuration of the nRF2402/nRF2402G is done via a 3-wire interface to a single
configuration register. The configuration word can be up to 20 bits long for ShockBurst™ use
and up to 14 bits long for direct mode.
Configuration for ShockBurst™ operation
The configuration word in ShockBurst™ enables the nRF2402/nRF2402G to handle the RF
protocol (in co-operation with nRF2401/nRF24E1). Once the protocol is completed and
loaded into nRF2402/nRF2402G only seven bits, also used in direct mode, needs to be
updated during operation.
The configuration bits dedicated to ShockBurst™ is as follows:
• Preamble: Generation of 8 bit preamble in transmitted data.
• CRC: Enables nRF2402/nRF2402G on-chip CRC generation.
NOTE:
The MCU must generate an address and a payload section that fits the configuration of the
nRF2401/nRF24E1 that is to receive the data.
When using the nRF2402/nRF2402G on-chip CRC feature ensure that CRC is enabled and
uses the same length for both the nRF2402/nRF2402G and the receiving nRF2401/nRF24E1
devices.
PRE-AMBLE
ADDRESS
PAYLOAD
CRC
Figure 8 Data packet set-up
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
Configuration for Direct Mode operation
For direct mode operation only the 14 first bits (bit[13:0]) of the configuring word is relevant.
Configuration Word overview
General device
configuration
Bit
Number
position of bits
19
18
17
16
15
14
13
12
11:9
8:7
6:0
6
1
1
1
1
1
1
1
3
2
7
Name
PLL Control
PREAMBLE
PREAMBLE
CRC
CRC
CM
RFDR_SB
XO_F
RF_PWR
RF_CH#
Function
Close the PLL for test.
UNUSED
Enable on-chip PREAMBLE generation
UNUSED, must be 1
8 or 16 bit CRC
Enable on-chip CRC generation
Communication mode (Direct or ShockBurst™)
RF data rate (1Mbps requires 16MHz crystal)
Crystal frequency
RF output power
Frequency channel (0 to 127)
Table 8 Table of configuration words.
The configuration word is shifted in MSB first on positive CLK edges. New configuration is
enabled on the negative edge of CS.
NOTE!
On the negative edge of CS, the nRF2402/nRF2402G updates the number of bits actually
shifted in during the last configuration.
Ex:
If the nRF2402/nRF2402G is to be configured for Preamble and CRC in ShockBurst™, a
total of 17 bits must be shifted in during the first configuration after VDD is applied.
Once the wanted "protocol" and modus are set there is no need to update this part of the
configuration during operation. If RF channel is to be changed, only the RF_CH# bits need to
be updated.
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
Configuration Word Detailed Description
The following describes the function of the 32 bits (bit 31 = MSB) that is used to configure
the nRF2402/nRF2402G.
General Device Configuration: bit[13:0]
ShockBurst™ Configuration: bit[17:14]
Test Configuration: bit[19:18]
TEST
D19
PLL
0
D13
Burst
0
D18
0
D12
OD
0
D17
PRE_EN
1
D16
ShockBurst
D15
D14
CRC
1
0
D11
D10
D9
XO Frequency
1
1
1
0
RF-Programming
D8
D7
D6
RF Power
1
0
0
Default
LSB
D5
0
D4
D3
D2
Channel selection
0
0
0
D1
D0
1
0
Default
The MSB bit should be loaded first into the configuration register.
Default configuration word: h30F02.
Test configuration
Bit 19:
PLL:
For test purposes the PLL may be closed to send a constant carrier
Logic 0: Open loop (normal operation)
Logic 1: Closed loop (test only)
Bit: 18:
Not used, must be set to logic 1
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
ShockBurst™ configuration
The section bit[17:14] contains the segments of the configuration register dedicated to
ShockBurst™ operation. After VDD is turned on ShockBurst™ configuration must be done
once, but remains set whilst VDD is present. During operation only the 7 bits for frequency
channel normally need to be changed.
PREAMBLE
17
16
CRC
15
14
Table 9 Preamble and CRC settings.
Bit 17:
PRE_EN:
Preamble to be generated by nRF2402/nRF2402G in ShockBurst™.
Logic 0: No generation of Preamble
Logic 1: Preamble generation enabled (default)
Bit: 16:
Not used, must be set to logic 1
Bit 15:
CRC_L:
CRC length to be calculated by nRF2402/nRF2402G in ShockBurst™.
Logic 0: 8 bit CRC (default)
Logic 1: 16 bit CRC
Bit: 14:
CRC_EN:
Enables on-chip CRC generation (TX)
Logic 0: On-chip CRC generation disabled (default)
Logic 1: On-chip CRC generation enabled
NOTE:
An 8 bit CRC (compared to 16 bit) will increase the number of payload bits
possible in each ShockBurst™ data packet, but will also reduce the
communication integrity.
General device configuration:
This section of the configuration word handles RF and device related parameters.
Burst
OD
13
12
XO_F
11
10
RF_PWR
9
8
7
Table 10 RF operational settings.
Bit 13:
Burst:
Nordic Semiconductor ASA
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Logic 0: nRF2402/nRF2402G operates in direct mode (default)
Logic 1: nRF2402/nRF2402G operates in ShockBurst™ mode
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PRODUCT SPECIFICATION
nRF2402/nRF2402G Single Chip 2.4 GHz Radio Transmitter
Bit 12:
OD:
Logic 0: 250 kbps data rate
Logic 1: 1 Mbps data rate
NOTE:
1Mbps requires 16MHz crystal.
Bit 11-9:
XO_F:
Selects the nRF2402/nRF2402G crystal frequency to be used:
D11
0
0
0
0
1
XO FREQUENCY SELECTION
D10
D9
Crystal Frequency [MHz]
0
0
1
1
0
0
1
0
1
0
4
8
12
16
20
Table 11 Crystal frequency setting.
Bit 8-7:
RF_PWR:
Sets nRF2402/nRF2402G RF output power:
RF OUTPUT POWER
D8
D7
P [dBm]
0
0
1
1
0
1
0
1
-20
-10
-5
0
Table 12 RF output power setting.
Conditions: Load impedance = 100+j175 Ω.
RF channel
RF_CH#
6
5
4
3
2
1
0
Table 13 Frequency channel setting.
Bit 6 – 0:
RF_CH#:
Sets the frequency channel the nRF2402/nRF2402G transmits in.
The channel frequency is given by:
Channel RF = 2400 MHz + RF _ CH # ⋅ 1.0 MHz
RF_CH #: Frequencies between 2400MHz and 2527MHz may be set.
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DATA PACKAGE DESCRIPTION
PRE-AMBLE
ADDRESS
PAYLOAD
CRC
Figure 9 Data Package Diagram
The data packet for both ShockBurst™ mode and direct mode communication is divided into
4 sections. These are:
•
•
1. PREAMBLE
•
2
ADDRESS
•
•
•
3
PAYLOAD
•
•
•
4
•
CRC
•
The preamble field is a requirement for ShockBurst™ and Direct modes
Preamble is 8 bits in length and is dependent on the 1st data bit.
PREAMBLE
1st Data Bit (Address)
01010101
0
10101010
1
Preamble is automatically added to the data packet and thereby gives
extra space for payload in ShockBurst™. Preamble must be added by
MCU in Direct mode
The address field is required in ShockBurst™ mode.1
8 to 40 bits length.
Address automatically removed from received packet in ShockBurst™
mode. In Direct mode MCU must handle address.
The data to be transmitted
In ShockBurst™ mode payload size is 256 bits minus the following:
(Address: 8 to 40 bits. + CRC 8 or 16 bits).
In Direct mode the maximum payload size is defined by 1Mbps for 4ms:
4000 bits minus the following: (Preamble: 8 bits. + Address: 0 to 40 bits.
+ CRC: 0, 8 or 16 bits).
On chip CRC calculation is an option in ShockBurst™ mode,
and is not used in Direct mode.
8 or 16 bits length
Table 14 Data package
1
Suggestions for the use of addresses in ShockBurst™: In general more bits in the address gives less
false detection, which in the end may give lower data packet loss.
• The address made by (5, 4, 3, or 2) equal bytes are not recommended because it in general will make the
packet-error-rate increase.
• Addresses where the level shift only one time (i.e. 000FFFFFFF) could often be detected in noise that may
give a false detection, which again may give raised packet-error-rate.
Direct mode will be dependent on the software used in the MCU, but it is recommended to have the
same restrictions on addresses for this mode.
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IMPORTANT TIMING DATA
The following timing applies for operation of nRF2402/nRF2402G.
nRF2402/nRF2402G Timing Data
nRF2402/nRF2402G timing
Min.
PWR_DWN è Configuration mode
PWR_DWNè Active mode (TX)
ST_BY è TX ShockBurst™
ST_BY è TX Direct Mode
Minimum delay from CS to data.
Minimum delay from CE to data.
Delay between edges
Setup time
Hold time
Delay to finish internal GFSK data
Minimum input clock high
Time on air, TX Direct mode
Max.
3ms
3ms
195µs
202µs
5µs
5µs
50ns
500ns
500ns
1/data rate
500ns
4ms
Name
Tpd2cfgm
Tpd2a
Tsby2txSB
Tsby2txDM
Tcs2data
Tce2data
Td
Ts
Th
Tfd
Thmin
ToaDM
Table 15 Switching times for nRF2402/nRF2402G
When the nRF2402/nRF2402G is powered up it must always settle in stand by for 3ms before
it can enter configuration or active mode.
PWR_UP
CS
CE
CLK
DIN
Tpd2cfgm
Figure 10 Timing diagram for power down (or VDD off) to configuration mode
for nRF2402/nRF2402G.
PWR_UP
CS
CE
CLK
DIN
Tpd2a
Figure 11 Power down (or VDD off) to active mode
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Note that the configuration word will be lost when VDD is turned off and that the device then
must be configured before going to active mode. If the device is configured one can go
directly from power down to active mode.
Note:
CE and CS may not be high at the same time. Setting one or the other decides whether
configuration or active mode is entered.
Configuration Mode
In configuration mode the transmitters output power, transmit frequency, data rate, CRC, and
preamble is set. The configuring data will be loaded during the Chip Select period (CS="1").
A random number of bits between 1 and 20 may be shifted in to the register to configure the
transmitter, but normally you would at least shift in the seven channel frequency bits. The
new configuration is activated on the negative edge of CS.
When one or more of the bits in the configuration word needs to be changed the following
timing apply.
Configuration Mode Timing
t=0
PWR_UP
CS
CE
CLK
DIN
Td
CS
CE
Thmin
CLK
MSB
Tcs2data
DIN
Ts
Th
Figure 12 Timing Diagram of Configuration Mode
If configuration mode is entered from power down, CS can be set high after Tpd2sby as
shown in Figure 10.
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ShockBurst™ Mode Timing
t=0
PWR_UP
CS
CE
CLK
DIN
.
ANT1/ANT2
Tsby2txSB
Td
Toa
CS
THmin
CE
CLK
Tce2data
DIN
Ts
Th
Figure 13 Timing of ShockBurst™ in nRF2402/nRF2402G.
The package length and the data rate give the delay Toa (time on air), as shown in the
equation.
TOA = 1 / datarate ⋅ (# databits + 1)
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Direct Mode Timing
t=0
PWR_UP
CS
CE
CLK
DIN
ANT1/ANT2
Td
Tsby2txDM
ToaDM
Tfd
Figure 14 Timing Diagram of Direct Mode
In direct mode the input data will be sampled by nRF2402/nRF2402G and therefore no clock
is needed. The clock must be stable at low level during transmission due to noise
considerations. The exact delay Tsby2txDM is given by the equation:
Tsby 2txDM = 194us + 1 / F XO ⋅ 20 + 2.25us
The maximum length of a package (ToaDM) over all voltages and temperatures is 4ms. This
is limited by frequency drift in the transmitter and is independent of data rate and frequency
channel.
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PERIPHERAL RF INFORMATION
Antenna output
The ANT1 and ANT2 output pins provide a balanced RF output to the antenna. The pins
must have a DC path to VDD_PA, either via a RF choke or via the center point in a balanced
antenna. Differential load impedance between the ANT1 and ANT2 pins, 100Ω+j175Ω, is
recomme nded for maximum output power. Antennas with lower load impedance (for
example 50Ω) can be matched to nRF2402/nRF2402G by using a simple matching network.
Antenna matching networks
The recommended 50Ω matching network is shown in Figure 15. This is a low pass network
improving higher harmonic suppression.
2.2nF
4.7pF
1.0pF
VDD_PA
nRF2402
10nH
ANT2
3.3nH
ANT1
RF output
5.6nH
1.0pF
4.7pF
Figure 15 Low pass antenna matching network
A somewhat simpler matching network is shown in Figure 16.
2.2nF
4.7pF
22nH
1.0pF
VDD_PA
nRF2402
RF output
ANT2
3.6nH
ANT1
1.0pF
Cout
1.5pF
Figure 16 High pass antenna matching network
This network utilizes one component less and uses few inductors, but performance of this
network requires very careful PCB ground plane layout. The value of capacitor Cout is
dependent on PCB ground plane layout and parasitics in the layout, and must hence be
matched to a given application layout. The value of Cout will typically be in the range 1.0pF –
1.8pF. Cout must be tuned while checking that the harmonics output is below frequency
regulatory limits.
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Output Power adjustment
Power setting bits of
configuring word
11
10
01
00
RF output power
DC current
consumption
0 dBm ±3dB
-5 dBm ±3dB
-10 dBm ±3dB
-20 dBm ±3dB
Conditions: Load impedance = 100+j175 Ω.
11.5 mA
10.0 mA
8.5 mA
7.0 mA
Table 16 RF output power setting for the nRF2402/nRF2402G.
Crystal Specification
Tolerance includes initially accuracy and tolerance over temperature and aging.
Frequency
CL
ESR
C0max
Tolerance
4MHz
8MHz
12MHz
16MHz
20MHz
8pF – 16pF
8pF – 16pF
8pF – 16pF
8pF – 16pF
8pF – 16pF
150Ω
100Ω
100Ω
100Ω
100Ω
7.0pF
7.0pF
7.0pF
7.0pF
7.0pF
±30ppm
±30ppm
±30ppm
±30ppm
±30ppm
Table 17 Crystal specification of the nRF2402/nRF2402G
To achieve a crystal oscillator solution with low power consumption and fast start-up time, it
is recommended to specify the crystal with a low value of crystal load capacitance.
Specifying a lower value of crystal parallel equivalent capacitance, Co=1.5pF is also good,
but this can increase the price of the crystal itself. Typically Co=1.5pF at a crystal specified
for Co_max=7.0pF.
The crystal load capacitance, CL, is given by:
CL =
C1 '⋅C 2 '
,
C1 '+C 2 '
where C1 ' = C1 + C PCB1 + C I 1 and C 2 ' = C 2 + C PCB 2 + C I 2
C1 and C2 are 0603 SMD capacitors as shown in the application schematics. CPCB1 and CPCB2
are the layout parasitic on the circuit board. CI1 and CI2 are the capacitance seen into the XC1
and XC2 pin respectively; the value is typical 1pF.
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Sharing crystal with micro controller.
When using a micro controller to drive the crystal reference input XC1 of the
nRF2402/nRF2402G transmitter some rules must be followed.
Crystal parameters:
When the micro controller drives the nRF2402/nRF2402G XC1 input, all crystal load
parameters (C L, C 0, ESR) are set by the micro controller specification. The frequency
accuracy (±30 ppm) is still set by the nRF2402/nRF2402G specification. The
nRF2402/nRF2402G will load the crystal circuitry of the micro controller by XC1 input
capacitance (0.5pF) plus PBC routing paracitics.
External reference input amplitude & Current consumption
The reference input should never have signal levels exceeding rail voltages. Exceeding rail
voltage will excite the ESD structure and the radio performance is degraded below
specification. Applying reference sources without DC bias will bring the reference signal
under GND level, and this is not acceptable.
XO_OUT
Buffer:
Sine to
full swing
Amplitude
controlled
current source
Current starved
inverter:
XOSC core
Vdd
Vdd
Vss
Vss
ESD
ESD
XC1
Figure 17
XC2
Principle of crystal oscillator
It is hence recommended to use a DC-block before the XC1 pin so that the internal ESD
structures will self bias the XC1 voltage.
The nRF2402/nRF2402G crystal oscillator is amplitude regulated. To achieve low current
consumption and also good signal-to-noise ratio, it is recommended to use an input signal
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larger than 0.4 V-peak. The needed input swing is independent of the crystal frequency.
When using external crystal refernce, XC2 is not used and can be left as an open pin.
Frequency Reference MCU
In direct mode there is a requirement on the accuracy of the data rate. For the receiver to
detect the incoming data and recover the clock, the data rate must be within ±200ppm, given
that the data is "random", i.e. there is a statistical calculation on how often a preamble like
sequence is present in the data. The clock is synchronized for any preamble detection, be it a
dedicated preamble or part of the data stream.
PCB layout and de-coupling guidelines
A well-designed PCB is necessary to achieve good RF performance. Keep in mind that a poor
layout may lead to loss of performance, or even functionality, if due care is not taken. A fully
qualified RF-layout for the nRF2402/nRF2402G and its surrounding components, including
matching networks, can be downloaded from www.nordicsemi.no.
A PCB with a minimum of two layers including a ground plane is recommended for optimum
performance. The nRF2402/nRF2402G DC supply voltage should be de-coupled as close as
possible to the VDD pins with high performance RF capacitors, see Table 18. It is preferable
to mount a large surface mount capacitor (e.g. 4.7µF tantalum) in parallel with the smaller
value capacitors. The nRF2402/nRF2402G supply voltage should be filtered and routed
separately from the supply voltages of any digital circuitry.
Long power supply lines on the PCB should be avoided. All device grounds, VDD
connections and VDD bypass capacitors must be connected as close as possible to the
nRF2402/nRF2402G IC. The VSS pins should be connected directly to the ground plane.
One via hole should be used for each VSS pin.
Full swing digital data or control signals should not be routed close to the crystal or the
power supply lines.
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APPLICATION EXAMPLE
nRF2402/nRF2402G with single ended matching network
VDD
VDD
C5
1nF
C6
10nF
16
15
14
13
R2
22k
CE
CS
CLK
DIN
C8
1.0pF
C3
4.7pF
nRF2402
L2
VDD_PA
ANT2
ANT1
VSS_PA
10nH
12
11
10
9
L1
3.3nH
C9
L3
VSS
XC2
XC1
VDD
1
2
3
4
PWR_UP
VSS
IREF
VDD
PWR_UP
CE
CS
CLK
DIN
C4
2.2nF
U1
NRF2402
5.6nH
RF output
4.7pF
5
6
7
8
C7
1.0pF
VDD
X1
16MHz
R1
1M
C1
22pF
C2
22pF
Figure 18 nRF2402/nRF2402G schematic for RF layouts with single ended 50Ω antenna
Component
Size
Value
Tolerance
Units
C1
C2
C3
C4
C5
C6
R1
R2
U1
Capacitor ceramic, 50V, NPO
Capacitor ceramic, 50V, NPO
Capacitor ceramic, 50V, NPO
Capacitor ceramic, 50V, X7R
Capacitor ceramic, 50V, X7R
Capacitor ceramic, 50V, X7R
Resistor
Resistor
nRF2402/nRF2402G transmitter
0603
0603
0603
0603
0603
0603
0603
0603
QFN16 / 4x4
±5%
±5%
±5%
±10%
±10%
±10%
±10%
±1%
pF
pF
pF
nF
nF
nF
MΩ
kΩ
X1
Crystal, CL = 12pF,
ESR < 100 ohm
Inductor 2)
Inductor 2)
Inductor 2)
Ceramic capacitor, 50V, NP0
Ceramic capacitor, 50V, NP0
Ceramic capacitor, 50V, NP0
LxWxH =
4.0x2.5x0.8
0603
0603
0603
0603
0603
0603
22
22
4.7
2.2
1.0
10
1.0
22
nRF2402/
nRF2402G
16 1)
+/- 30 ppm
MHz
3.3
10
5.6
1.0
1.0
4.7
± 5%
± 5%
± 5%
± 0.1 pF
± 0.1 pF
± 0.25 pF
nH
nH
nH
pF
pF
pF
L1
L2
L3
C7
C8
C9
Description
Table 18 Recommended components (BOM) in nRF2402/nRF2402G with antenna matching network
1)
2)
nRF2402/nRF2402G can operate at several crystal frequencies, ref. the Crystal Spec. chapter.
Self-resonant frequency (SFR) must be > 2.7 GHz
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PCB layout example
Figure 19 shows a PCB layout example for the application schematic in Figure 18.
A double-sided FR-4 board of 1.6mm thickness is used. This PCB has ground planes on both
bottom layer and top layer to ensure good grounding of critical component. Additionally,
there are ground areas on the component side of the board to ensure sufficient grounding of
critical components. A large number of via holes connect the top layer ground areas to the
bottom layer ground plane.
No components in bottom layer
Top silk screen
Bottom view
Top view
Figure 19 nRF2402/nRF2402G RF layout with single ended connection to 50Ω antenna and
0603 size passive components
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DEFINITIONS
Data sheet status
Objective product specification
Preliminary product
specification
Product specification
This datasheet contains target specifications for product development.
This datasheet contains preliminary data; supplementary data may be
published from Nordic Semiconductor ASA later.
This datasheet contains final product specifications. Nordic Semiconductor
ASA reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Limiting values
Stress above one or more of the limiting values may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or at any other conditions above those given in the
Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may
affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Table 19. Definitions.
Nordic Semiconductor ASA reserves the right to make changes without further notice to the
product to improve reliability, function or design. Nordic Semiconductor does not assume
any liability arising out of the application or use of any product or circuits described herein.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Nordic
Semiconductor ASA customers using or selling these products for use in such applications do
so at their own risk and agree to fully indemnify Nordic Semiconductor ASA for any
damages resulting from such improper use or sale.
Product Specification: Revision Date: 26/04/2005.
Datasheet order code: 260405-nRF2402/nRF2402G.
All rights reserved ®. Reproduction in whole or in part is prohibited without the prior written
permission of the copyright holder.
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YOUR NOTES
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Nordic Semiconductor ASA – World Wide Distributors
For Your nearest dealer, please see http://www.nordicsemi.no
Main Office:
Vestre Rosten 81, N-7075 Tiller, Norway
Phone: +47 72 89 89 00, Fax: +47 72 89 89 89
Visit the Nordic Semiconductor ASA web site at http://www.nordicsemi.no
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