P4C1981/P4C1981L, P4C1982/P4C1982L ULTRA HIGH SPEED 16K x 4 CMOS STATIC RAMS P4C1981/1981L, P4C1982/1982L FEATURES Full CMOS, 6T Cell 5V ± 10% Power Supply High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 12/15/20/25/35 ns (Industrial) – 15/20/25/35/45 ns (Military) Data Retention with 2.0V Supply, 10 µA Typical Current (P4C1981L/1982L (Military) Low Power Operation (Commercial/Military) – 715 mW Active – 12/15 – 550/660 mW Active – 20/25/35/45 – 193/220 mW Standby (TTL Input) – 83/110 mW Standby (CMOS Input) P4C1981/1981L – 5.5 mW Standby (CMOS Input) P4C1981L/82L (Military) Separate Inputs and Outputs – P4C1981/L Input Data at Outputs during Write – P4C1982/L Outputs in High Z during Write Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil DIP, SOJ – 28-Pin 350 x 550 mil LCC Output Enable and Dual Chip Enable Functions DESCRIPTION CMOS is used to reduce power consumption to a low 715 mW active, 193 mW standby. For the P4C1982L and P4C1981L, power is only 5.5 mW standby with CMOS input levels. The P4C1981/L and P4C1982/L are members of a family of PACE RAM™ products offering fast access times. The P4C1981/L and P4C1982/L are 65,536-bit (16Kx4) ultra high-speed static RAMs similar to the P4C198, but with separate data I/O pins. The P4C1981/L feature a transparent write operation when OE is low; the outputs of the P4C1982/L are in high impedance during the write cycle. All devices have low power standby modes. The RAMs operate from a single 5V ± 10% tolerance power supply. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Current drain is typically 10 µA from 2.0V supply. The P4C1981/L and P4C1982/L are available in 28-pin 300 mil DIP and SOJ, and in 28-pin 350x550 mil LCC packages providing excellent board level densities. Access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. FUNCTIONAL BLOCK DIAGRAM I1 I2 I3 I4 INPUT DATA CONTROL COLUMN I/O O1 O2 O3 O4 COLUMN SELECT CE1 A CE2 WE OE (6) A P4C1982 28 V CC 2 27 A2 A3 3 26 A13 A 12 4 25 A4 5 24 A5 6 23 A6 7 22 A7 8 21 I4 I3 A8 9 20 O4 I1 10 19 O3 I2 11 18 O2 CE1 12 17 O1 OE GND 13 16 WE 14 15 CE2 A11 A10 A9 A3 A4 2 28 1 5 27 26 25 A5 A6 6 24 7 23 A7 A8 8 22 9 21 I1 10 20 I2 11 19 CE1 12 13 DIP (P5, D5-2), SOJ (J5) TOP VIEW P4C1981/ 1982 P4C1981 3 4 VCC A 13 1 A1 14 15 16 18 17 A12 A11 A10 A9 I4 I3 O4 O3 O2 WE O1 A A0 OE 65,536-BIT MEMORY ARRAY ROW SELECT GND CE2 A (8) A2 A1 A0 PIN CONFIGURATIONS LCC (L5) TOP VIEW Means Quality, Service and Speed 1Q97 81 P4C1981/1981L, P4C1982/1982L MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C Symbol Ambient Temperature Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Parameter VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol Parameter Conditions Typ. Unit GND VCC 0V 5.0V ± 10% CIN Input Capacitance VIN = 0V 5 pF 0V 0V 5.0V ± 10% 5.0V ± 10% COUT Output Capacitance VOUT = 0V 7 pF Military –55°C to +125°C –40°C to +85°C Industrial 0°C to +70°C Commercial DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter P4C1981 / 1982 Min Max Test Conditions VIH Input High Voltage 2.2 VIL Input Low Voltage –0.5(3) VHC CMOS Input High Voltage VLC CMOS Input Low Voltage VCD Input Clamp Diode Voltage VCC = Min., IIN = –18 mA VOL Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current VOH ILI P4C1981L / 82L Unit Min Max VCC +0.5 2.2 VCC +0.5 V 0.8 –0.5(3) 0.8 VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5 –0.5(3) IOL = +8 mA, VCC = Min. IOH = –4 mA, VCC = Min. VCC = Max. V 0.2 V –1.2 –1.2 V 0.4 0.4 V 0.2 2.4 2.4 V +10 +5 –5 n/a +5 n/a µA Com’l. –10 –5 Mil. VIN = GND to VCC –0.5(3) V ILO Output Leakage Current Mil. Ind./Com’l. –10 –5 +10 +5 –5 n/a +5 n/a µA ISB Standby Power Supply CE1, CE2 ≥ VIH, Mil. Current (TTL Input Levels) VCC = Max., Ind./Com’l. f = Max., Outputs Open ___ ___ 40 35 ___ ___ 40 n/a mA ISB1 Standby Power Supply Current (CMOS Input Levels) CE1, CE2 ≥ VHC, Mil. VCC = Max., Ind./Com’l. f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC ___ ___ 20 15 ___ ___ 1.0 n/a mA VCC = Max., CE1, CE2 = VIH VOUT = GND to VCC n/a = Not Applicable Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM ratingconditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 82 P4C1981/1981L, P4C1982/1982L POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Dynamic Operating Current* ICC Temperature Range Commercial –10 –12 –15 –20 –25 –35 –45 180 170 160 155 150 N/A N/A mA Industrial N/A 180 170 160 155 150 N/A mA Military N/A N/A 170 160 155 150 145 mA Unit *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIL, OE = VIH DATA RETENTION CHARACTERISTICS (P4C1981L/P4C1982L Military Temperature Only) Symbol Parameter Test Condition VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR† Operation Recovery Time Min Typ.* VCC= 2.0V 3.0V Max VCC= 2.0V 3.0V 2.0 V 10 CE1 or CE2 ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V 15 600 tRC = Read Cycle Time † This parameter is guaranteed but not tested. tRC§ ns DATA RETENTION WAVEFORM DATA RETENTION MODE 4.5V VDR ≥ 2V 4.5V t CDR CE1 or CE2 tR VDR VIH VIH 1348 07 83 µA ns DATA RETENTION WAVEFORM VCC 900 0 *TA = +25°C § Unit P4C1981/1981L, P4C1982/1982L AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. -10 Parameter -12 Min Max Min -20 -25 -35 -45 Unit Max Min Max Min Max Min Max Min Max Min Max tRC Read Cycle Time tAA Address Access Time 10 12 15 20 25 35 45 ns tAC Chip Enable Access Time 10 12 15 20 25 35 45 ns tOH Output Hold from Address Change 2 2 2 2 2 2 2 ns tLZ Chip Enable to Output in Low Z 2 2 2 2 2 2 2 ns tHZ Chip Disable to Output in High Z 6 7 8 10 10 15 15 ns tOE Output Enable Low to Data Valid 6 7 8 12 15 21 27 ns tOLZ Output Enable to Output in Low Z 10 -15 2 tOHZ Output Disable to Output in High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 12 15 2 2 6 7 0 20 0 2 9 12 0 15 35 2 9 0 10 25 2 10 0 20 45 2 14 0 25 ns ns 15 0 25 ns 30 OE controlled)(5) READ CYCLE NO.1 (OE t RC (10) ADDRESS t AA OE t OE t OLZ CE1, CE2 t OH (9) t OHZ(9) t AC t LZ (9) t HZ(9) DATA OUT Notes: 5. WE is HIGH for READ cycle. 6. CE1, CE2 and OE are LOW for READ Cycle. 7. OE is LOW for the cycle. 8. ADDRESS must be valid prior to or coincident with, CE1, and CE2 transition LOW. 9. Transition is measured ±200mV from steady state voltage prior to change, with loading as specified in Figure 1. 10. Read Cycle Time is measured from the last valid address to the first transitioning address. 84 ns ns P4C1981/1981L, P4C1982/1982L READ CYCLE NO. 2 (ADDRESS Controlled)(5,6) t RC (10) ADDRESS t AA t OH PREVIOUS DATA VALID DATA OUT DATA VALID 1520 05 CE1, CE2 Controlled)(5,7,8) READ CYCLE NO. 3 (CE tRC CE 1, CE 2 (9,11) (11) t HZ t AC (9,11) t LZ DATA OUT DATA VALID I V CC t CC (11) HIGH IMPEDANCE t PU (11) PD SUPPLY CURRENT I SB Note: 11. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them. 85 P4C1981/1981L, P4C1982/1982L AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter –10 –12 –15 –20 –35 –25 –45 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit tWC Write Cycle Time 10 12 13 15 20 30 40 ns tCW Chip Enable Time to End of Write 7 8 10 15 20 30 35 ns tAW Address Valid to End of Write 7 8 10 15 20 25 35 ns tAS Address Set-up Time Write Pulse Width 0 0 0 0 0 0 0 ns 8 9 10 15 20 25 35 ns tAH Address Hold Time from End of Write 0 0 0 0 0 0 0 ns tDW Data Valid to End of Write 5 6 7 10 13 15 20 ns tDH Data Hold Time 0 0 0 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write tAWE Write Enable to Data-out Valid (P4C1981) Data-in Valid to Data-out Valid (P4C1981) tWP tADV 5 2 6 2 7 2 8 2 10 10 2 2 2 ns ns 10 12 13 18 20 30 35 ns 10 12 13 18 20 30 35 ns WRITE CYCLE NO. 1 (WITH OE HIGH) tWC (15) ADDRESS tAH OE tCW CE 1, CE 2 tAS 15 tAW WE t WP t OHZ t DW DATA IN DATA OUT 86 tDH P4C1981/1981L, P4C1982/1982L WE CONTROLLED)(13,14) WRITE CYCLE NO. 2 (WE t WC (15) ADDRESS t CW CE1, CE2 t AW t WP t AH WE t AS t DW DATA IN t DH DATA VALID (9,14) (9) t OW t WZ DATA OUT P4C1982 DATA UNDEFINED HIGH IMPEDANCE t ADV t AWE DATA OUT P4C1981 DATA VALID 1520 08 CE1, CE2 CONTROLLED)(11,12) WRITE CYCLE NO. 3 (CE t WC (15) ADDRESS t AS t CW CE 1, CE 2 t AH t WR t AW t WP WE t DW DATA IN DATA OUT P4C1982 t DH DATA VALID HIGH IMPEDANCE DATA OUT P4C1981 tADV DATA VALID Notes: 12. CE (CE1, CE2and WE must be LOW for WRITE cycle. 13. OE is LOW for WRITE cycle. 14. If CE1 or CE2 goes HIGH simultaneously with WE HIGH, theoutput remains in a high impedance state. HIGH IMPEDANCE 15. Write Cycle Time is measured from the last valid address to the first transitioning address. 87 P4C1981/1981L, P4C1982/1982L TRUTH TABLE AC TEST CONDITIONS P4C1981/L (P4C1982/L) GND to 3.0V CE1 CE2 WE OE Input Rise and Fall Times 3ns H X X X Standby High Z Input Timing Reference Level 1.5V X H X X Standby High Z Output Timing Reference Level 1.5V L L H H Output Inhibit High Z See Figures 1 and 2 L L H L READ DOUT L L L H WRITE High Z L L L L WRITE DIN (High Z) Input Pulse Levels Output Load Mode Output +5V RTH = 166.5Ω 480Ω DOUT DOUT 255Ω V TH = 1.73V 30pF* (5pF* for tHZ, tLZ, tOHZ, tOLZ , tWZ and tOW) 30pF* (5pF* for tHZ , t,LZ 30pF* (5pF* tLZ t , tOHZ, tOLZ, HZ,for t and t ) ) WZ tWZ andOW tOW Figure 2. Thevenin Equivalent Figure 1. Output Load * including scope and test fixture. Note: Because of the ultra-high speed of the P4C1981/L and P4C1982/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). 88 P4C1981/1981L, P4C1982/1982L PACKAGE SUFFIX Package Suffix TEMPERATURE RANGE SUFFIX Temperature Range Suffix Description P J L D Plastic DIP, 300 mil wide standard Plastic SOJ, 300 mil wide standard Leadless Chip Carrier (ceramic) CERDIP, 300 mil wide standard Description Commercial Temperature Range, 0°C to +70°C. Industrial Temperature Range, –40°C to +85°C. Military Temperature Range, –55°C to +125°C. Mil. Temp. with MIL-STD-883 Class B compliance. C I M MB ORDERING INFORMATION P4C P4C 1981 1982 l — ss p t Temperature Range Package Code Speed (Access/Cycle Time) Low Power Designator: Blank = None, L = Low Power Device Number Static RAM Prefix l = Ultra-low standby power designator L, if needed. ss = Speed (access/cycle time in ns), e.g., 25, 35 p = Package code, i.e., P, J, L, D. t = Temperature range, i.e., C, M, MB. SELECTION GUIDE The P4C1981 and P4C1982 are available in the following temperature, speed and package options. Temperature Range Commercial Industrial Military Temp. Military Processed* Speed (ns) Package Plastic DIP Plastic SOJ Plastic DIP Plastic SOJ CERDIP LCC CERDIP LCC 10 12 15 20 25 35 45 -10PC -10JC N/A N/A N/A N/A -12PC -12JC -12PI -12JI N/A N/A -15PC -15JC -15PI -15JI -15DM -15LM -20PC -20JC -20PI -20JI -20DM -20LM -25PC -25JC -25PI -25JI -25DM -25LM N/A N/A -35PI -35JI -35DM -35LM N/A N/A N/A N/A -45DM -45LM N/A N/A N/A N/A * Military temperature range with MIL-STD-883, Class B processing. N/A = Not available 89 -15DMB -20DMB -25DMB -15LMB -20LMB -25LMB -35DMB -45DMB -35LMB -45LMB P4C1981/1981L, P4C1982/1982L 90