TI SN74ALVC16373

SN74ALVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS257B – JANUARY 1993 – REVISED JULY 1995
D
D
D
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus  Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
ESD Protection Exceeds 2000 V Per
MIL-STD-833C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
description
This 16-bit transparent D-type latch is designed
for 3.3-V VCC operation; it is tested at 2.5-V, 2.7-V,
and 3.3-V VCC.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
The SN74ALVC16373 is particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (highor low-logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVC16373 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16373 is characterized for operation from – 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ALVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS257B – JANUARY 1993 – REVISED JULY 1995
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic symbol†
1OE
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
48
24
25
47
logic diagram (positive logic)
1OE
1EN
C3
1LE
C1
C4
3D
1D1
2
1
3
44
5
43
6
41
8
40
9
38
11
37
12
35
48
2EN
46
36
1
4D
13
2
14
33
16
32
17
30
19
29
20
27
22
26
23
47
1Q1
1Q1
1Q2
1Q3
1Q4
To Seven Other Channels
1Q5
1Q6
1Q7
2OE
1Q8
2Q1
2LE
24
25
2Q2
2Q3
C1
2D1
36
1D
2Q4
2Q5
2Q6
2Q7
To Seven Other Channels
2Q8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2
2
1D
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• DALLAS, TEXAS 75265
13
2Q1
SN74ALVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS257B – JANUARY 1993 – REVISED JULY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . 0.85 W
DL package . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
VCC
Supply voltage
MIN
MAX
2.3
3.6
VIH
High level input voltage
High-level
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VIL
Low level input voltage
Low-level
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI
VO
Input voltage
0
Output voltage
0
IOH
High-level output current
IOL
∆t /∆v
Low-level output current
0.7
0.8
VCC
VCC
– 12
VCC = 3 V
VCC = 2.3 V
– 24
VCC = 2.7 V
VCC = 3 V
12
Input transition rise or fall rate
• DALLAS, TEXAS 75265
V
V
2
VCC = 2.3 V
VCC = 2.7 V
TA
Operating free-air temperature
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
POST OFFICE BOX 655303
1.7
UNIT
– 12
V
V
V
mA
12
mA
24
0
10
ns / V
– 40
85
°C
3
SN74ALVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS257B – JANUARY 1993 – REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH = – 100 µA
IOH = – 6 mA
VOH
VOL
II
IOZ‡
ICC
VIH = 1.7 V
VIH = 1.7 V
2.3 V
VCC – 0.2
2
2.3 V
1.7
IOH = – 12 mA
VIH = 2 V
VIH = 2 V
2.7 V
2.2
3V
2.4
IOH = – 24 mA
IOL = 100 µA
VIH = 2 V
3V
2
MIN to MAX
0.2
IOL = 6 mA
IOL = 12 mA
VIL = 0.7 mA
VIL = 0.7 mA
2.3 V
0.4
2.3 V
0.7
IOL = 12 mA
IOL = 24 mA
VIL = 0.8 mA
VIL = 0.8 mA
2.7 V
0.4
3V
0.55
45
VI = 1.7 V
VI = 0.8 V
3V
– 45
3V
75
VI = 2 V
VI = 0 to 3.6 V
3V
–75
One input at VCC – 0.6 V,
Control inputs
Inputs
±5
2.3 V
IO = 0
Other inputs at VCC or GND
UNIT
V
3.6 V
VO = VCC or GND
VI = VCC or GND,
nICC
Ci
MIN to MAX
VI = VCC or GND
VI = 0.7 V
II(hold)
(
)
TA = – 40°C to 85°C
MIN
TYP
MAX
VCC†
TEST CONDITIONS
V
µA
µA
3.6 V
± 500
3.6 V
± 10
µA
3.6 V
40
µA
3 V to 3.6 V
750
µA
VI = VCC or GND
3
33V
3.3
pF
6
Co
VO = VCC or GND
3.3 V
† For conditions shown as MIN or MAX use the appropriate values under recommended operating conditions.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
7
pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 and 2)
VCC = 2.5 V
± 0.2 V
MIN
tw
tsu
Pulse duration, LE high or low
th
Hold time, data after LE↓
4
Setup time, data before LE↓
POST OFFICE BOX 655303
MAX
VCC = 2.7 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
3.3
3.3
3.3
ns
1
1
1.1
ns
1.5
1.7
1.4
ns
• DALLAS, TEXAS 75265
SN74ALVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS257B – JANUARY 1993 – REVISED JULY 1995
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
D
VCC = 2.5 V
± 0.2 V
MIN
MAX
Q
1
LE
Q
ten
OE
tdis
OE
tpd
d
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
5.1
4.3
1.1
3.6
1
5.5
4.6
1
3.9
Q
1
6.5
5.7
1
4.7
ns
Q
1.9
5.3
4.5
1.4
4.1
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
d
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 50 pF,
pF
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f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
19
22
4
5
UNIT
pF
5
SN74ALVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS257B – JANUARY 1993 – REVISED JULY 1995
"
PARAMETER MEASUREMENT INFORMATION
0.2 V
VCC = 2.5 V
4.6 V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
4.6 V
GND
500 Ω
tw
LOAD CIRCUIT
2.3 V
2.3 V
Timing
Input
1.2 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.3 V
Data
Input
1.2 V
1.2 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.2 V
1.2 V
0V
tPLH
tPHL
VOH
1.2 V
2.3 V
Output
Control
(low-level
enabling)
1.2 V
1.2 V
VOL
tPLZ
2.3 V
Output
Waveform 1
S1 at 4.6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.2 V
0V
tPZL
2.3 V
Output
1.2 V
1.2 V
tsu
Input
Input
1.2 V
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
1.2 V
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
v
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
v
v
SN74ALVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS257B – JANUARY 1993 – REVISED JULY 1995
"
PARAMETER MEASUREMENT INFORMATION
0.3 V
VCC = 2.7 V AND 3.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
500 Ω
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
2.7 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
3V
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
0V
tPZL
2.7 V
Output
1.5 V
1.5 V
tsu
Input
Input
1.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
1.5 V
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
v
v
v
Figure 2. Load Circuit and Voltage Waveforms
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• DALLAS, TEXAS 75265
7
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