TI TPS9103PW

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
D
D
D
D
D
D
D
Charge Pump Provides Negative Gate Bias
for Depletion-Mode GaAs Power Amplifiers
Buffered Clock Output to Drive Additional
External Charge Pump
135-mΩ High-Side Switch Controls Supply
Voltage to the GaAs Power Amplifier
Power-Good Circuitry Prevents High-Side
Switch Turn-on Until Negative Gate Bias is
Present
Charge Pump Can Be Driven From the
Internal Oscillator or An External Clock
10-µA Maximum Standby Current
Low-Profile (1.2-mm Max Height), 20-Pin
TSSOP Package
PW PACKAGE
(TOP VIEW)
GATE_BIAS
VCC
C1–
C1+
BATT_IN
BATT_IN
BATT_IN
PGP
PG
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
CLK
BCLK
GND
BATT_OUT
BATT_OUT
BATT_OUT
SW_EN
OSC_EN
EN
description
The TPS9103 is a highly integrated power supply for depletion-mode GaAs power amplifiers (PA) in cellular
handsets and other wireless communications equipment. Functional integration and low-profile packaging
combine to minimize circuit-board area and component height requirements. The device includes: a p-channel
MOSFET configured as a high-side switch to control the application of power to the PA; a driver for the high-side
switch with a logic-compatible input; a charge pump to provide negative gate-bias voltage; and logic to prevent
turn-on of the high-side switch until gate bias is present. The high-side switch has a typical on-state resistance
of 135 mΩ.
The TPS9103 is available in a 20-pin thin shrink small-outline package (TSSOP) or in chip form. Contact factory
for die sales. The device operates over a junction temperature range of – 25°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICE
TA
TSS0P
(PW)
– 25°C to 85°C
TPS9103PWLE
CHIP FORM
(Y)
TPS9103Y
The PW package is only available left-end taped and reeled
(indicated by the LE suffix on the device type).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
functional block diagram
BATT_IN
5, 6, 7
3
3
14, 15, 16
BATT_OUT
VCC
VCC
BCLK
VDD
EN
OSC_EN
UVLO
2
13
18
UVDLO
20
9
11
12
REF
+
OSC
C1 +
C1 –
GND
2
PG
Vref
19
R
PGP
SW_EN
PG
Comparator
CLK
8
4
3
Inverting
Charge
Pump
0.6R
1
10, 17
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GATE_BIAS
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
TPS9103Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS9103. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform. Contact factory for die sales.
BONDING PAD ASSIGNMENTS
(3)
(7)
(1 )
(2)
(20)
(19)
(18)
(6)
VCC VDD
2
20
4
C1 +
C1 –
(4)
BATT_IN
PGP
PG
(17)
EN
OSC_EN
SW_EN
CLK
116
1
3
5, 6, 7
8
9
11
12
13
GATE_BIAS
14, 15, 16
BATT_OUT
TPS9103Y
18
19
BCLK
(16)
10, 17
(5)
GND
(15)
(6)
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJ max = 150°C
(14)
ALL DIMENSIONS ARE IN MILS.
(7)
(8)
TOLERANCES ARE ± 10%.
(9)
(10)
(11)
(12)
(13)
83
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3
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
Terminal Functions
TERMINAL
NAME
4
DESCRIPTION
NO.
GATE_BIAS
1
Negative gate-bias output voltage
VCC
C1–
2
Logic supply voltage
3
External capacitor connection (inverting charge pump)
C1+
4
External capacitor connection (inverting charge pump)
BATT_IN
5
High-side switch input voltage
BATT_IN
6
High-side switch input voltage
BATT_IN
7
High-side switch input voltage
PGP
8
Program input for power-good threshold
PG
9
Power-good output
GND
10
Ground
EN
11
Chip-enable input
OSC_EN
12
Oscillator-enable input
SW_EN
13
High-side switch enable input
BATT_OUT
14
High-side switch output voltage
BATT_OUT
15
High-side switch output voltage
BATT_OUT
16
High-side switch output voltage
GND
17
Ground
BCLK
18
Buffered clock output
CLK
19
Clock (bidirectional)
VDD
20
Charge-pump supply voltage
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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
detailed description
high-side switch and driver (BATT_IN, BATT_OUT, SW_EN)
The high-side switch is a p-channel MOSFET with a maximum on-state resistance of 180 mΩ
(VI(BATT_IN) = 6 V and VCC = 3.3 V). The driver pulls the gate of the high-side switch to GATE_BIAS instead of
ground to reduce the MOSFET on-state resistance. Gate breakdown considerations limit the voltage between
BATT_IN and GATE_BIAS to 15 V. Extremely fast switching times are not required in this application, and the
high-side switch/driver is designed to provide 2 µs maximum switching times with minimum power consumption.
The GaAs depletion-mode MOSFETs in the PA are protected from damage at power-up by internal logic that
inhibits the driver until negative gate bias is available. The control input SW_EN is compatible with 3-V and 5-V
CMOS logic; a logic-high input turns the high-side switch on.
oscillator (OSC_EN, CLK)
The internal oscillator drives the charge pump at 50 kHz with a nominal duty cycle of 50% when both the EN
and OSC_EN inputs are logic lows. CLK outputs the internal oscillator signal (no buffer). A logic-high input to
OSC_EN disables the internal oscillator and allows the charge pump to operate from an external clock
connected to CLK. When an external clock with negative overshoot is applied, a Schottky diode must be added
to limit the amplitude of the overshoot.
charge pump (GATE_BIAS, C1+, C1–)
The inverting charge pump generates the negative gate-bias voltage output at GATE_BIAS.
chip enable (EN)
A logic high on EN shuts down the internal functions of the TPS9103 and turns the bias system off, reducing
the supply current to less than 10 µA. A low input on EN causes normal operation to resume.
power good (PG, PGP)
PG output is logic high when GATE_BIAS is in regulation. PG output is logic low when GATE_BIAS is not in
regulation. The high-side switch is disabled and PG is forced to logic low whenever the magnitude of
GATE_BIAS is less than 0.6 × VDD. A modified threshold for the power-good function can be achieved by
programming PGP with an external resistor.
undervoltage lockout for VCC and VDD (UVLO and UVDLO)
Undervoltage lockout prevents operation at supply voltages too low for proper operation. When UVLO or
UVDLO is active, all power-switch drives are forced to the off state and bias is removed from unneeded
functions. Hysteresis is provided to minimize cycling on and off because of source impedance loading when the
supply voltage is close to the threshold.
buffered clock output (BCLK)
The buffered clock output is a driver for an external charge pump. When the optional external charge pump is
not needed, BCLK should be left unconnected. For more details, see the application section.
supply input for inverting charge pump (VDD)
VDD is the supply voltage for the inverting charge pump. In normal operation, VDD is connected to VCC. If the
negative gate-bias needs to be larger than VCC (i.e., more negative), then a higher voltage supply needs to be
connected to VDD. This can be supplied from an external charge pump driven from BCLK.
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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PW
645 mW
6.5 mW/°C
353 mW
255 mW
Maximum values are calculated using a derating factor based on RθJA = 154°C/W for the package. These devices are
mounted on an FR4 board with no special thermal considerations.
PD– Maximum Continuous Dissipation – mW
700
PW Package
RθJA = 154°C/W
600
500
400
300
200
100
0
25
35
45
55
65
75
85
TA – Free-Air Temperature – °C
Figure 1. Dissipation vs Free-Air Temperature
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
High-side switch input voltage range, BATT_IN (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V
Supply voltage range, VCC, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Differential voltage, |BATT_IN|–|GATE_BIAS| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Input voltage range, SW_EN, EN, CLK, OSC_EN, PG . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
GATE_BIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 5.5 V
Output current, PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Output current, BCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output current, GATE_BIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Output current, BATT_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
Peak output current, BATT_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 A
Maximum external clock frequency, CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 kHz
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 25°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to device GND.
2. Differential voltage calculated: |VImax| + |GATE_BIAS|
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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
recommended operating conditions
MIN
Input voltage, BATT_IN
NOM
MAX
UNIT
3
9
V
Supply voltage, VCC, VDD
2.7
5.5
V
Output voltage, GATE_BIAS, VO
–2
–5
V
Continuous output current, GATE_BIAS
0
10
mA
Continuous output current, BATT_OUT
0
Charge-pump capacitor value at C1+/C1–
2
External clock frequency, CLK
25
High-level input voltage, VIH
75
2
0.8
V
–1
1
µA
–25
125
°C
Input current, II
Operating junction temperature, TJ
kHz
V
SW_EN, EN, OSC_EN, CLK
Low-level input voltage, VIL
A
µF
0.33
electrical characteristics over recommended operating junction temperature range,
BATT_IN = 6 V, VCC = VDD = 3.3 V, IO(BATT_OUT) = 0.5 A, IO(GATE_BIAS) = 2 mA,
EN = OSC_EN = 0 V, SW_EN = VCC, C1 = 0.33 µF (unless otherwise noted)
charge pump
PARAMETER
TEST CONDITIONS
MIN
Output voltage
–3
Output resistance
TYP
–3.10
MAX
–3.3
UNIT
V
Ω
95
high-side switch
PARAMETER
Dran to source on-state
on state resistance
Dran-to-source
Leakage current
TEST CONDITIONS
MIN
TA = 25°C
TA = – 25°C to 85°C
TYP
135
MAX
UNIT
180
210
TA = 25°C,
TA = –25°C to 85°C,
VI(BATT_IN) = 3 V
TA = 25°C,
VI(BATT_IN) = 9 V,
SW_EN = 0 V
1
TA = 85°C,
VI(BATT_IN) = 9 V,
SW_EN = 0 V
10
160
BATT_IN = 3 V
220
mΩ
260
µA
Delay to high-level output
SW_EN from 0 to VCC
0.2
2
µs
Delay to low-level output
SW_EN from VCC to 0
0.9
2
µs
oscillator
PARAMETER
Frequency
TEST CONDITIONS
VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
Duty cycle
MIN
TYP
MAX
35
50
60
40%
50%
60%
UNIT
kHz
buffered clock output (BCLK)
PARAMETER
TEST CONDITIONS
MIN
Output resistance
TYP
MAX
10
High-level output voltage
I(BCLK) = 30 mA
Low-level output voltage
I(BCLK) = 30 mA
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0.3
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UNIT
V
7
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
power good (PG)
PARAMETER
Threshold voltage
TEST CONDITIONS
On-state voltage
VDD = 2.7 V to 5.5 V
IO(PG) = 500 µA, VCC = 2.7 V to 5.5 V
Off-state voltage
IO(PG) = – 500 µA,
VCC = 2.7 V to 5.5 V
MIN
TYP
MAX
0.60 × VDD
UNIT
V
0.3
VCC – 0.3
V
V
Hysteresis
130
mV
power good (PGP)
PARAMETER
TEST CONDITIONS
Input impedance
MIN
TYP
MAX
85
UNIT
kΩ
undervoltage lockout (UVLO + UVDLO)
PARAMETER
Start threshold voltage
TEST CONDITIONS
VCC increasing
MIN
TYP
2.4
Hysteresis
MAX
2.7
130
UNIT
V
mV
supply current (ICC and IDD)
PARAMETER
TEST CONDITIONS
Standby mode
EN = VCC
Undervoltage lockout
VCC = VDD < 2.3 V
No load
Operating mode
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MIN
TYP
MAX
UNIT
1
10
µA
35
50
µA
300
500
µA
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
5
VI(BATT_IN)
6
C1
0.1 µF
7
2
VCC
20
+
C3
4.7 µF
C4
0.1 µF
4
10 kΩ
3
13
10 kΩ
11
10 kΩ
BATT_OUT
BATT_IN
BATT_OUT
BATT_IN
BATT_OUT
VCC
VDD
GATE_BIAS
14
15
IO(BATT_OUT)
16
1
C5
+
0.1 µF
C1+
C6
4.7 µF
IO(GATE_BIAS)
TSP9103
C2
0.33 µF
VCC
BATT_IN
12
C1–
PG
SW_EN
PGP
EN
CLK
OSC_EN
BCLK
GND
9
8
19
18
IO(BCLK)
GND
17
10
Figure 2. Test Circuit
4
3
Input and Output Voltage – V
VCC
2
1
0
–1
–2
GATE BIAS
–3
0
5
10
15
20
25 30
t – Time – ms
35
40
45
50
Figure 3. GATE_BIAS Output Voltage Rise Time
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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
IO – GATE_BIAS = 5 mA
VDD = VCC = 5 V
20 mV/div
0
5
10
15
20
25
30
t – Time – µs
Figure 4. Ripple on GATE_BIAS
10
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35
40
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
rDS(
DS(on))
source on
state resistance
Static drain
drain-source
on-state
Fosc
Oscillator frequency
VO
Output voltage
VIT
Threshold voltage
Supply current (ICC + IDD)
r DS(on) – Static Drain-Source On-State Resistance – m Ω
vs
190
GATE-SOURCE VOLTAGE,
180
dc (VO(GATE_BIAS) –VI(BATT_IN))
170
160
150
140
130
120
110
100
– 12
– 11
– 10
–9
–8
–7
VGS – Gate-Source Voltage,
dc (VO(GATE_BIAS) –VI(BATT_IN))
–6
r DS(on) – Static Drain-Source On-State Resistance – m Ω
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs Gate-source voltage, dc
5
vs Temperature
6
vs Supply voltage
7
vs Temperature
8
vs Output current
9
vs CLK frequency
10
vs Temperature
11
vs Supply voltage
12
vs Temperature
13
HIGH-SIDE SWITCH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
TEMPERATURE
180
160
140
120
100
80
60
– 50
– 25
Figure 5
0
25
50
75
T – Temperature –°C
100
125
Figure 6
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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
SUPPLY VOLTAGE
OSCILLATOR FREQUENCY
vs
TEMPERATURE
49.5
f osc – Oscillator Frequency – kHz
f osc – Oscillator Frequency – kHz
49
48
47
46
2.5
4.5
3.5
4
VCC – Supply Voltage – V
3
5
49
3.3 V
48.5
2.7 V
48
5V
47.5
47
– 50
5.5
– 25
Figure 7
–1
– 3.05
VO – Output Voltage – V
VO – Output Voltage – V
–3
VCC = 2.7 V
VCC = 3.3 V
–4
VCC = 5 V
– 3.1
– 3.15
– 3.2
– 3.25
–5
– 3.3
–6
0
1
2
3
4
5
6
7
8
IO – Output Current – mA
9
10
25
30
35
40
45
50
Figure 10
POST OFFICE BOX 655303
55
60
f – CLK Frequency – kHz
Figure 9
12
125
GATE BIAS
OUTPUT VOLTAGE
vs
CLK FREQUENCY
0
–3
100
Figure 8
GATE BIAS
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
–2
75
0
25
50
T – Temperature – °C
• DALLAS, TEXAS 75265
65
70
75
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
TYPICAL CHARACTERISTICS
UNDERVOLTAGE LOCKOUT (VCC, VDD)
THRESHOLD VOLTAGE
vs
TEMPERATURE
SUPPLY CURRENT (ICC + IDD)
vs
SUPPLY VOLTAGE
450
Supply Current (ICC + I DD ) – µ A
2.63
2.61
2.59
2.57
2.55
– 50
– 25
0
75
25
50
T – Temperature – °C
100
400
350
300
250
200
2.7
125
3.2
3.7
4.2
4.7
Supply Voltage – V
Figure 11
5.2
5.7
Figure 12
SUPPLY CURRENT (ICC + IDD)
vs
TEMPERATURE
500
450
Supply Current (ICC + I DD ) – µ A
V IT – Threshold Voltage – V
2.65
5.5 V
400
350
3.3 V
300
250
200
– 50
– 25
0
25
50
75
T – Temperature – °C
100
125
Figure 13
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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch packages requires special attention to power
dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection
surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given
component.
Three basic approaches for enhancing thermal performance are listed below:
D
D
D
Improving the power-dissipation capability of the PWB design
Improving the thermal coupling of the component to the PWB
Introducing airflow in to the system
Using the given RθJA for this IC, the maximum power dissipation can be calculated with the equation:
P max
D
* TA
+ TJmax
R
qJA
For the TPS9103, the power dissipation is in the PMOSFET. To calculate the power, use: I2 R where I is the
current through the device and R is the internal resistance as shown in the electrical characteristics table.
For a VI of 6 V, the resistance at 85°C is 0.210 Ω. At a current of 2 A, the peak power dissipation is:
PD
+ 22
0.210
+ 0.84 W
Assuming a duty cycle of 1/8 or 0.125, the average power is:
0.84 W
0.125
+ 0.105 W
The change in temperature is:
∆T = 0.105 W × 154°C/W = 16.2°C
and the junction temperature is:
TJ = 85°C + 16.2°C =101.2°C
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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
APPLICATION INFORMATION
introduction
Traditionally the RF power amplifier (PA) is powered directly from the battery, with a switching arrangement for
powering down when not in use. GaAs FET PAs require a negative bias voltage that must be present before
the supply is connected, or there is risk of destroying the FET. Logic must be provided to ensure the presence
of the negative bias voltage.
A secondary charge pump is necessary for systems in which the supply voltage is insufficiently high – the
negative bias produced from the charge pump is inadequate. In mobile telephony a second charge pump
(regulated or unregulated) may also be needed, e.g. for varicap diodes/VCOs and some preamplifiers. The
need for larger dynamic range or control-voltage range can become critical in certain applications.
the TPS9103 approach
The TPS9103 integrates a P-channel MOSFET high-side switch together with a selectable oscillator and charge
pump for the GaAs FET power-amplifier gate bias, which is monitored.
Complete precautions are taken to ensure that the PA supply is not enabled unless the gate bias is present while
VCC and VDD are also good. This protects the PA from inadvertent damage–without a major system size/cost
increase.
The bias regulation monitor is flexible, accommodating both fixed and programmable approaches. The fixed
resistors, provided internally, set the trip voltage to –0.6 x VDD. If VDD is 5 V, then the trip voltage is –3 V. Should
another value be preferred, it can be set by applying voltage divider to PGP. See the section “dimensioning the
external voltage divider” for more details.
The charge pump clock is also flexible. The on-chip oscillator runs at a nominal 50 kHz, or alternatively an
external oscillator can be connected to CLK. When an external clock is used, OSC_EN should be taken high
to disable the oscillator. When OSC_EN is low and the on-chip oscillator is used, CLK provides an unbuffered
clock output.
The circuit provides for a secondary charge pump driver. The buffered BCLK output can be used (with four
external components) to provide a higher supply, both for those system functions that require it and for those
GaAs PAs that need a more negative bias than is made possible by inverting the existing supply. This is
facilitated by use of single-cell Li-ion batteries.
Figure 14 shows the TPS9103 in a typical application.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
APPLICATION INFORMATION
5
Battery
4 V to 8 V
C1
0.1 µF
6
7
13
XMIT
4
C2
0.33 µF
VCC
3.3 V
C3
4.7 µF
3
2
+
C4
0.1 µF
20
11
12
BATT_IN
BATT_OUT
BATT_IN
BATT_OUT
BATT_IN
BATT_OUT
14
16
SW_EN
GATE_BIAS
C1+
1
C1–
VCC
PG
VDD
PGP
EN
CLK
OSC_EN
BCLK
17
9
8
19
18
GND
10
Figure 14. Typical Application
POST OFFICE BOX 655303
PA Gate–3 V
C5
+
0.1 µF
TSP9103
GND
16
PA Drain
15
• DALLAS, TEXAS 75265
C6
4.7 µF
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
APPLICATION INFORMATION
capacitors of the internal inverting charge pump (see Figure 15)
This charge pump inverts the voltage at VDD and provides a negative output voltage at GATE_BIAS.
TPS9103
C+
Charge
Pump
C2
GATE_BIAS
+
C–
C6
Figure 15. Internal Inverting Charge Pump
The output capacitor C6 limits the voltage ripple at GATE_BIAS:
+ O(GATE_BIAS)
Ripple
C6 f
I
V
With a capacitor C6 of 4.7 µF and an output current of 10 mA, the voltage ripple at GATE_BIAS is 42 mV.
The capacitor C2 can be calculated using an equivalent resistance method:
R
equivalent
+ C21
f
Using 0.33 µF for C2, the equivalent resistance is:
R
equivalent
+ 0.33 mF 1 50 kHz + 60.6 W
Add the internal resistance of the switches (35 Ω) to get a total resistance seen by the current:
R
TOTAL
+ 60 ) 35 + 95 W
With a total resistance of 95 Ω and 10 mA flowing through it, a voltage drop of 0.95 V occurs. With 5 V on VDD,
the output is – 4.05 V with a 42 mV ripple.
The capacitors should have a low equivalent series resistance (ESR) to maintain low ripple and low noise.
Careful layout is required. In most instances it is advisable to add a small decoupling capacitor C5 close to the
GATE_BIAS. An additional 0.1-µF capacitor at other locations may be necessary if the power amplifier is located
away from the TPS9103.
POST OFFICE BOX 655303
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17
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
APPLICATION INFORMATION
dimensioning of the external charge pump
For systems in which the bias voltage requirement is not met by inverting the power rail, the BCLK output can
be used (with four passive components) to generate a higher VDD. The higher voltage is then inverted as before
to produce the bias voltage. This voltage is also available for other parts of the main circuitry (see Figure 16).
With the TPS9103, an external charge pump could be used to increase the voltage at VDD, thereby deriving a
higher negative voltage at GATE_BIAS than would otherwise be available.
VCC
D1
BCLK
V
VDD
C7
1
D2
+
C8
Figure 16. External Charge Pump
When BCLK is low, node 1 charges up to VCC – Vdiode. When BCLK goes high, node 1 is 2 VCC – Vdiode. The
capacitor C8 charges up to 2 VCC – 2 Vdiode. This voltage can then be connected to VDD.
The magnitude of Vripple of VDD is determined by the value of C8. Capacitor value must be large enough that
the discharge during one period is not as great as the maximum voltage variation allowable. The discharge of
C8 depends on the load current.
+ O(GATE_BIAS)
V
I
C8
ripple
f
With a supply voltage of VCC = 3.3 V, a maximum voltage variation (Vripple) of 2% = 66 mV and a load of
ICC = 10 mA, the value of C8 is 3 µF. A 4.7 µF meets this requirement.
The capacitance of C7 can be calculated using an equivalent resistance method:
R
equivalent
+ C71
f
Using 0.22 µF for C7, the equivalent resistance is:
R
equivalent
+ 0.22 mF 1 50 kHz + 90 W
Add the equivalent resistance to the internal resistance of the switch (10 Ω):
RTOTAL = 90 + 10 = 100 Ω
With a total resistance of 100 Ω and with 10 mA flowing through it, a voltage drop of 1 V occurs. Thus with 3.3
V on VCC the output is 4.2 V with a 42-mV ripple.
Care must be taken that the maximum voltages are not exceeded when using BCLK as a charge pump (see
Figure 17).
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
APPLICATION INFORMATION
5
Battery
4 V to 8 V
C1
0.1 µF
6
7
13
XMIT
4
C2
0.33 µF
VCC
3.3 V
3
BATT_OUT
BATT_IN
BATT_OUT
BATT_IN
BATT_OUT
SW_EN
GATE_BIAS
2
16
1
PA Gate–3 V
C6
4.7 µF
TSP9103
C1–
VCC
PGP
CLK
12
PA Drain
15
C5
+
0.1 µF
C4
0.1 µF
11
14
C1+
PG
+
C3
4.7 µF
BATT_IN
VDD
EN
OSC_EN
BCLK
GND
17
GND
9
8
19
20
18
C7
0.22 µF
10
+
C8
4.7 µF
Figure 17. TPS9103 Configured With External Charge Pump
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
dimensioning the external voltage divider
Drain voltage should only be applied to the power amplifier when the complete negative voltage from the
GATE_BIAS output is provided to the gate of the GaAs power amplifier. For that reason there is an internal
voltage divider R/0.6R and a PG comparator in the TPS9103 (see Figure 15). When the voltage at the inverting
input of the comparator reaches zero, the output goes high and the high-side MOSFET switches on, provided
a SW_EN high signal is applied. For example, when the supply voltage at VDD is 5 V, the high-side switch is
switched on when the voltage at GATE_BIAS reaches –3 V.
This trip point can be changed to another value by using an external voltage divider connected between VDD,
GATE_BIAS, and PGP. The resistor values should be low enough to minimize the error that is present when
the internal resistor values (typ R = 100 kΩ ± 30%) are taken into consideration. Therefore, the external resistor
values, R1 and R2, are chosen within the 10-kΩ range.
TPS9103
VDD
R1
R
PG Comparator
PGP
R2
0.6 R
GATE_BIAS
Figure 18. External Voltage Divider for Setting the Trip Point
R1 = 10 kΩ. The value of R2 can then be calculated using:
R2
+ 0.6
* 0.6
V
R
[R1
DD
R1
) R] )
V
trip
V
trip
R1
where VDD = supply voltage, and Vtrip = chosen value to trip PG comparator.
The values of the internal resistor can vary about 30%, and can move the trip point. In a worst-case condition,
with a resistor variation of 30%, the shifting of the trip point can be calculated to:
DVtrip_point + VDD
20
ǒ
R1
) 1.3
R1
R
R2
POST OFFICE BOX 655303
)
0.6 R2
0.78 R
* R1R1) R
• DALLAS, TEXAS 75265
)
Ǔ
0.6 R2
R2 0.6 R
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,32
0,19
0,65
14
0,13 M
8
0,15 NOM
4,50
4,30
6,70
6,10
Gage Plane
0,25
1
7
0°– 8°
0,75
0,50
A
Seating Plane
1,20 MAX
0,10
0,10 MIN
PINS **
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064 / D 10/95
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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• DALLAS, TEXAS 75265
21
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