ICS ICS853017AM

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
GENERAL DESCRIPTION
FEATURES
The ICS853017 is a quad 1-to-1, 2.5V/3.3V/5V differential LVPECL/ECL receiver and a member of
HiPerClockS™
the HiperclocksTM family of High Performance Clock
Solutions from ICS. The ICS853017 operates with
a positive or negative power supply at 2.5V, 3.3V or
5V, and can accept both single-ended and differential inputs. For
single-ended operation, an internally generated voltage, which is
available on output pin VBB, can be used as a switching bias voltage on the unused input of the differential pair. VBB can also be
used to rebias AC coupled inputs.
• 4 differential LVPECL / ECL 1:1 receivers
ICS
• 4 differential LVPECL clock input pairs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Output frequency: >2GHz (typical)
• Translates any single ended input signal to
LVPECL levels with resistor bias on nPCLKx input
• Output skew: TBD
• Part-to-part skew: TBD
• Propagation delay: 320ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 5.25V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -5.25V to -2.375V
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100LVEL17
BLOCK DIAGRAM
PIN ASSIGNMENT
D0
nD0
Q0
nQ0
D1
nD1
Q1
nQ1
D2
nD2
Q2
nQ2
D3
nD3
Q3
nQ3
VCC
D0
nD0
D1
nD1
D2
nD2
D3
nD3
VBB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
VEE
ICS853017
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
Top View
V BB
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853017AM
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REV. A APRIL 21, 2004
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 20
VCC
Power
2
D0
Input
3
nD0
Input
4
D1
Input
5
nD1
Input
6
D2
Input
7
nD2
Input
8
D3
Input
9
nD3
Input
10
VBB
Power
Bias Voltage.
11
VEE
Power
Negative supply pin.
12, 13
nQ3, Q3
Output
Differential output pair. LVPECL interface levels.
14, 15
nQ2, Q2
Output
Differential output pair. LVPECL interface levels.
17, 18
nQ1, Q1
Output
Differential output pair. LVPECL interface levels.
19, 20
nQ0, Q0
Output
Differential output pair. LVPECL interface levels.
Core supply pins.
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Non-inver ting differential clock input.
Inver ting differential clock input. VCC/2 default when left floating.
Non-inver ting differential clock input.
Inver ting differential clock input. VCC/2 default when left floating.
Non-inver ting differential clock input.
Inver ting differential clock input. VCC/2 default when left floating.
Non-inver ting differential clock input.
Inver ting differential clock input. VCC/2 default when left floating.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
RPULLDOWN
Input Pulldown Resistor
Test Conditions
Minimum
Typical
75
Maximum
Units
KΩ
RVCC/2
Pullup/Pulldown Resistors
50
KΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
HIGH
Differential to Differential
Non Inver ting
HIGH
LOW
Differential to Differential
Non Inver ting
D0:D3
nD0:nD3
Q0:Q3
nQ0:nQ3,
0
1
LOW
1
0
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential
Non Inver ting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential
Non Inver ting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
853017AM
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2
REV. A APRIL 21, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
ABSOLUTE MAXIMUM RATINGS
Negative Supply Voltage, VEE
5.5V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-5.5V (ECL mode, VCC = 0)
Inputs, VI (LVPECL mode)
-0.5V to VCC + 0.5V
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Supply Voltage, VCC
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
VBB Sing/Source, IBB
± 0.5mA
to the device. These ratings are stress specifications only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG
-65°C to 150°C
Package Thermal Impedance, θJA
46.2°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 5.25V; VEE = 0V
Symbol
Parameter
VCC
Core Supply Voltage
IEE
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
2.375
3.3
5.25
V
46
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
Min
-40°C
Typ
Max
Min
2.275
25°C
Typ
Max
Min
2.295
85°C
Typ
Max
2.33
Units
V
VOL
Output Low Voltage; NOTE 1
VIH
Input High Voltage(Single-Ended)
2.075
2.075
2.075
VIL
Input Low Voltage(Single-Ended)
1.43
1.43
1.43
V
VBB
Output Voltage Reference; NOTE 2
1.86
1.86
1.86
V
VPP
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
D0, D1, D2, D3
High Current nD0, nD1,n D2, nD3
D0, D1, D2, D3
Input
Low Current nD0, nD1,n D2, nD3
VCMR
IIH
IIL
1.545
1.52
800
1.535
800
1.2
3.3
1.2
150
V
V
800
3.3
1.2
150
mV
3.3
V
150
µA
-10
-10
-10
µA
-150
-150
-150
µA
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
853017AM
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3
REV. A APRIL 21, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol
Parameter
-40°C
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Units
VOH
Output High Voltage; NOTE 1
1.475
1.495
1.53
V
VOL
Output Low Voltage; NOTE 1
0.745
0.72
0.735
V
VIH
Input High Voltage(Single-Ended)
1.275
VIL
Input Low Voltage(Single-Ended)
0.63
VPP
IIH
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
Input
D0, D1, D2, D3
High Current nD0, nD1,n D2, nD3
IIL
Input
Low Current
VCMR
D0, D1, D2, D3
1.275
1.275
0.63
800
0.63
800
1.2
2.5
1.2
V
mV
800
2.5
150
-10
V
1.2
150
-10
-150
-150
nD0, nD1,n D2, nD3
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
2.5
V
150
µA
-10
µA
-150
µA
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V
-40°C
25°C
85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
3.975
3.995
4.03
V
VOL
Output Low Voltage; NOTE 1
3.245
3.22
3.235
V
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
VIH
Input High Voltage(Single-Ended)
3.775
3.775
3.775
V
VIL
Input Low Voltage(Single-Ended)
3.13
3.13
3.13
V
VPP
IIH
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
Input
D0, D1, D2, D3
High Current nD0, nD1,n D2, nD3
IIL
Input
Low Current
VCMR
D0, D1, D2, D3
800
800
1.2
5
1.2
150
5
1.2
150
-10
5
V
150
µA
-10
µA
-150
-150
nD0, nD1,n D2, nD3 -150
Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
µA
853017AM
-10
mV
800
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4
REV. A APRIL 21, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
TABLE 4C. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol
-40°C
Parameter
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Units
VOH
Output High Voltage; NOTE 1
-1.025
-1.005
-0.97
V
VOL
Output Low Voltage; NOTE 1
-1.755
-1.78
-1.765
V
VIH
Input High Voltage(Single-Ended)
-1.225
-1.225
-1.225
V
VIL
Input Low Voltage(Single-Ended)
-1.87
-1.87
-1.87
V
VBB
Output Voltage Reference; NOTE 2
-1.44
-1.44
-1.44
V
VPP
IIH
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
D0, D1, D2, D3
High Current nD0, nD1,n D2, nD3
IIL
Input
Low Current
VCMR
800
800
VEE+1.2V
D0, D1, D2, D3
0
VEE+1.2V
800
0
150
-10
-150
-150
nD0, nD1,n D2, nD3
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
Symbol
OR
Min
Typ
0
V
150
µA
-10
µA
-150
µA
VCC = 2.375V TO 5.25V; VEE = 0V
-40°C
Parameter
VEE+1.2V
150
-10
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
mV
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Units
fMAX
Output Frequency
>2
>2
>2
GHz
tP LH
Propagation Delay, Low-to-High; NOTE 1
320
320
320
ps
tPHL
Propagation Delay, High-to-Low; NOTE 1
320
320
320
ps
tsk(o)
Output Skew; NOTE 2, 4
TBD
TBD
TBD
ps
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 4
TBD
TBD
TBD
ps
tR/tF
Output Rise/Fall Time
175
175
175
ps
20% to 80%
All parameters tested ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853017AM
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5
REV. A APRIL 21, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
VCC
SCOPE
nD0:nD3
LVPECL
V
V
Cross Points
PP
CMR
D0:D3
nQx
VEE
V EE
-0.375V to -3.25V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
nQy
nQy
Qx
PART 2
Qy
Qy
t sk(pp)
t sk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nD0:nD3
80%
nD0:D3
80%
VSW I N G
Clock
Outputs
20%
20%
tR
nQ0:nQ3
tF
Q0:Q3
tp
LH
OUTPUT RISE/FALL TIME
853017AM
tp
HL
PROPAGATION DELAY
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6
REV. A APRIL 21, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
PCLK
V_REF
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
1
RTT =
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
853017AM
125Ω
84Ω
FIGURE 2B. LVPECL OUTPUT TERMINATION
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7
REV. A APRIL 21, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
TERMINATION
FOR
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in Figure 3C.
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
R1
250
Zo = 50 Ohm
R3
250
+
Zo = 50 Ohm
+
Zo = 50 Ohm
-
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
2,5V LVPECL
Driv er
R2
62.5
R2
50
R4
62.5
R3
18
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
853017AM
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8
REV. A APRIL 21, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
LVPECL CLOCK INPUT INTERFACE
suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm
the driver termination requirements.
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS PCLKx/nPCLKx input
driven by the most common driver types. The input interfaces
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R1
50
CML
R3
120
R2
50
Zo = 60 Ohm
SSTL
Zo = 50 Ohm
R4
120
PCLK
PCLK
Zo = 60 Ohm
Zo = 50 Ohm
nPCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
HiPerClockS
PCLK/nPCLK
R2
120
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
C1
LVDS
R3
1K
R4
1K
PCLK
PCLK
R5
100
Zo = 50 Ohm
nPCLK
LVPECL
R1
84
C2
nPCLK
Zo = 50 Ohm
HiPerClockS
Input
R1
1K
R2
84
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
HiPerClockS
PC L K /n PC LK
R2
1K
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
3.3V LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
84
R4
84
PCLK
nPCLK
R5
100 - 200
R6
100 - 200
R1
125
HiPerClockS
PCLK/nPCLK
R2
125
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
853017AM
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9
REV. A APRIL 21, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
RELIABILITY INFORMATION
TABLE 6.
θJAVS. AIR FLOW TABLE FOR 20 LEAD SOIC
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
83.2°C/W
46.2°C/W
65.7°C/W
39.7°C/W
57.5°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853017 is: 187
853017AM
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10
REV. A APRIL 21, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
FOR
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
20 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
Maximum
20
A
--
2.65
A1
0.10
--
A2
2.05
2.55
B
0.33
0.51
C
0.18
0.32
D
12.60
13.00
E
7.40
7.60
e
H
1.27 BASIC
10.00
10.65
h
0.25
0.75
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-013, MO-119
853017AM
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11
REV. A APRIL 21, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS853017AM
ICS853017AM
20 Lead SOIC
38 per tube
-40°C to 85°C
ICS853017AMT
ICS853017AM
20 Lead SOIC on Tape and Reel
1000
-40°C to 85°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853017AM
www.icst.com/products/hiperclocks.html
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REV. A APRIL 21, 2004