PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS85354 is a 2:1/1:2 Multiplexer and a member of the HiPerClockSTM family of high perforHiPerClockS™ mance clock solutions from ICS. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 MUX switches one input to one of two outputs. This device may be useful for multiplexing multirate Ethernet Phys which have 100Mbit and 1000Mbit transmit/ receive pairs onto an optical SFP module which has a single trasmit/receive pair. Please refer to the Application Block diagram on page 2 of the data sheet. • Dual 2:1/1:2 MUX The ICS85354 is optimized for applications requiring very high performance and has a maximum operating frequency in excess of 2GHz. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards. • Propagation delay: 330ps (typical) ICS • 3 LVPECL outputs • 3 differential clock inputs • CLKx pair can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequency: 3GHz • Part-to-part skew: 85ps (typical) • Additive jitter, RMS: 0.03ps (typical) • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.465V to -2.375V • -40°C to 85°C ambient operating temperature QA nQA nQB0 2 11 nCLKA0 QB1 3 10 CLKA1 nQB1 4 9 1 CLKB 5 CLKB nCLKB QB0 nQB0 6 7 8 VEE 16 15 14 13 12 nCLKB CLKA1 nCLKA1 QB0 1 0 CLK_SELB CLKA0 nCLKA0 nQA QA CLK_SELA VCC PIN ASSIGNMENT CLK_SELA BLOCK DIAGRAM CLKA0 nCLKA1 ICS85354 CLK_SELB 16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View QB1 nQB1 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 85354AK www.icst.com/products/hiperclocks.html 1 REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER A TYPICAL APPLICATION FOR THE ICS85354 Used to connect a multi-rate PHY with the Tx/Rx pins of an SFP Module. Problem Addressed: How to mape the 2 Tx/Rx pairs of the multi-rate PHY to the single Tx/Rx pair on the SFP Module. MULTI-RATE PHY 100BaseFX 1000BaseX SFP MODULE ➣ Tx Rx ➣ ? ➣ Tx Rx ➣ ➣ Rx ➣ Tx MODE 1, 100BASEX CONNECTED TO SFP Bold red lines signal path. All lines are differential pairs, but drawn as single-ended to simplify the drawing. are active connections highlighting the CLK_SELA = 0 MULTI-RATE PHY Tx SFP MODULE CLKA0 0 CLKA1 Rx CLKB Tx 1 100BaseFX Rx QA QB0 QB1 CLK_SELB = 0 Tx ICS85354 1000BaseX Rx 85354AK www.icst.com/products/hiperclocks.html 2 REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER MODE 2, 1000BASEX CONNECTED TO SFP Bold red lines the signal path. All lines are differential pairs, but drawn as single-ended to simplify the drawing. are active connections highlighting CLK_SELA = 1 MULTI-RATE PHY Tx SFP MODULE CLKA0 0 QA Rx CLKA1 1 100BaseFX Rx CLKB QB0 Tx QB1 CLK_SELB = 1 Tx ICS85354 1000BaseX Rx 85354AK www.icst.com/products/hiperclocks.html 3 REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number Name Type 1, 2 QB0, nQB0 Output 3, 4 QB1, nQB1 Output 5 CLKB Input 6 nCLKB Input 7 CLK_SELB Input 8 VEE Power 9 nCLKA1 Input 10 CLKA1 Input 11 nCLKA0 Input 12 CLKA0 Input Description Differential output pair. LVPECL/ECL interface levels. Differential output pair. LVPECL/ECL interface levels. Pulldown Non-inver ting LVPECL/ECL differential clock input. Pullup/ Inver ting differential LVPECL clock input. VCC/2 default when left floating. Pulldown Clock select pin for QBx outputs. When HIGH, selects QB1, nQB1 Pulldown outputs. When LOW, selects QB0, nQB0 outputs. LVCMOS/LVTTL interface levels. Negative supply pin. Pullup/ Inver ting differential LVPECL clock input. VCC/2 default when left floating. Pulldown Pulldown Non-inver ting LVPECL differential clock input. Pullup/ Inver ting differential LVPECL clock input. VCC/2 default when left floating. Pulldown Pulldown Non-inver ting LVPECL differential clock input. Positive supply pin. Clock select pin for QA outputs. When HIGH, selects QA output. 14 CLK_SELA Input Pulldown When LOW, selects nQA output. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL/ECL interface levels. 15, 16 nQA, QA Output NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 13 Power VCC TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units RPULLDOWN Input Pulldown Resistor 37.5 KΩ RVCC/2 Pullup/Pulldown Resistors 37.5 KΩ TABLE 3A. CONTROL INPUT FUNCTION TABLE, BANK A Bank A Control Inputs Outputs CLK_SELA QA, nQA 0 Selects CLKA0, nCLKA0 1 Selects CLKA1, nCLKA1 TABLE 3B. CONTROL INPUT FUNCTION TABLE, BANK B Bank B Control Inputs Outputs CLK_SELB QB0, nQB0 QB1, nQB1 0 Follows CLKB input Low 1 Low Follows CLKB input 85354AK www.icst.com/products/hiperclocks.html 4 REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER ABSOLUTE MAXIMUM RATINGS Negative Supply Voltage, VEE 4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5 V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Supply Voltage, VCC Outputs, IO Continuous Current Surge Current to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character- 50mA 100mA istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 51.5°C/W (0 lfpm) (Junction-to-Ambient) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.465V, VEE = 0V OR VCC = 0V, VEE = -3.465V TO -2.375V Symbol Parameter Test Conditions VCC Positive Supply Voltage I EE Power Supply Current Minimum Typical Maximum Units 3.135 2.375 3.3 3.465 V 2.5 2.625 V 38 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.375V TO 3.465V Symbol Parameter VIH Input High Voltage CLK_SELx VIL Input Low Voltage IIH IIL 85354AK Test Conditions Minimum VCC = 2.5V or 3.3V CLK_SELx VCC = 2.5V or 3.3V Input High Current CLK_SELA, CLK_SELB VCC = VIN = 3.465V, Maximum Units 2 VCC + 0.3 V 0 0.8 V 150 µA Input Low Current CLK_SELA, CLK_SELB VCC = 3.465 2.625V, VIN = 0V VCC = VIN = 2.625V www.icst.com/products/hiperclocks.html 5 -150 Typical µA REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V, VEE = 0V Symbol VOH VOL VP P VCMR IIH IIL -40°C Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 CLKAx, Input CLKB High Current nCLKAx, nCLKB CLKAx, CLKB Input Low Current nCLKAx, nCLKB 25°C 85°C Units Min Typ Max Min Typ Max Min Typ Max VCC-1.125 VCC-1.025 VCC-0.92 VCC-1.075 VCC-1.005 VCC-0.93 VCC-1.005 VCC-0.97 VCC-0.935 V VCC-1.895 VCC-1.755 VCC-1.62 VCC-1.875 VCC-1.78 VCC-1.685 VCC-1.86 VCC-1.765 VCC-1.67 V 150 800 1200 150 800 1200 150 800 1200 mV VCC 1.2 VCC 1.2 VCC V 150 µA 1.2 150 150 -10 -10 -10 µA -150 -150 -150 µA Input and output parameters var y 1:1 with VCC. VCC can var y +0.165V to -0.925V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for CLKAx, nCLKAx and CLKB, nCLKB is VCC + 0.3V. TABLE 4D. ECL DC CHARACTERISTICS, VEE = -3.465V TO -2.375V, VCC = 0V Symbol -40°C Parameter 25°C Min Typ Max Min Typ 85°C Max Min Typ Max Units VOH Output High Voltage; NOTE 1 -1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.005 -0.97 -0.935 V VOL Output Low Voltage; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V VPP 150 800 1200 150 800 1200 150 800 1200 mV VCC VEE+1.2V VCC VEE+1.2V VCC V IIH Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input CLKAx, CLKB High Current nCLKAx, nCLKB 150 µA IIL Input Low Current VCMR CLKAx, CLKB VEE+1.2V 150 -10 150 -10 -10 -150 -150 -150 nCLKAx, nCLKB Input and output parameters vary 1:1 with VCC. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for CLKAx, nCLKAx and CLKB, nCLKB is VCC + 0.3V. 85354AK www.icst.com/products/hiperclocks.html 6 µA µA REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.465V, VEE = 0V OR VCC = 0V, VEE = -3.465V TO -2.375V Symbol Parameter fMAX Output Frequency t PD Propagation Delay; NOTE 1 330 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section MUX Isolation 85 ps 0.03 ps 55 dB Output Rise/Fall Time 170 ps tjit tR/tF Conditions 20% to 80% Minimum Typical Maximum Units 3 GHz All parameters are measured ≤ 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 85354AK www.icst.com/products/hiperclocks.html 7 REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER PARAMETER MEASUREMENT INFORMATION 2V VCC Qx VCC SCOPE nCLKA0, nCLKA1 nCLKB LVPECL V PP Cross Points V CMR CLKA0, CLKA1 CLKB nQx VEE V EE -0.375V to -1.465V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nCLKA0, nCLKA1 nCLKB nQx PART 1 Qx CLKA0, CLKA1 CLKB nQA, nQB0, nQB1 QA, QB0, QB1 nQy PART 2 Qy t sk(pp) PROPAGATION DELAY PART-TO-PART SKEW 80% tPD 80% VSW I N G Clock Outputs 20% 20% tR tF OUTPUT RISE/FALL TIME 85354AK www.icst.com/products/hiperclocks.html 8 REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR 3.3V LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 85354AK FIN 50Ω 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 9 REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm - 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE 85354AK www.icst.com/products/hiperclocks.html 10 REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 85354AK BY www.icst.com/products/hiperclocks.html 11 REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85354. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85354 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 38mA = 131.7mW Power (outputs)MAX = 27.83mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 27.83mW = 111.3mW Total Power_MAX (3.465, with all outputs switching) = 131.7mW + 111.3mW = 243mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.243W * 51.5°C/W = 97.5°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 16-PIN VFQFN, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 85354AK 51.5°C/W www.icst.com/products/hiperclocks.html 12 REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • – 1.005V OH_MAX OL_MAX CC_MAX CC_MAX ) = 1.005 -V For logic low, VOUT = V (V =V =V CC_MAX – 1.78V ) = 1.78V -V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V Pd_H = [(V – (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= OH_MAX CC_MAX CC_MAX OH_MAX CC_MAX OH_MAX CC_MAX OH_MAX L L [(2V - 1.005V)/50Ω] * 1.005V = 20mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.78V)/50Ω] * 1.78V = 7.83mW Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW 85354AK www.icst.com/products/hiperclocks.html 13 REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN θJA by Velocity (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 51.5°C/W TRANSISTOR COUNT The transistor count for ICS85354 is: 210 85354AK www.icst.com/products/hiperclocks.html 14 REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - K SUFFIX FOR ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER 16 LEAD VFQFN TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM 16 N A 0.80 1.0 A1 0 0.05 0.25 Reference A3 b 0.18 0.30 e 0.50 BASIC ND 4 NE 4 3.0 D D2 0.25 1.25 3.0 E E2 0.25 1.25 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 85354AK www.icst.com/products/hiperclocks.html 15 REV. B JUNE 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS85354AK 354A 16 Lead VFQFN 120 per Tube -40°C to 85°C ICS85354AKT 354A 16 Lead VFQFN on Tape and Reel 3500 -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85354AK www.icst.com/products/hiperclocks.html 16 REV. B JUNE 8, 2004