OPA827 OP A8 27 www.ti.com ..................................................................................................................................... SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 Low-Noise, High-Precision, JFET-Input OPERATIONAL AMPLIFIER FEATURES DESCRIPTION 1 • INPUT VOLTAGE NOISE DENSITY: 4nV/√Hz at 1kHz • INPUT VOLTAGE NOISE: 0.1Hz to 10Hz: 250nVPP • INPUT BIAS CURRENT: 15pA • INPUT OFFSET VOLTAGE: 150µV (max) • INPUT OFFSET DRIFT: 1.5µV/°C • GAIN BANDWIDTH: 22MHz • SLEW RATE: 28V/µs • QUIESCENT CURRENT: 4.8mA/Ch • WIDE SUPPLY RANGE: ±4V to ±18V • PACKAGES: SO-8 and MSOP-8(1) The OPA827 series of JFET operational amplifiers combine outstanding dc precision with excellent ac performance. These amplifiers offer low offset voltage (150µV, max), very low drift over temperature (1.5µV/°C, typ), low bias current (15pA, typ), and very low 0.1Hz to 10Hz noise (250nVPP, typ). The device operates over a wide supply voltage range, ±4V to ±18V on a low supply current (4.8mA/Ch, typ). 2 xx xx (1) Excellent ac characteristics, such as a 22MHz gain bandwidth product (GBW), a slew rate of 28V/µs, and precision dc characteristics make the OPA827 series well-suited for a wide range of applications including 16-bit to 18-bit mixed signal systems, transimpedance (I/V-conversion) amplifiers, filters, precision ±10V front ends, and professional audio applications. MSOP-8 (DGK) package is product preview. The OPA827 is available in both SO-8 and MSOP-8(1) surface-mount packages, and is specified from –40°C to +125°C. APPLICATIONS • • • • • • • • • ADC DRIVERS DAC OUTPUT BUFFERS TEST EQUIPMENT MEDICAL EQUIPMENT PLL FILTERS SEISMIC APPLICATIONS TRANSIMPEDANCE AMPLIFIERS INTEGRATORS ACTIVE FILTERS INPUT VOLTAGE NOISE DENSITY vs FREQUENCY 0.1Hz to 10Hz NOISE VS = ±18V 50nV/div Voltage Noise Density (nV/ÖHz) 100 10 1 0.1 1 10 100 1k 10k Time (1s/div) Frequency (Hz) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2008, Texas Instruments Incorporated OPA827 SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING Standard Grade OPA827AI SO-8 D OPA827A OPA827AI (2) MSOP-8 DGK NSP SO-8 D OPA827 MSOP-8 DGK NSP High Grade OPA827I (2) (1) (2) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Shaded cells indicate product preview devices. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). PARAMETER Supply Voltage VS = (V+) – (V–) VALUE UNIT 40 V Input Voltage (2) (V–) – 0.5 to (V+) + 0.5 V Input Current (2) ±10 mA Differential Input Voltage ±VS Output Short-Circuit (3) V Continuous Operating Temperature TA –55 to +150 °C Storage Temperature TA –65 to +150 °C Junction Temperature TJ +150 °C Human Body Model (HBM) 4000 V Charged Device Model (CDM) 1000 V ESD Ratings (1) (2) (3) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current-limited to 10mA or less. Short-circuit to VS/2 (ground in symmetrical dual-supply setups). Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 OPA827 www.ti.com ..................................................................................................................................... SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 ELECTRICAL CHARACTERISTICS: VS = ±4V to ±18V Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. STANDARD GRADE OPA827AI PARAMETER CONDITIONS MIN HIGH GRADE OPA827I (1) (2) TYP MAX 75 150 MIN TYP MAX UNIT 50 75 µV OFFSET VOLTAGE Input Offset Voltage Drift vs Power Supply VOS VS = ±15V, VCM = 0V dVOS/dT 1.5 PSRR 0.2 µV/°C 1.5 1 Over Temperature 0.2 3 1 µV/V 3 µV/V ±50 pA INPUT BIAS CURRENT Input Bias Current IB Over Temperature Input Offset Current ±15 ±50 ±15 –40°C to +85°C ±5 ±5 nA –40°C to +125°C ±50 ±50 nA ±50 pA IOS ±10 ±50 ±10 NOISE Input Voltage Noise: f = 0.1Hz to 10Hz en VS = ±18V, VCM = 0V 250 250 nVPP f = 1kHz en VS = ±18V, VCM = 0V f = 10kHz en VS = ±18V, VCM = 0V 4 4 nV/√Hz 3.8 3.8 nV/√Hz in VS = ±18V, VCM = 0V 2.2 2.2 fA/√Hz Input Voltage Noise Density: Input Current Noise Density: f = 1kHz INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio VCM CMRR Over Temperature (V–)+3 (V+)–3 (V–)+3 (V+)–3 V (V−)+3V ≤ VCM ≤ (V+)−3V, VS < 10V 104 114 114 120 dB (V−)+3V ≤ VCM ≤ (V+)−3V, VS ≥ 10V 114 126 120 126 dB (V−)+3V ≤ VCM ≤ (V+)−3V, VS < 10V 100 100 dB (V−)+3V ≤ VCM ≤ (V+)−3V, VS ≥ 10V 110 110 dB INPUT IMPEDANCE Differential 1013 9 1013 9 Ω pF Common-Mode 1013 9 1013 9 Ω pF OPEN-LOOP GAIN Open-Loop Voltage Gain AOL Over Temperature (V–)+3V ≤ VO ≤ (V+)–3V, RL = 1kΩ 120 (V–)+3V ≤ VO ≤ (V+)–3V, RL = 1kΩ 114 126 120 126 114 dB dB FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate Settling Time, ±0.01% GBW SR tS 0.00075% (16-bit) Overload Recovery Time Total Harmonic Distortion + Noise (1) (2) G = +1 THD+N 22 22 MHz G = –1 28 28 V/µs 10V Step, G = –1, CL = 100pF 550 550 ns 10V Step, G = –1, CL = 100pF 850 850 ns Gain = –10 150 150 ns G = +1, f = 1kHz 0.00004 0.00004 % VO = 3VRMS, RL = 600Ω –128 –128 dB Shaded cells indicate different specifications from standard grade version of device. High-grade specifications are preview only. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 3 OPA827 SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±4V to ±18V (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. STANDARD GRADE OPA827AI PARAMETER CONDITIONS MIN RL = 1kΩ, AOL > 120dB (V–)+3 RL = 1kΩ, AOL > 114dB (V–)+3 TYP HIGH GRADE OPA827I (1) (2) MAX MIN (V+)–3 (V–)+3 (V+)–3 (V–)+3 TYP MAX UNIT (V+)–3 V OUTPUT Voltage Output Swing Over Temperature Output Current Short-Circuit Current Capacitive Load Drive Open-Loop Output Impedance IOUT |VS – VOUT| < 3V 30 ISC ±65 CLOAD See Typical Characteristics ZO See Typical Characteristics (V+)–3 V 30 mA ±65 mA POWER SUPPLY Specified Voltage VS Quiescent Current (per amplifier) IQ ±4 ±18 IOUT = 0A 4.8 Over Temperature ±4 5.2 4.8 6 ±18 V 5.2 mA 6 mA TEMPERATURE RANGE Specified Range TA –40 +125 –40 +125 °C Operating Range TA –55 +150 –55 +150 °C Thermal Resistance θJA SO-8, MSOP-8 (3) (3) 150 150 °C/W MSOP-8 (DGK) package is product preview. PIN CONFIGURATION D, DGK(1) PACKAGES SO-8, MSOP-8(1) (TOP VIEW) NC (2) (2) 1 8 NC -In 2 7 V+ +In 3 6 Out V- 4 5 NC (2) (1) MSOP-8 (DGK) package is product preview. (2) NC denotes no internal connection. 4 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 OPA827 www.ti.com ..................................................................................................................................... SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS: VS = ±18V At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY INTEGRATED INPUT VOLTAGE NOISE vs BANDWIDTH 100 Input Voltage Noise (mV) Voltage Noise Density (nV/ÖHz) 100 10 10 VPP 1 VRMS 0.1 Noise Bandwidth: 0.1Hz to indicated frequency. 0.01 1 1 0.1 10 100 1k 10k 1 10 100 100k 1M 10M Figure 2. TOTAL HARMONIC DISTORTION + NOISE RATIO vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE RATIO vs AMPLITUDE -120 G = 11 G=1 -140 0.00001 10 100 1k 10k 20k Total Harmonic Distortion + Noise (%) 0.0001 -40 1 -100 VS = ±15V RL = 600W VOUT = 3VRMS VS = ±15V RL = 600W 0.1 1kHz Signal -60 -80 0.01 G = 11 -100 0.001 -120 0.0001 G=1 0.00001 0.01 Frequency (Hz) 0.1 1 10 Total Harmonic Distortion + Noise (dB) Total Harmonic Distortion + Noise (%) 10k Figure 1. Total Harmonic Distortion + Noise (dB) 0.001 1k Bandwidth (Hz) Frequency (Hz) -140 100 Output Voltage Amplitude (VRMS) Figure 3. Figure 4. 50nV/div 0.1Hz to 10Hz NOISE Time (1s/div) Figure 5. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 5 OPA827 SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±18V (continued) At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. OFFSET VOLTAGE PRODUCTION DISTRIBUTION OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION VS = ±15V -40°C to +125°C 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 135 150 105 120 75 90 60 30 45 0 15 -15 -30 -45 -60 -90 -75 -105 -120 -135 -150 Population Population VS = ±15V Offset Voltage (mV) 250 Figure 7. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE OFFSET VOLTAGE vs COMMON-MODE VOLTAGE 250 10 Typical Units Shown 150 150 100 100 50 50 0 -50 -100 -150 -150 -200 -200 -250 3.0 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 3 5.0 8 13 18 23 28 VCM (V) VCM (V) Figure 8. Figure 9. VOS WARMUP OFFSET VOLTAGE DRIFT vs TEMPERATURE 250 33 VS = ±15V 100 150 100 VOS (mV) VOS Shift (mV) 0 -50 -100 -250 50 Specified Temperature Range 0 -50 -100 -150 VS = ±15V 0 6 10 Typical Units Shown VS = 36V 100 VOS (mV) VOS (mV) Figure 6. VS = 8V 100 Offset Voltage Drift (mV/°C) 50 20 Typical Units Shown 100 150 200 250 300 -200 -250 -75 -50 -25 0 25 50 Time (s) Temperature (°C) Figure 10. Figure 11. Submit Documentation Feedback 75 100 125 150 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 OPA827 www.ti.com ..................................................................................................................................... SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS: VS = ±18V (continued) At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. INPUT BIAS CURRENT AND OFFSET CURRENT vs SUPPLY VOLTAGE INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE 0 20 IOS 15 Specified Common-Mode -5 +IB 10 IB (pA) IOS, IB (pA) Voltage Range 5 -10 -IB -15 Unit 1 0 Unit 3 -5 -10 Unit 2 -20 -15 -25 -20 4 6 8 10 12 14 16 -3 0 3 6 9 12 VCM (V) Figure 12. Figure 13. INPUT BIAS CURRENT vs TEMPERATURE NORMALIZED QUIESCENT CURRENT vs TIME 500 0.05 450 0 400 -0.05 350 -0.10 I Q Shift (mA) 250 +IB 200 -IB 150 15 18 10 Typical Units Shown -0.15 -0.20 -0.25 -0.30 100 50 -0.35 0 -0.40 -50 -75 -6 VS (±V) 300 IB (pA) -18 -15 -12 -9 18 -0.45 -50 -25 0 25 50 75 100 125 150 0 50 100 150 200 Temperature (°C) Time (s) Figure 14. Figure 15. QUIESCENT CURRENT vs TEMPERATURE QUIESCENT CURRENT vs SUPPLY VOLTAGE 6.0 250 300 33 38 5.00 4.95 VS = ±18V 5.5 4.85 5.0 IQ (mA) IQ (mA) 4.90 VS = ±5V 4.5 4.80 4.75 4.70 4.0 4.65 3.5 -75 4.60 -50 -25 0 25 50 75 100 125 150 8 Temperature (°C) 13 18 23 28 VS (V) Figure 16. Figure 17. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 7 OPA827 SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±18V (continued) At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. OUTPUT VOLTAGE SWING vs OUTPUT CURRENT 5 16 VS = ±5V 4 -40°C +150°C +25°C +125°C +85°C -40°C 0 -1 -2 Output Swing (V) 8 2 1 4 +150°C +125°C +85°C 0 -40°C +25°C -55°C -4 -8 -55°C -3 VS = ±18V 12 -55°C 3 Output Swing (V) OUTPUT VOLTAGE SWING vs OUTPUT CURRENT -12 -4 -5 -16 30 20 50 40 60 70 48 73 53 58 63 68 73 Output Current (mA) Output Current (mA) Figure 18. Figure 19. POWER-SUPPLY REJECTION RATIO vs FREQUENCY COMMON-MODE REJECTION RATIO vs FREQUENCY 180 140 Referred to Input 160 Positive VS ³ 10V 120 120 100 CMRR (dB) PSRR (dB) 140 Negative 80 100 80 60 60 40 40 20 20 0 0.1 1 10 100 1k 10k 100k 1M 0.1 10M 100M 1 10 100 Frequency (Hz) 1k 10k 100k 1M 10M 100M Frequency (Hz) Figure 20. Figure 21. POWER-SUPPLY REJECTION RATIO vs TEMPERATURE COMMON-MODE REJECTION RATIO vs TEMPERATURE 0.30 1.6 1.4 1.2 CMRR (mV/V) PSRR (mV/V) 0.25 0.20 0.15 1.0 0.8 0.6 0.4 0.2 0.0 0.10 -0.2 0.05 -75 8 -0.4 -50 -25 0 25 50 75 100 125 150 -75 -50 -25 0 25 50 Temperature (°C) Temperature (°C) Figure 22. Figure 23. Submit Documentation Feedback 75 100 125 150 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 OPA827 www.ti.com ..................................................................................................................................... SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS: VS = ±18V (continued) At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. OPEN-LOOP GAIN AND PHASE vs FREQUENCY CLOSED-LOOP GAIN vs FREQUENCY 140 50 0 30 Phase -90 60 40 Phase (°) 80 Gain (dB) -45 100 Gain (dB) G = +101 40 120 10 G = +1 0 -10 -135 20 G = +11 20 -20 0 Gain -20 10 1 100 1k 10k 100k 1M 10M -180 100M -30 100 1k 10k 10M Figure 25. OPEN-LOOP GAIN vs TEMPERATURE OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY 100M 1000 Open-Loop Output Impedance (ZO) RL = 1kW 1.0 AOL (mV/V) 1M Figure 24. 1.2 0.8 0.6 0.4 0.2 -75 100k Frequency (Hz) Frequency (Hz) -50 -25 0 25 50 75 100 125 100 10 1 100 150 1k Temperature (°C) 10k 100k 1M 10M 100M Frequency (Hz) Figure 26. Figure 27. SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD NO PHASE REVERSAL 70 100mV Output Step G = +1 Output 50 40 G = -1 30 5V/div Overshoot (%) 60 +18V OPA827 20 Output -18V 37VPP Sine Wave (±18.5V) 10 0 0 100 200 300 400 500 600 700 800 900 1000 0.5ms/div Capacitive Load (pF) Figure 28. Figure 29. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 9 OPA827 SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±18V (continued) At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. POSITIVE OVERLOAD RECOVERY NEGATIVE OVERLOAD RECOVERY G = -10 G = -10 VIN 5V/div 5V/div VOUT 0V 10kW 0V 10kW 1kW VIN 1kW OPA827 VOUT OPA827 VIN VOUT VIN VOUT Time (0.5ms/div) Time (0.5ms/div) Figure 30. Figure 31. SMALL-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE +18V OPA827 -18V C1 5.6pF 20mV/div 20mV/div G = +1 RL = 1kW CL = 100pF R1 1kW +18V OPA827 RL CL CL G = -1 CL = 100pF -18V Time (0.1ms/div) Figure 32. Figure 33. LARGE-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE 2V/div 2V/div Time (0.1ms/div) G = +1 RL = 1kW CL = 100pF 10 R2 1kW G = -1 CL = 100pF Time (0.5ms/div) Time (0.5ms/div) Figure 34. Figure 35. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 OPA827 www.ti.com ..................................................................................................................................... SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS: VS = ±18V (continued) At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. 0.010 1.0 0.010 0.8 0.008 0.8 0.008 0.6 0.006 0.6 0.4 0.004 0.002 0 0 -0.002 -0.2 (±1/2 LSB = ±0.00075%) -0.4 -0.004 -0.6 -0.006 -0.8 -1.0 100 200 300 400 500 600 Time (ns) 0.006 0.4 0.004 16-Bit Settling 0.2 0.002 0 0 -0.2 -0.002 (±1/2 LSB = ±0.00075%) -0.4 -0.004 -0.6 -0.006 -0.008 -0.8 -0.008 -0.010 700 800 900 1000 -1.0 0 100 200 300 400 500 600 Time (ns) -0.010 700 800 900 1000 Figure 36. Figure 37. LARGE-SIGNAL NEGATIVE SETTLING TIME (10VPP, CL = 100pF) LARGE-SIGNAL NEGATIVE SETTLING TIME (10VPP, CL = 10pF) 0.010 0.8 0.008 0.6 0.006 0.6 0.006 0.4 0.004 16-Bit Settling 0.2 0.002 0 0 -0.002 -0.2 (±1/2 LSB = ±0.00075%) -0.4 -0.004 -0.6 -0.006 -0.8 -1.0 0 100 200 300 400 500 600 Time (ns) D From Final Value (mV) 1.0 0.008 0.004 16-Bit Settling 0.2 0.002 0 0 -0.002 -0.2 (±1/2 LSB = ±0.00075%) -0.4 -0.004 -0.6 -0.006 -0.008 -0.8 -0.008 -0.010 700 800 900 1000 -1.0 0 100 200 300 400 500 600 Time (ns) Figure 38. D From Final Value (%) 0.010 0.8 D From Final Value (%) 1.0 0.4 D From Final Value (%) 16-Bit Settling 0.2 D From Final Value (mV) 1.0 0 D From Final Value (mV) LARGE-SIGNAL POSITIVE SETTLING TIME (10VPP, CL = 10pF) D From Final Value (%) D From Final Value (mV) LARGE-SIGNAL POSITIVE SETTLING TIME (10VPP, CL = 100pF) -0.010 700 800 900 1000 Figure 39. SHORT-CIRCUIT CURRENT vs TEMPERATURE 80 Sourcing 60 ISC (mA) 40 20 0 -20 -40 Sinking -60 -80 -75 -25 25 75 125 175 Temperature (°C) Figure 40. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 11 OPA827 SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com APPLICATION INFORMATION OPERATING VOLTAGE The OPA827 series of op amps can be used with single or dual supplies from an operating range of VS = +8V (±4V) and up to VS = +36V (±18V). This device does not require symmetrical supplies; it only requires a minimum supply voltage of 8V. Supply voltages higher than +40V (±20V) can permanently damage the device; see the Absolute Maximum Ratings table. Key parameters are specified over the operating temperature range, TA = –40°C to +125°C. Key parameters that vary over the supply voltage or temperature range are shown in the Typical Characteristics section of this data sheet. NOISE PERFORMANCE Figure 41 shows the total circuit noise for varying source impedances with the operational amplifier in a unity-gain configuration (with no feedback resistor network and therefore no additional noise contributions). The OPA827 (GBW = 22MHz) and OPA211 (GBW = 80MHz) are both shown in this example with total circuit noise calculated. The op amp itself contributes both a voltage noise component and a current noise component. The voltage noise is commonly modeled as a time-varying component of the offset voltage. The current noise is modeled as the time-varying component of the input bias current and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest noise op amp for a given application depends on the source impedance. For low source impedance, current noise is negligible, and voltage noise generally dominates. The OPA827 family has both low voltage noise and lower current noise because of the FET input of the op amp. Very low current noise allows for excellent noise performance with source impedances greater than 10kΩ. The OPA211 has lower voltage noise and higher current noise. The low voltage noise makes the OPA211 a better choice for low source impedances (less than 2kΩ). For high source impedance, current noise may dominate, and makes the OPA827 series amplifier the better choice. 12 The equation in Figure 41 shows the calculation of the total circuit noise, with these parameters: • en = voltage noise • in = current noise • RS = source impedance • k = Boltzmann's constant = 1.38 × 10–23 J/K • T = temperature in kelvins For more details on calculating noise, see the Basic Noise Calculations section. 10k Votlage Noise Spectral Density, EO The OPA827 is a unity-gain stable, precision operational amplifier with very low noise, input bias current, and input offset voltage. Applications with noisy or high impedance power supplies require decoupling capacitors placed close to the device pins. In most cases, 0.1µF capacitors are adequate. EO 1k OPA211 RS 100 OPA827 Resistor Noise 10 2 2 2 EO = en + (in RS) + 4kTRS 1 100 1k 10k 100k 1M Source Resistance, RS (W) Figure 41. Noise Performance of the OPA827 and OPA211 in Unity-Gain Buffer Configuration BASIC NOISE CALCULATIONS Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the circuit is the root-sum-square combination of all noise components. The resistive portion of the source impedance produces thermal noise proportional to the square root of the resistance. This function is plotted in Figure 41. The source impedance is usually fixed; consequently, select the op amp and the feedback resistors to minimize the respective contributions to the total noise. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 OPA827 www.ti.com ..................................................................................................................................... SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 Figure 42 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit configurations with gain, the feedback network resistors also contribute noise. The current noise of the op amp reacts with the feedback resistors to create additional noise components. The feedback resistor values can generally be chosen to make these noise sources negligible. Note that low impedance feedback resistors will load the output of the amplifier. The equations for total noise are shown for both configurations. A) Noise in Noninverting Gain Configuration Noise at the output: R2 2 2 2 R1 EO = 1 + R2 R1 2 2 2 2 2 2 en + e1 + e2 + (inR2) + eS + (inRS) EO R2 Where eS = Ö4kTRS ´ 1 + 1+ R2 R1 = thermal noise of RS R1 RS e1 = Ö4kTR1 ´ VS R2 R1 = thermal noise of R1 e2 = Ö4kTR2 = thermal noise of R2 B) Noise in Inverting Gain Configuration Noise at the output: R2 2 2 EO = 1 + R1 R2 R 1 + RS EO RS Where eS = Ö4kTRS ´ 2 2 2 2 en + e1 + e2 + (inR2) + eS R2 R 1 + RS 2 = thermal noise of RS VS e1 = Ö4kTR1 ´ R2 R 1 + RS = thermal noise of R1 e2 = Ö4kTR2 = thermal noise of R2 For the OPA827 series op amps at 1kHz, en = 4nV/ÖHz and in = 2.2fA/ÖHz. Figure 42. Noise Calculation in Gain Configurations Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 13 OPA827 SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com TOTAL HARMONIC DISTORTION MEASUREMENTS The OPA827 series op amps have excellent distortion characteristics. THD + Noise is below 0.0001% (G = +1, VO = 3VRMS) throughout the audio frequency range, 20Hz to 20kHz, with a 600Ω load (see Figure 3). The distortion produced by the OPA827 series is below the measurement limit of many commercially available testers. However, a special test circuit (illustrated in Figure 43) can be used to extend the measurement capabilities. Op amp distortion can be considered an internal error source that can be referred to the input. Figure 43 shows a circuit that causes the op amp distortion to be 101 times greater than that distortion normally produced by the op amp. The addition of R3 to the otherwise standard noninverting amplifier configuration alters the feedback factor or noise gain R1 of the circuit. The closed-loop gain is unchanged, but the feedback available for error correction is reduced by a factor of 101, thus extending the resolution by 101. Note that the input signal and load applied to the op amp are the same as with conventional feedback without R3. The value of R3 should be kept small to minimize its effect on the distortion measurements. The validity of this technique can be verified by duplicating measurements at high gain and/or high frequency where the distortion is within the measurement capability of the test equipment. Measurements for this data sheet were made with an Audio Precision System Two distortion/noise analyzer, which greatly simplifies such repetitive measurements. This measurement technique, however, can be performed with manual distortion measurement instruments. R2 SIGNAL DISTORTION GAIN GAIN R3 OPA827 VO = 3VRMS R Signal Gain = 1+ 2 R1 Distortion Gain = 1+ R2 R1 II R3 Generator Output R1 R2 R3 1 101 ¥ 1kW 10W 11 101 100W 1kW 11W Analyzer Input Audio Precision System Two(1) with PC Controller RL 600W NOTE: (1) Measurement BW = 80kHz. Figure 43. Distortion Test Circuit 14 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 OPA827 www.ti.com ..................................................................................................................................... SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 Capacitive load drive depends on the gain and overshoot requirements of the application. Capacitive loads limit the bandwidth of the amplifier. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads (see Figure 28). PHASE-REVERSAL PROTECTION The OPA827 family has internal phase-reversal protection. Many FET-input op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input circuitry of the OPA827 prevents phase reversal with excessive common-mode voltage; instead, the output limits into the appropriate rail (see Figure 29). 50mV/div VOUT Figure 44. OPA827 Driving 2.2µF Ceramic Capacitor 100mV/div In Figure 45, the OPA827 is driving a 2.2µF tantalum capacitor. A relatively small ESR that is internal to the capacitor additionally improves phase margin and provides an output waveform with no ringing and minimal overshoot. Figure 45 shows a stable system that can be used in almost any application. VIN 20ms/div 50mV/div The combination of gain bandwidth product (GBW) and near constant open loop output impedance (ZO) over frequency gives the OPA827 the ability to drive large capacitive loads. Figure 44 shows the OPA827 connected in a buffer configuration (G = +1) while driving a 2.2µF ceramic capacitor (with an ESR value of approximately 0Ω). The small overshoot and fast settling time are results of good phase margin. This feature provides superior performance compared to the competition. Figure 44 and Figure 45 were taken without any resistive load in parallel to shorten the ringing time. 100mV/div CAPACITIVE LOAD AND STABILITY VIN VOUT 20ms/div Figure 45. OPA827 Driving 2.2µF Tantalum Capacitor Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 15 OPA827 SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com TRANSIMPEDANCE AMPLIFIER Bandwidth (f–3dB) calculated by Equation 2: The gain bandwidth, low voltage noise, and current noise of the OPA827 series make them ideal wide bandwidth transimpedance amplifiers in a photo-conductive application. High transimpedance gains with feedback resistors greater than 100kΩ benefit from the low input current noise (2.2fA/Hz) of the JFET input. Low voltage noise is important because photodiode capacitance causes the effective noise gain in the circuit to increase at high frequencies. Total input capacitance of the circuit limits the overall gain bandwidth of the amplifier and is addressed below. Figure 46 shows a photodiode transimpedance application. f-3dB = UGBW Hz 2pRF(CTOT) These equations result in maximum transimpedance bandwidth. For additional information, refer to Application Bulletin SBOA055, Compensate Transimpedance Amplifiers Intuitively, available for download at www.ti.com. (1) CF < 1pF RF 1MW Key Transimpedance Points • The total input capacitance (CTOT) consists of the photodiode junction capacitance, and both the common-mode and differential input capacitance of the operational amplifier. • The desired transimpedance gain, VOUT = IDRF. • The Unity Gain Bandwidth Product (UGBW) (22MHz for the OPA827). CSTRAY OPA827 ID CTOT VOUT = IDRF -VS NOTES: (1) CF is optional to prevent gain peaking. (2) CSTRAY is the stray capacitance of RF (typically, 2pF for a surface-mount resistor). To ensure 45° phase margin, the minimal amount of feedback capacitance can be calculated using Equation 1: 1 CF 1+ 1+ (8pCTOTRFUGBW 4pRFUGBW )( (2) +VS With these three variables set, the feedback capacitor value (CF) can be calculated to ensure stability. CSTRAY is the parasitic capacitance of the PCB and passive components, which is approximately 0.5pF. ( (2) Figure 46. Transimpedance Amplifier ) (1) V+ IN- IN+ OUT V- Figure 47. Equivalent Schematic (Single Channel) 16 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 OPA827 www.ti.com ..................................................................................................................................... SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 PHASE-LOCK LOOP The OPA827 is well-suited for phase-lock loop (PLL) applications because of the low voltage offset, low noise, and wide gain bandwidth. Figure 48 illustrates an example of the OPA827 in this application. The first amplifier (OPA827) provides the loop low-pass, active filter function, while the second amplifier (OPA211) serves as a scaling amplifier. This second stage amplifies the dc error voltage to the appropriate level before it is applied to the voltage-controlled oscillator (VCO). Operational amplifiers used in PLL applications are often required to have low voltage offset. As with other dc levels generated in the loop, a voltage offset applied to the VCO is interpreted as a phase error. An operational amplifier with inherently low voltage offset helps reduce this source of error. Also, any noise produced by the operational amplifiers modulates the voltage applied to the VCO and limits the spectral purity of the oscillator output. The VCO generates noise-related, random phase variations of its own, but this characteristic becomes worse when the input voltage source noise is included. This noise appears as random sideband energy that can limit system performance. The very low flicker noise (1/f) and current noise (In) of the OPA827 help to minimize the operational amplifier contribution to the phase noise. Offset Voltage Generator (Frequency Adjustment) Scaling Amplifier Low-Pass Filter Current Source Input Signal Phase Dector Output Signal OPA827 OPA211 Current Source VCO Level Adjustment and Buffer Amplifier Divider 1/N Figure 48. PLL Application Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 17 OPA827 SBOS376E – NOVEMBER 2006 – REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com OPA827 USED AS AN I/V CONVERTER The OPA827 series of operation amplifiers have low current noise and offset voltage that make these devices a great choice for an I/V converter. The DAC8811 is a single channel, current output, 16-bit digital-to-analog converter (DAC). The IOUT terminal of the DAC is held at a virtual GND potential by the use of the OPA827 as an external I/V converter op amp. The R-2R ladder is connected to an external reference input (VREF) that determines the DAC full-scale current. The external reference voltage can vary in a range of –15V to +15V, thus providing bipolar IOUT current operation. By using the OPA827 as an external I/V converter in conjunction with the internal DAC8811 RFB resistor, output voltage ranges of –VREF to +VREF can be generated. When using an external I/V converter and the DAC8811 RFB resistor, the DAC output voltage is given by Equation 3. -VREF ´ CODE VOUT = 65536 (3) The DAC output impedance as seen looking into the IOUT terminal changes versus code. The low offset voltage of the OPA827 minimizes the error propagated from the DAC. For a current-to-voltage design (see Figure 49), the DAC8811 IOUT pin and the inverting node of the OPA827 should be as short as possible and adhere to good PCB layout design. For each code change on the output of the DAC, there is a step function. If the parasitic capacitance is excessive at the inverting node, then gain peaking is possible. For circuit stability, two compensation capacitors, C1 and C2(4pF to 20pF typical) can be added to the design. Some applications require full four-quadrant multiplying capabilities or a bipolar output swing. As shown in Figure 49, the OPA827 is added as a summing amp and has a gain of 2x that widens the output span to 20V. A four-quadrant multiplying circuit is implemented by using a 10V offset of the reference voltage to bias the OPA827. NOTE: CODE is the digital input into the DAC. 10kW 10kW C2 5kW VDD RFB +10V VREF OPA827 C1 VOUT DAC8811 IOUT OPA827 -10V £ VOUT £ +10V GND Figure 49. I/V Converter 18 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): OPA827 PACKAGE OPTION ADDENDUM www.ti.com 27-Oct-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty OPA827AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-UNLIM OPA827AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-UNLIM OPA827AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA827AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Oct-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device OPA827AIDR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.4 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Oct-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA827AIDR SOIC D 8 2500 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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