TI TMS27C040

TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
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description
The TMS27C040 devices are 524 288 by 8-bit
(4 194 304-bit), ultraviolet (UV) light erasable,
electrically programmable read-only memories
(EPROMs).
TMS27C040
J PACKAGE
( TOP VIEW )
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VCC
A18
A17
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
TMS27PC040
FM PACKAGE
( TOP VIEW )
4
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
The TMS27PC040 devices are 524 288 by 8-bit
(4 194 304-bit), one-time programmable (OTP)
electrically programmable read-only memories
(PROMs).
These devices are fabricated using CMOS
technology for high speed and simple interface
with MOS and bipolar circuits. All inputs ( including
program data inputs) can be driven by the Series
74 TTL circuits. Each output can drive one Series
74 TTL circuit without external resistors.
1
21
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ1
DQ2
14 15 16 17 18 19 20
GND
DQ3
DQ4
DQ5
DQ6
D
D
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Organization . . . 524 288 by 8 Bits
Single 5-V Power Supply
Industry Standard 32-Pin Dual In-Line
Package and 32-Lead Plastic Leaded Chip
Carrier
All Inputs / Outputs Fully TTL Compatible
Static Operation (No Clocks, No Refresh)
Max Access / Min Cycle Time
VCC ± 10%
’27C/ PC040-10
100 ns
’27C/ PC040-12
120 ns
’27C/ PC040-15
150 ns
8-Bit Output For Use in
Microprocessor-Based Systems
Power-Saving CMOS Technology
3-State Output Buffers
400-mV Assured DC Noise Immunity With
Standard TTL Loads
Latchup Immunity of 250 mA on All Input
and Output Pins
No Pullup Resistors Required
Low Power Dissipation (VCC = 5.5 V)
– Active . . . 275 mW Worst Case
– Standby . . . 0.55 mW Worst Cas E
(CMOS-Input Levels)
Temperature Range Options
A12
A15
A16
VPP
VCC
A18
A17
D
D
D
PIN NOMENCLATURE
A0 – A18
DQ0 – DQ7
E
G
GND
VCC
VPP
Address Inputs
Inputs (programming) / Outputs
Chip Enable
Output Enable
Ground
5-V Supply
13-V Power Supply†
† Only in program mode.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
description (continued)
The data outputs are 3-state for connecting multiple devices to a common bus
The TMS27C040 is offered in a 600-mil ceramic dual-in-line package (J suffix). The TMS27C040 is offered with
two choices of temperature ranges of 0°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). (See Table 1.)
The TMS27PC040 is offered in a 32-lead plastic leaded chip carrier package ( FM suffix). The TMS27PC040
is offered with two choices of temperature ranges of 0°C to 70°C ( JL suffix) and –40°C to 85°C (JE suffix).
Table 1. Temperature Range Suffixes
SUFFIX FOR OPERATING
FREE-AIR TEMPERATURE
RANGES
FUNCTION
0°C to 70°C
– 40°C to 85°C
TMS27C040-XXX
JL
JE
TMS27PC040-XXX
FML
FME
These EPROMs and PROMS operate from a single 5-V supply ( in the read mode), and they are ideal for use
in microprocessor-based systems. One other (13 V) supply is needed for programming. All programming
signals are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are
TTL level except for VPP during programming (13 V), and VH (12 V) on A9 for the signature mode.
Table 2. Operation Modes
MODE
Read
Output Disable
Standby
Programming
Program Inhibit
Verify
Signature Mode
FUNCTION †
E
G
VIL
VIL
VIH
VIL
VIH
VIH
VIL
VCC
VCC
A9
A0
DQ0 – DQ7
VIL
VIH
X
VPP
X
X
X
Data Out
VCC
VCC
VCC
VCC
X
X
Hi-Z
X
X
Hi-Z
VIH
VIH
VPP
VPP
VCC
VCC
X
X
Data In
X
X
Hi-Z
VIL
VPP
VCC
X
X
Data Out
VH ‡
VIL
VIH
MFG Code 97
VIL
VCC
VCC
Device Code 50
† X can be VIL or VIH
‡ VH = 12 V ± 0.5 V
read/ output disable
When the outputs of two or more TMS27C040s or TMS27PC040s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C040 and TMS27PC040 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. The input / output layout approach controls latchup
without compromising performance or packing density.
2
POST OFFICE BOX 1443
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TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
power down
Active ICC supply current can be reduced from 50 mA to 1 mA by applying a high TTL input on E and to
100 µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure ( TMS27C040)
Before programming, the TMS27C040 EPROM is erased by exposing the chip through the transparent lid to
a high intensity UV-light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity ×
exposure time) is 15-W⋅s / cm2 . A typical 12-mW / cm2, filterless UV lamp erases the device in 21 minutes. The
lamp must be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state.
Normal ambient light contains the correct wavelength for erasure; therefore, when using the TMS27C040, the
window must be covered with an opaque label. After erasure (all bits in logic high state), logic lows are
programmed into the desired locations. A programmed low can be erased only by UV light.
initializing ( TMS27PC040)
The OTP TMS27PC040 PROM is provided with all bits in logic high state, then logic lows are programmed into
the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The TMS27C040 and TMS27PC040 are programmed by using the SNAP! Pulse programming algorithm. The
programming sequence is shown in the SNAP! Pulse programming flow chart shown in Figure 1.
The initial setup is VPP = 13 V, VCC = 6.5 V, E = VIH, and G = VIH. Once the initial location is selected, the data
is presented in parallel (eight bits) on pins DQ0 through DQ7. Once addresses and data are stable, the
programming mode is achieved when E is pulsed low (VIL) with a pulse duration of tw(PGM). Every location is
programmed only once before going to interactive mode.
In the interactive mode, the word is verified at VPP = 13 V, VCC = 6.5 V, E = VIH, and G = VIL. If the correct data
is not read, the programming is performed by pulling E low with a pulse duration of tw(PGM). This sequence of
verification and programming is performed up to a maximum of 10 times. When the device is fully programmed,
all bytes are verified with VCC = VPP = 5 V ± 10%.
program inhibit
Programming can be inhibited by maintaining high level inputs on the E and G pins.
program verify
Programmed bits can be verified with VPP = 13 V when G = VIL, and E = VIH.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other
addresses must be held low. The signature code for the TMS27C040 is 9750. A0 low selects the manufacturer’s
code 97 (Hex), and A0 high selects the device code 50 (Hex), as shown in Table 3.
Table 3. Signature Mode
IDENTIFIER†
MANUFACTURER CODE
DEVICE CODE
PINS
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
HEX
VIL
VIH
1
0
0
1
0
1
1
1
97
0
1
0
1
0
0
0
0
50
† E = G = VIL, A1-A8 = VIL, A9 = VH, A10-A18 = VIL, VPP = VCC.
POST OFFICE BOX 1443
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3
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
Start
Address = First Location
VCC = 6.5 V ± 0.25 V, VPP = 13 V ± 0.25 V
Program
Mode
Program One Pulse = tw = 100 µs
Last
Address?
Increment Address
No
Yes
Address = First Location
X=0
Program One Pulse = tw = 100 µs
No
Increment
Address
Verify
One Byte
Fail
X=X+1
X = 10?
Interactive
Mode
Pass
No
Last
Address?
Yes
Yes
VCC = VPP = 5 V ± 0.5 V
Compare
All Bytes
to Original
Data
Device Failed
Fail
Final
Verification
Pass
Device Passed
Figure 1. SNAP! Pulse Programming Flow Chart
4
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TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
logic symbol†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
E
G
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
31
22
24
0
EPROM 524 288 × 8
A
0
524 287
A
A
A
A
A
A
A
A
13
14
15
17
18
19
20
21
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
18
[PWR DWN]
&
EN
† This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers are for the J package.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
Supply voltage range, VPP (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13 V
Output voltage range, with respect to VSS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
Operating free-air temperature range (’27C040-_ _JL and ’27PC040-_ _FML) . . . . . . . . . . . . . . 0°C to 70°C
Operating free-air temperature range (’27C040-_ _JE and ’27PC040 _ _ FME) . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 125°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
5
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
recommended operating conditions
VCC
Read mode (see Note 2)
Supply voltage
SNAP! Pulse programming algorithm
Read mode
VPP
Supply voltage
VIH
High level dc input voltage
High-level
VIL
Low level dc input voltage
Low-level
TA
MIN
NOM
MAX
4.5
5
5.5
V
6.25
6.5
6.75
V
V
13
VCC + 0.6
13.25
VCC + 0.5
VCC + 0.5
V
VCC – 0.6
12.75
SNAP! Pulse programming algorithm
TTL
2
CMOS
VCC – 0.2
– 0.5
TTL
CMOS
V
V
0.8
V
– 0.5
0.2
V
0
70
°C
’27C040-_ _JL
’27PC040-_ _FML
Operating free-air temperature
UNIT
TA
Operating free-air temperature
’27C040-_ _JE
– 40
85
°C
NOTE 2: VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted
into or removed from the board when VPP or VCC is applied.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VOH
High level dc output voltage
High-level
IOH = – 400 µA
IOH = – 20 µA
VOL
Low level dc output voltage
Low-level
IOL = 2.1 mA
IOL = 20 µA
0.4
±1
µA
±1
µA
10
µA
50
mA
Input current (leakage)
Output current (leakage)
VI = 0 V to 5.5 V
VO = 0 V to VCC
IPP1
IPP2
VPP supply current
VPP supply current (during program pulse)
VPP = VCC = 5.5 V
VPP = 12.75 V
ICC2
TTL-Input level
VCC supply current (standby)
CMOS-Input level
VCC = 5.5 V,
VCC = 5.5 V,
V
0.1
II
IO
ICC1
2.4
VCC – 0.1
E = VIH
E = VCC
E = VIL,
VCC = 5.5 V
tcycle = minimum cycle time,
outputs open†
VCC supply current (active)
V
1
mA
100
µA
50
mA
† Minimum cycle time = maximum access time.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz‡
PARAMETER
Ci
TEST CONDITIONS
Input capacitance
Co
Output capacitance
‡ All typical values are at TA = 25°C and nominal voltages.
§ Capacitance measurements are made on sample basis only.
6
POST OFFICE BOX 1443
VI = 0 V
VO = 0 V
• HOUSTON, TEXAS 77251–1443
MIN
TYP§
MAX
4
8
pF
8
12
pF
UNIT
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
switching characteristics over recommended ranges of operating conditions (see Notes 3
and 4)
PARAMETER
TEST CONDITIONS
’27C040-10
’27 PC040-10
MIN
ta(A)
ta(E)
Access time from address
ten(G)
Output enable time from G
tdis
Output disable time from G or E, whichever
occurs first
tv(A)
Output data valid time after change of
address, E, or G, whichever occurs first†
Access time from chip enable
CL = 100 pF,
F,
1 Series 74
TTL load,
Input tr ≤ 20 ns,
Input tf ≤ 20 ns
MAX
’27C040-12
’27 PC040-12
MIN
MAX
’27C040-15
’27 PC040-15
MIN
UNIT
MAX
100
120
150
ns
100
120
150
ns
50
50
50
ns
50
ns
0
50
0
0
50
0
0
0
ns
† Value calculated from 0.5-V delta to measured output level.
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (See Figure 2)
4. Common test conditions apply for tdis except during programming.
switching characteristics for programming: VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25°C
(see Note 3)
PARAMETER
tdis(G)
ten(G)
Output disable time from G
MIN
MAX
UNIT
0
100
ns
150
ns
Output enable time from G
NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (See Figure 2)
timing requirements for programming
SNAP! Pulse programming algorithm
MIN
NOM
MAX
UNIT
95
100
105
µs
tw(PGM)
tsu(A)
Pulse duration, program
Setup time, address
2
µs
tsu(E)
tsu(G)
Setup time, E
2
µs
Setup time, G
2
µs
tsu(D)
tsu(VPP)
Setup time, data
2
µs
Setup time, VPP
2
µs
tsu(VCC)
th(A)
Setup time, VCC
2
µs
Hold time, address
0
µs
th(D)
Hold time, data
2
µs
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7
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
2.08 V
RL = 800 Ω
Output
Under Test
CL = 100 pF
(see Note A)
2.4 V
2V
2V
0.8 V
0.4 V
0.8 V
NOTES: A. CL includes probe and fixture capacitance.
B. AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at 2 V for logic high and
0.8 V for logic low for both inputs and outputs.
Figure 2. AC Testing Output Load Circuit and Waveform
VIH
A0 – A18
Addresses Valid
VIL
ta(A)
VIH
E
VIL
ta(E)
VIH
G
VIL
tdis
ten(G)
tv(A)
VIH
DQ0 – DQ7
Output Valid
Hi-Z
Hi-Z
VIL
Figure 3. Read-Cycle Timing
8
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• HOUSTON, TEXAS 77251–1443
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
Verify
Program
VIH
A0 – A18
Address Stable
VIL
tsu(A)
DQ0 – DQ7
Data-In Stable
tsu(D)
th(A)
VIH / VOH
Data-Out
Stable
Hi-Z
ten(G)
VIL / VOL
tdis(G)
VPP†
VPP
VCC
tsu(VPP)
VCC†
VCC
tsu(E)
VCC
th(D)
tsu(VCC)
VIH
E
tsu(G)
tw(PGM)
VIL
VIH
G
VIL
† 13-V VPP and 6.5-V VCC for SNAP! Pulse programming
Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
9
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
FM (R-PQCC-J32)
PLASTIC J-LEADED CHIP CARRIER
Seating Plane
0.004 (0,10)
0.140 (3,56)
0.132 (3,35)
0.495 (12,57)
4
0.485 (12,32)
0.129 (3,28)
0.123 (3,12)
0.453 (11,51)
0.447 (11,35)
0.049 (1,24)
0.043 (1,09)
1
0.008 (0,20) NOM
30
29
5
0.020 (0,51)
0.015 (0,38)
0.595 (15,11)
0.585 (14,86)
0.553 (14,05)
0.547 (13,89)
0.030 (0,76)
TYP
21
13
14
20
0.050 (1,27)
4040201-4 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-016
10
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• HOUSTON, TEXAS 77251–1443
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
J (R-CDIP-T**)
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
24 PIN SHOWN
B
13
24
C
12
1
Lens Protrusion
0.010 (0,25) MAX
0.065 (1,65)
0.045 (1,14)
0.090 (2,29)
0.060 (1,53)
0.018 (0,46) MIN
0.175 (4,45)
0.140 (3,56)
A
Seating Plane
0°– 10°
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
A
B
C
28
24
PINS**
NARR
DIM
0.012 (0,30)
0.008 (0,20)
NARR
WIDE
32
WIDE
NARR
40
WIDE
NARR
WIDE
MAX
0.624(15,85) 0.624(15,85)
0.624(15,85) 0.624(15,85)
0.624(15,85) 0.624(15,85)
0.624(15,85) 0.624(15,85)
MIN
0.590(14,99) 0.590(14,99)
0.590(14,99) 0.590(14,99)
0.590(14,99) 0.590(14,99)
0.590(14,99) 0.590(14,99)
MAX
1.265(32,13) 1.265(32,13)
1.465(37,21) 1.465(37,21)
1.668(42,37) 1.668(42,37)
2.068(52,53) 2.068(52,53)
MIN
1.235(31,37) 1.235(31,37)
1.435(36,45) 1.435(36,45)
1.632(41,45) 1.632(41,45)
2.032(51,61) 2.032(51,61)
MAX
0.541(13,74) 0.598(15,19)
0.541(13,74) 0.598(15,19)
0.541(13,74) 0.598(15,19)
0.541(13,74) 0.598(15,19)
MIN
0.514(13,06) 0.571(14,50)
0.514(13,06) 0.571(14,50)
0.514(13,06) 0.571(14,50)
0.514(13,06) 0.571(14,50)
4040084 / B 04/95
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
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