TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 D D D D D D D Organization – TM4EP64xxN-xx . . . 4 194 304 × 64 Bits – TM4EP72xxN-xx . . . 4 194 304 × 72 Bits Single 3.3-V Power Supply (±10% Tolerance) JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket TM4EP64xxN-xx — Utilizes Sixteen 16M-Bit High-Speed (4M × 4-Bit) Dynamic RAMs TM4EP72xxN-xx — Utilizes Eighteen 16M-Bit High-Speed (4M × 4-Bit) Dynamic RAMs High-Speed, Low-Noise LVTTL Interface High-Reliability Plastic 24/26-Lead 300-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package (DJ Suffix) and 24/26-Lead 300-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGA Suffix) D D D D D D D Long Refresh Periods: – TM4EPxxCxN: 64 ms (4 096 Cycles) – TM4EPxxBxN: 32 ms (2 048 Cycles) 3-State Output Extended-Data-Out (EDO) Operation With CAS-Before-RAS (CBR), RAS-Only, and Hidden Refresh Serial Presence-Detect (SPD) Using EEPROM Ambient Temperature Range 0°C to 70°C Gold-Plated Contacts Performance Ranges ’4EPxxxxN-50 ’4EPxxxxN-60 ’4EPxxxxN-70 ACCESS TIME tRAC (MAX) 50 ns 60 ns 70 ns ACCESS ACCESS EDO TIME TIME CYCLE tCAC tAA tHPC (MAX) (MAX) (MIN) 13 ns 25 ns 20 ns 15 ns 30 ns 25 ns 18 ns 35 ns 30 ns description The TM4EP64xxN is a 32M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of sixteen TMS42x409A, 4 194 304 × 4-bit EDO dynamic random-access memories (DRAMs), each in a 300-mil, 26-pin plastic thin small-outline package (TSOP) (DGA suffix) mounted on a substrate with decoupling capacitors. See the TMS42x409A data sheet (literature number SMKS893). The TM4EP64xJN is available with an SOJ package (DJ suffix). The TM4EP72xxN is a 32M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS42x409A, 4 194 304 × 4-bit EDO DRAMs, each in a 300-mil, 26-pin plastic TSOP (DGA suffix) mounted on a substrate with decoupling capacitors. See the TMS42x409A data sheet (literature number SMKS893). The TM4EP72xJN is available with an SOJ packaage (DJ suffix). operation The TM4EP64xxN operates as 16 TMS42x409As that are connected as shown in the TM4EP64xxN functional block diagram. The TM4EP72xxN operates as 18 TMS42x409As that are connected as shown in the TM4EP72xxN functional block diagram. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 DUAL-IN-LINE MEMORY MODULE ( TOP VIEW ) TM4EP64xxN ( SIDE VIEW ) TM4EP72xxN ( SIDE VIEW ) PIN NOMENCLATURE – TM4EPxxBxN A[0:10] A[0:10] DQ[0:63] CB[0:7] CAS[0:7] RAS0 and RAS2 WE0 and WE2 OE0 and OE2 SA[0:2] 1 10 11 SDA SCL NC VDD VSS Row-Address Inputs Column-Address Inputs Data In / Data Out Check Bit In / Check Bit Out Column-Address Strobe Row-Address Strobe Write Enable Output Enable Serial Presence Detect (SPD) Device Add Input SPD Address / Data SPD Clock No Connect 3.3-V Supply Ground PIN NOMENCLATURE – TM4EPxxCxN A[0:11] A[0:9] DQ[0:63] CB[0:7] CAS[0:7] RAS0 and RAS2 WE0 and WE2 OE0 and OE2 SA[0:2] 40 41 SDA SCL NC VDD VSS 84 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Row-Address Inputs Column-Address Inputs Data In / Data Out Check Bit In / Check Bit Out Column-Address Strobe Row-Address Strobe Write Enable Output Enable Serial Presence Detect (SPD) Device Add Input SPD Address / Data SPD Clock No Connect 3.3-V Supply Ground TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 Pin Assignments PIN PIN NAME NO. PIN NAME NO. PIN NAME NO. NAME NO. 1 VSS DQ0 43 86 VSS DQ32 127 44 VSS OE2 85 2 128 VSS NC 3 DQ1 45 RAS2 87 DQ33 129 NC 4 DQ2 46 CAS2 88 DQ34 130 CAS6 5 DQ3 47 CAS3 89 DQ35 131 CAS7 6 VDD DQ4 48 WE2 90 NC 49 91 133 8 DQ5 50 VDD NC VDD DQ36 132 7 92 DQ37 134 VDD NC 9 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 VSS DQ9 54 97 VSS DQ41 138 55 VSS DQ16 96 13 139 VSS DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 DQ45 143 60 102 VDD DQ52 61 NC 103 VDD DQ46 144 19 VDD DQ14 VDD DQ20 101 18 145 NC 20 DQ15 62 NC 104 DQ47 146 NC 21 CB0 63 NC 105 CB4 147 NC 22 CB1 64 CB5 148 65 107 VSS DQ53 66 DQ22 108 VSS NC 149 24 VSS NC VSS DQ21 106 23 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 68 111 VDD NC 152 69 VSS DQ24 110 27 VDD WE0 153 VSS DQ56 28 CAS0 70 DQ25 112 CAS4 154 DQ57 29 CAS1 71 DQ26 113 CAS5 155 DQ58 30 RAS0 72 DQ27 114 NC 156 DQ59 31 OE0 73 115 NC 157 32 74 116 158 75 DQ29 117 VSS A1 VDD DQ60 33 VSS A0 VDD DQ28 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 120 A7 162 37 A8 79 VSS NC 121 A9 163 VSS NC 38 A10 80 NC 122 A11 164 NC 39 NC 81 NC 123 NC 165 SA0 40 VDD NC 82 SDA 124 SA1 83 SCL 125 VDD NC 166 41 167 SA2 42 NC 84 VDD 126 NC 168 VDD POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 dual-in-line memory module and components The dual-in-line memory module and components include: D D D PC substrate: 1,27 " 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper functional block diagram for the TM4EP64xxN RAS0 WE0 OE0 CAS0 DQ[0:3] RAS2 WE2 OE2 CAS CAS1 DQ[8:11] CAS2 DQ[16:19] CAS3 DQ[24:27] W W W OE W CAS DQ[36:39] RAS W W W DQ[44:47] RAS OE DQ[48:51] CAS DQ[52:55] RAS OE CAS DQ[56:59] OE CAS DQ[60:63] W RAS W RAS W RAS W RAS UB6 DQ[0:3] RAS RAS UB5 DQ[0:3] CAS7 W UB4 DQ[0:3] RAS RAS UB3 OE CAS W UB2 DQ[0:3] CAS6 U7 DQ[0:3] OE CAS RAS UB1 DQ[0:3] RAS U6 OE CAS DQ[40:43] U5 OE OE DQ[0:3] CAS5 W UB0 DQ[0:3] RAS U4 OE OE CAS DQ[32:35] U3 DQ[0:3] CAS DQ[28:31] OE DQ[0:3] CAS CAS4 U2 DQ[0:3] CAS DQ[20:23] OE DQ[0:3] CAS RAS U1 DQ[0:3] CAS DQ[12:15] OE DQ[0:3] CAS W U0 DQ[0:3] CAS DQ[4:7] OE OE DQ[0:3] W RAS UB7 TM4EP64xxN: A[0:11] A[0:11]† : U[0:7], UB[0:7] VDD SPD EEPROM SCL SDA A0 A1 A2 SA0 SA1 SA2 † A11 is not used in TM4EP64BxN 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 VSS U[0:7], UB[0:7] Two 0.1 µF (minimum) per DRAM U[0:7], UB[0:7] TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 functional block diagram for the TM4EP72xxN RAS0 WE0 OE0 CAS0 DQ[0:3] RAS2 WE2 OE2 CAS CAS1 DQ[8:11] CAS1 CB[0:3] CAS2 DQ[16:19] CAS CAS3 DQ[24:27] DQ[32:35] W W OE W CAS DQ[36:39] RAS W DQ[40:43] W DQ[44:47] RAS CB[4:7] RAS W OE W DQ[48:51] OE CAS DQ[52:55] RAS OE CAS DQ[56:59] OE CAS DQ[60:63] W RAS W RAS W RAS W RAS UB5 W RAS UB6 DQ[0:3] RAS RAS UB4 DQ[0:3] CAS7 W UB8 DQ[0:3] RAS U7 DQ[0:3] OE CAS RAS UB3 DQ[0:3] CAS6 U6 DQ[0:3] OE CAS W UB2 DQ[0:3] CAS5 U5 OE OE CAS RAS UB1 DQ[0:3] RAS U4 OE OE CAS W UB0 DQ[0:3] CAS5 U8 OE OE DQ[0:3] RAS U3 DQ[0:3] CAS DQ[28:31] OE DQ[0:3] CAS W CAS CAS4 U2 DQ[0:3] CAS DQ[20:23] OE DQ[0:3] CAS RAS U1 DQ[0:3] CAS DQ[12:15] OE DQ[0:3] CAS W U0 DQ[0:3] CAS DQ[4:7] OE OE DQ[0:3] W RAS UB7 TM4EP72xxN: A[0:11] A[0:11]†: U[0:8], UB[0:8] VDD SPD EEPROM SCL SDA A0 A1 A2 SA0 SA1 SA2 VSS U[0:8], UB[0:8] Two 0.1 µF (minimum) per DRAM U[0:8], UB[0:8] † A11 is not used in TM4EP72BxN POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 absolute maximum ratings over ambient temperature range (unless otherwise noted)† Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM4EP64xxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W TM4EP72xxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX 3 3.3 3.6 UNIT VDD VSS Supply voltage VIH VIL-SPD High-level input voltage 2 High-level input voltage for the SPD device 2 VDD + 0.3 5.5 VIL Low-level input voltage – 0.3 0.8 V TA Ambient temperature 0 70 °C 6 Supply voltage 0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 V V V V TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) TM4EP64BxN PARAMETER TEST CONDITIONS† ’4EP64BxN-50 MIN ’4EP64BxN-60 MAX MIN MAX ’4EP64BxN-70 MIN MAX UNIT High-level output voltage IOH = – 2 mA LVTTL VOH IOH = – 100 µA LVCMOS Low-level output voltage IOL = 2 mA LVTTL 0.4 0.4 0.4 VOL IOL = 100 µA LVCMOS 0.2 0.2 0.2 II Input current (leakage) VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 µA IO Output current (leakage) VDD = 3.6 V, CASx high VO = 0 V to VDD, ± 20 ± 20 ± 20 µA ICC1‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 1 920 1 600 1 440 mA VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 32 32 32 mA VIH = VDD – 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 16 16 16 mA ICC2 Average standby current 2.4 2.4 2.4 V VDD– 0.2 VDD – 0.2 VDD – 0.2 V ICC3‡§ Average refresh current (RASx-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) 1 920 1 600 1 440 mA ICC4‡¶ Average EDO current VDD = 3.6 V, RASx low, 1 760 1 440 1 280 mA tHPC = MIN, CASx cycling † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL ¶ Measured with a maximum of one address change during each EDO cycle, tHPC POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM4EP72BxN PARAMETER ’4EP72BxN-50 TEST CONDITIONS† MIN ’4EP72BxN-60 MAX MIN MAX ’4EP72BxN-70 MIN MAX UNIT High-level output voltage IOH = – 2 mA LVTTL VOH IOH = – 100 µA LVCMOS Low-level output voltage IOL = 2 mA LVTTL 0.4 0.4 0.4 VOL IOL = 100 µA LVCMOS 0.2 0.2 0.2 II Input current (leakage) VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 µA IO Output current (leakage) VDD = 3.6 V, CASx high VO = 0 V to VDD, ± 20 ± 20 ± 20 µA ICC1‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 2 160 1 800 1 620 mA VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 36 36 36 mA VIH = VDD – 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 18 18 18 mA ICC2 Average standby current 2.4 2.4 2.4 V VDD – 0.2 VDD – 0.2 VDD – 0.2 V ICC3‡§ Average refresh current (RAS-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) 2 160 1 800 1 620 mA ICC4‡¶ Average EDO current VDD = 3.6 V, RASx low, 1 980 1 620 1 440 mA tHPC = MIN, CASx cycling † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL ¶ Measured with a maximum of one address change during each EDO cycle, tHPC 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM4EP64CxN PARAMETER TEST CONDITIONS† ’4EP64CxN-50 MIN ’4EP64CxN-60 MAX MIN MAX ’4EP64CxN-70 MIN MAX UNIT High-level output voltage IOH = – 2 mA LVTTL VOH IOH = – 100 µA LVCMOS Low-level output voltage IOL = 2 mA LVTTL 0.4 0.4 0.4 VOL IOL = 100 µA LVCMOS 0.2 0.2 0.2 II Input current (leakage) VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 µA IO Output current (leakage) VDD = 3.6 V, CASx high VO = 0 V to VDD, ± 20 ± 20 ± 20 µA ICC1‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 1 440 1 120 960 mA VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 32 32 32 mA VIH = VDD – 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 16 16 16 mA ICC2 Average standby current 2.4 2.4 2.4 V VDD – 0.2 VDD – 0.2 VDD – 0.2 V ICC3‡§ Average refresh current (RASx-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) 1 440 1 120 960 mA ICC4‡¶ Average EDO current VDD = 3.6 V, RASx low, 1 600 1 440 1 280 mA tHPC = MIN, CASx cycling † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL ¶ Measured with a maximum of one address change during each EDO cycle, tHPC POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM4EP72CxN PARAMETER ’4EP72CxN-50 TEST CONDITIONS† MIN ’4EP72CxN-60 MAX MIN MAX ’4EP72CxN-70 MIN MAX UNIT High-level output voltage IOH = – 2 mA LVTTL VOH IOH = – 100 µA LVCMOS Low-level output voltage IOL = 2 mA LVTTL 0.4 0.4 0.4 VOL IOL = 100 µA LVCMOS 0.2 0.2 0.2 II Input current (leakage) VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 µA IO Output current (leakage) VDD = 3.6 V, CASx high VO = 0 V to VDD, ± 20 ± 20 ± 20 µA ICC1‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 1 620 1 260 1 080 mA VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 36 36 36 mA VIH = VDD – 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 18 18 18 mA ICC2 Average standby current 2.4 2.4 2.4 V VDD – 0.2 VDD – 0.2 VDD– 0.2 V ICC3‡§ Average refresh current (RASx-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) 1 620 1 260 1 080 mA ICC4‡¶ Average EDO current VDD = 3.6 V, RASx low, 1 800 1 620 1 440 mA tHPC = MIN, CASx cycling † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL ¶ Measured with a maximum of one address change during each EDO cycle, tHPC 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2) PARAMETER ’4EP64xxN ’4EP72xxN MIN MIN MAX MAX UNIT Ci(A) Input capacitance, A0 – A11 82 92 pF Ci(OE) Input capacitance, OEx 58 65 pF Ci(CAS) Input capacitance, CASx 16 23 pF Ci(RAS) Input capacitance, RASx 58 65 pF Ci(W) Input capacitance, WEx 58 65 pF Co Output capacitance 8 8 pF Ci/o(SDA) Input/output capacitance, SDA input 9 9 pF Ci(SPD) 7 7 pF Input capacitance, SA0, SA1, SA2, SCL inputs NOTE 2: VDD = NOM supply voltage ± 10%, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3) ’4EP64xxN-50 ’4EP72xxN-50 PARAMETER MIN MAX ’4EP64xxN-60 ’4EP72xxN-60 MIN MAX ’4EP64xxN-70 ’4EP72xxN-70 MIN UNIT MAX tAA tCAC Access time from column address (see Note 4) 25 30 35 ns Access time from CASx (see Note 4) 13 15 18 ns tCPA tRAC Access time from CASx precharge (see Note 4) 28 35 40 ns Access time from RASx (see Note 4) 50 60 70 ns tOEA tCLZ Access time from OEx (see Note 4) 13 15 18 ns Delay time, CASx to output in low impedance 0 tREZ tCEZ Output buffer turn-off delay from RASx (see Note 5) 3 13 3 15 3 18 ns Output buffer turn-off delay from CASx (see Note 5) 3 13 3 15 3 18 ns tOEZ tWEZ Output buffer turn-off delay from OEx (see Note 5) 3 13 3 15 3 18 ns Output buffer turn-off delay from WEx (see Note 5) 3 13 3 15 3 18 ns 0 0 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 5. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the outputs are no longer driven. Data-in should not be driven until one of the applicable maximum values is satisfied. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 EDO timing requirements (see Note 3) ’4EP64xxN-50 ’4EP72xxN-50 MIN MAX ’4EP64xxN-60 ’4EP72xxN-60 MIN MAX ’4EP64xxN-70 ’4EP72xxN-70 MIN UNIT MAX tHPC tPRWC Cycle time, EDO page mode, read-write 20 25 30 ns Cycle time, EDO read-write 57 68 78 ns tCSH tCHO Delay time, RASx active to CASx precharge 40 48 58 ns Hold time, OEx from CASx 7 10 10 ns tDOH tCAS Hold time, output from CASx 5 5 5 Pulse duration, CASx active 8 tWPE tOCH Pulse duration, WEx active (output disable only) 7 7 7 ns Setup time, OEx before CASx 8 10 10 ns tCP tOEP Pulse duration, CASx precharge 8 10 10 ns Precharge time, OEx 5 5 5 ns 10 000 NOTE 3: With ac parameters, it is assumed that tT = 2 ns. 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 10 10 000 12 ns 10 000 ns TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 ac timing requirements (see Note 3) ’4EP64xxN-50 ’4EP72xxN-50 MIN MAX ’4EP64xxN-60 ’4EP72xxN-60 MIN MAX ’4EP64xxN-70 ’4EP72xxN-70 MIN UNIT MAX tRC tRWC Cycle time, random read or write tRASP tRAS Pulse duration, RASx active, fast-page mode (see Note 6) 50 100 000 60 100 000 70 100 000 ns Pulse duration, RASx active, non-page mode (see Note 6) 50 60 70 ns tRP tWP Pulse duration, RASx precharge 30 40 50 ns Pulse duration, write command 8 10 10 ns tASC tASR Setup time, column address 0 0 0 ns Setup time, row address 0 0 0 ns tDS tRCS Setup time, data in (see Note 7) 0 0 0 ns Setup time, read command 0 0 0 ns tCWL tRWL Setup time, write command before CASx precharge 8 10 12 ns Setup time, write command before RASx precharge 8 10 12 ns Setup time, write command before CASx active (early-write only) 0 0 0 ns tWCS Cycle time, read-write 84 104 124 ns 111 135 160 ns 10 000 10 000 10 000 tWRP tWTS Setup time, WEx high before RASx low (CBR refresh only) 10 10 10 ns Setup time, WEx low before RASx low (test mode only) 10 10 10 ns tCSR tCAH Setup time, CASx referenced to RASx ( CBR refresh only ) 5 5 5 ns Hold time, column address 8 10 12 ns tDH tRAH Hold time, data in (see Note 7) 8 10 12 ns Hold time, row address 8 10 10 ns tRCH tRRH Hold time, read command referenced to CASx (see Note 8) 0 0 0 ns Hold time, read command referenced to RASx (see Note 8) 0 0 0 ns tWCH tROH Hold time, write command during CASx active ( early-write only ) 8 10 12 ns Hold time, RASx referenced to OEx 10 10 10 ns tWRH tWTH Hold time, WEx high after RASx low (CBR refresh) 10 10 10 ns Hold time, WEx low after RASx low (test mode only) 10 10 10 ns tCHR tOEH Hold time, CASx referenced to RASx ( CBR refresh only ) 10 10 10 ns Hold time, OEx command 13 15 18 ns tCHS tRHCP Hold time, CASx referenced to RASx ( self-refresh only) – 50 – 50 – 50 ns Hold time, RASx active from CASx precharge 28 35 40 ns tAWD tCPW Delay time, column address to write command ( read-write only ) 42 49 57 ns Delay time, WEx low after CASx precharge (read-write only) 45 54 62 ns tCRP tCWD Delay time, CASx precharge to RASx 5 5 5 ns Delay time, CASx to write command ( read-write only ) 30 34 40 ns tOED tRAD Delay time, OEx to data in 13 15 18 Delay time, RASx to column address (see Note 9) 10 tRAL tCAL Delay time, column address to RASx precharge 25 30 35 ns Delay time, column address to CASx precharge 18 20 25 ns NOTES: 3. 6. 7. 8. 9. 25 12 30 12 ns 35 ns With ac parameters, it is assumed that tT = 2 ns. In a read-write cycle, tRWD and tRWL must be observed. Referenced to the later of CASx or WEx in write operations Either tRCH or tRRH must be satisfied for a read cycle. The maximum value is specified only to ensure access time. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 ac timing requirements (see Note 3) (continued) ’4EP64xxN-50 ’4EP72xxN-50 ’4EP64xxN-60 ’4EP72xxN-60 ’4EP64xxN-70 ’4EP72xxN-70 MIN MAX MIN MAX MIN MAX 12 37 14 45 14 52 UNIT tRCD tRPC Delay time, RASx to CASx ( see Note 9) Delay time, RASx precharge to CASx 0 0 0 ns tRSH tRWD Delay time, CASx active to RASx precharge 8 10 12 ns Delay time, RASx to write command (read-write only) 67 79 92 ns tTAA tTCPA Access time from address (test mode) 30 35 40 ns Access time from column precharge (test mode) 35 40 45 ns tTRAC tREF Access time from RASx (test mode) 55 Refresh time interval tT Transition time NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 9. The maximum value is specified only to ensure access time. 14 65 32 POST OFFICE BOX 1443 2 • HOUSTON, TEXAS 77251–1443 30 75 32 2 30 2 ns ns 32 ms 30 ns TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 serial presence detect The serial presence detect (SPD) is contained in a 256-byte Serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing parameters (see Table 1 through Table 4). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. SPD contents for the TM4EPxxxxN devices are listed in the following tables: Table 1–TM4EP64BxN Table 3–TM4EP72BxN Table 2–TM4EP64CxN Table 4–TM4EP72CxN Table 1. Serial-Presence-Detect Data for the TM4EP64BxN ’4EP64BxN-50 ’4EP64BxN-60 ’4EP64BxN-70 BYTE NO. FUNCTION DESCRIBED ITEM DATA ITEM DATA ITEM DATA 0 Defines number of bytes written into serial memory during module manufacturing 128 bytes 80h 128 bytes 80h 128 bytes 80h 1 Total number of bytes of SPD memory device 256 bytes 08h 256 bytes 08h 256 bytes 08h 2 Fundamental memory type (FPM, EDO, SDRAM) EDO 02h EDO 02h EDO 02h 3 Number of row addresses on this assembly 10 0Ah 10 0Ah 10 0Ah 4 Number of column addresses on this assembly 10 0Ah 10 0Ah 10 0Ah 5 Number of module banks on this assembly 1 bank 01h 1 bank 01h 1 bank 01h 6 Data width of this assembly 64 bits 40h 64 bits 40h 64 bits 40h 7 Data width continuation 8 Voltage interface standard of this assembly 00h 00h 00h LVTTL 01h LVTTL 01h LVTTL 01h tRAC = 50 ns tRAC = 13 ns 32h tRAC = 60 ns tRAC = 15 ns 3Ch 0Fh tRAC = 70 ns tRAC = 18 ns 46h 0Dh Non-parity 00h Non-parity 00h Non-parity 00h 15.6 µs 00h 15.6 µs 00h 15.6 µs 00h 9 RASx access time of module 10 CASx access time of module 11 DIMM configuration type (non-parity, parity, ECC) 12 Refresh rate / type 13 DRAM width, primary DRAM x4 04h x4 04h x4 04h 14 Error-checking SDRAM data width N/A 00h N/A 00h N/A 00h 62 SPD revision Rev. 1 01h Rev. 1 01h Rev. 1 01h 63 Checksum for bytes 0 – 62 36 24h 48 30h 61 3Dh 64–71 Manufacturer’s JEDEC code per JEP-106E 97h 9700...00h 97h 9700...00h 97h 9700...00h 72 Manufacturing location† TBD TBD TBD TBD TBD TBD 91 Manufacturer’s part number† Die revision code† TBD TBD TBD 92 PCB revision code† TBD TBD TBD 73–90 ID POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 12h 15 TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 serial presence detect (continued) Table 1. Serial-Presence-Detect Data for the TM4EP64BxN (Continued) BYTE NO. FUNCTION DESCRIBED ’4EP64BxN-50 ITEM DATA ’4EP64BxN-60 ITEM DATA ’4EP64BxN-70 ITEM 93–94 Manufacturing date† TBD TBD TBD 95–98 Assembly serial number† TBD TBD TBD 99–125 TBD TBD TBD 126–127 Manufacturer-specific data† Vendor-specific data† TBD TBD TBD 128–166 System-integrator-specific data‡ TBD TBD TBD 167–255 Open † TBD indicates that values are determined at manufacturing time and are module-dependent. ‡ These TBD values are determined and programmed by the customer (optional). 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DATA TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 serial presence detect (continued) Table 2. Serial-Presence-Detect Data for the TM4EP64CxN BYTE NO. FUNCTION DESCRIBED 0 ’4EP64CxN-50 ’4EP64CxN-60 ’4EP64CxN-70 ITEM DATA ITEM DATA ITEM DATA Defines number of bytes written into serial memory during module manufacturing 128 bytes 80h 128 bytes 80h 128 bytes 80h 1 Total number of bytes of SPD memory device 256 08h 256 08h 256 08h 2 Fundamental memory type (FPM, EDO, SDRAM) EDO 02h EDO 02h EDO 02h 3 Number of row addresses on this assembly 11 0Bh 11 0Bh 11 0Bh 4 Number of column addresses on this assembly 9 09h 9 09h 9 09h 5 Number of module banks on this assembly 1 bank 01h 1 bank 01h 1 bank 01h 6 Data width of this assembly 64 bits 40h 64 bits 40h 64 bits 40h 7 Data width continuation 8 Voltage interface standard of this assembly 9 RASx access time of module 10 CASx access time of module 11 DIMM configuration type (non-parity, parity, ECC) 12 Refresh rate / type 13 DRAM width, primary DRAM 14 Error-checking SDRAM data width 62 SPD revision 63 Checksum for bytes 0 – 62 64–71 Manufacturer’s JEDEC code per JEP-106E 72 Manufacturing location† TBD TBD TBD Manufacturer’s part number† Die revision code† TBD TBD TBD TBD TBD TBD TBD TBD TBD 93–94 PCB revision code† Manufacturing date† TBD TBD TBD 95–98 Assembly serial number† TBD TBD TBD 99–125 Manufacturer-specific data† Vendor-specific data† TBD TBD TBD TBD TBD TBD TBD TBD TBD 73–90 91 92 126–127 128–166 System-integrator-specific data‡ 00h ID 00h 00h LVTTL 01h LVTTL 01h LVTTL 01h tRAC = 50 ns tRAC = 13 ns 32h 3Ch 0Fh tRAC = 70 ns tRAC = 18 ns 46h 0Dh tRAC = 60 ns tRAC = 15 ns Non-parity 00h Non-parity 00h Non-parity 00h 15.6 µs 00h 15.6 µs 00h 15.6 µs 00h x4 04h x4 04h x4 04h N/A 00h N/A 00h N/A 00h Rev. 1 01h Rev. 1 01h Rev. 1 01h 36 24h 48 30h 61 3Dh 97h 9700...00h 97h 9700...00h 97h 9700...00h 12h 167–255 Open † TBD indicates that values are determined at manufacturing time and are module-dependent. ‡ These TBD values are determined and programmed by the customer (optional). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 serial presence detection (continued) Table 3. Serial-Presence-Detect Data for the TM4EP72BxN BYTE NO. FUNCTION DESCRIBED 0 ’4EP72BxN-50 ’4EP72BxN-60 ’4EP72BxN-70 ITEM DATA ITEM DATA ITEM DATA Defines number of bytes written into serial memory during module manufacturing 128 bytes 80h 128 bytes 80h 128 bytes 80h 1 Total number of bytes of SPD memory device 256 bytes 08h 256 bytes 08h 256 bytes 08h 2 Fundamental memory type (FPM, EDO, SDRAM) EDO 02h EDO 02h EDO 02h 3 Number of row addresses on this assembly 10 0Ah 10 0Ah 10 0Ah 4 Number of column addresses on this assembly 10 0Ah 10 0Ah 10 0Ah 5 Number of module banks on this assembly 1 bank 01h 1 bank 01h 1 bank 01h 6 Data width of this assembly 72 bits 48h 72 bits 48h 72 bits 48h 7 Data width continuation 8 Voltage interface standard of this assembly 9 RASx access time of module 10 CASx access time of module 11 DIMM configuration type (non-parity, parity, ECC) 12 Refresh rate / type 13 DRAM width, primary DRAM 14 Error-checking SDRAM data width 62 SPD revision 63 Checksum for bytes 0 – 62 64–71 Manufacturer’s JEDEC code per JEP-106E 72 Manufacturing location† TBD TBD TBD Manufacturer’s part number† Die revision code† TBD TBD TBD TBD TBD TBD TBD TBD TBD 93–94 PCB revision code† Manufacturing date† TBD TBD TBD 95–98 Assembly serial number† TBD TBD TBD 99–125 Manufacturer-specific data† Vendor-specific data† TBD TBD TBD TBD TBD TBD TBD TBD TBD 73–90 91 92 126–127 128–166 System-integrator-specific data‡ 00h ID 00h LVTTL 01h LVTTL 01h LVTTL 01h tRAC = 50 ns tRAC = 13 ns 32h 3Ch 0Fh tRAC = 70 ns tRAC = 18 ns 46h 0Dh tRAC = 60 ns tRAC = 15 ns ECC 02h ECC 02h ECC 02h 15.6 µs 00h 15.6 µs 00h 15.6 µs 00h x4 04h x4 04h x4 04h x4 04h x4 04h x4 04h Rev. 1 01h Rev. 1 01h Rev. 1 01h 50 32h 62 3Eh 75 4Bh 97h 9700...00h 97h 9700...00h 97h 9700...00h 167–255 Open † TBD indicates that values are determined at manufacturing time and are module-dependent. ‡ These TBD values are determined and programmed by the customer (optional). 18 00h POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 12h TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 serial presence detect (continued) Table 4. Serial-Presence-Detect Data for the TM4EP72CxN BYTE NO. FUNCTION DESCRIBED 0 ’4EP72CxN-50 ’4EP72CxN-60 ’4EP72CxN-70 ITEM DATA ITEM DATA ITEM DATA Defines number of bytes written into serial memory during module manufacturing 128 bytes 80h 128 bytes 80h 128 bytes 80h 1 Total number of bytes of SPD memory device 256 bytes 08h 256 bytes 08h 256 bytes 08h 2 Fundamental memory type (FPM, EDO, SDRAM) EDO 02h EDO 02h EDO 02h 3 Number of row addresses on this assembly 11 0Bh 11 0Bh 11 0Bh 4 Number of column addresses on this assembly 9 09h 9 09h 10 09h 5 Number of module banks on this assembly 1 01h 1 01h 2 01h 6 Data width of this assembly 72 bits 48h 72 bits 48h 72 bits 48h 7 Data width continuation 8 Voltage interface standard of this assembly 9 RASx access time of module 10 CASx access time of module 11 DIMM configuration type (non-parity, parity, ECC) 12 Refresh rate / type 13 DRAM width, primary DRAM 14 Error-checking SDRAM data width 62 SPD revision 63 Checksum for bytes 0 – 62 64–71 Manufacturer’s JEDEC code per JEP-106E 72 Manufacturing location† TBD TBD TBD Manufacturer’s part number† Die revision code† TBD TBD TBD TBD TBD TBD TBD TBD TBD 93–94 PCB revision code† Manufacturing date† TBD TBD TBD 95–98 Assembly serial number† TBD TBD TBD 99–125 Manufacturer-specific data† Vendor-specific data† TBD TBD TBD TBD TBD TBD TBD TBD TBD 73–90 91 92 126–127 128–166 System-integrator-specific data‡ 00h ID 00h 00h LVTTL 01h LVTTL 01h LVTTL 01h tRAC = 50 ns tRAC = 13 ns 32h 3Ch 0Fh tRAC = 70 ns tRAC = 18 ns 46h 0Dh tRAC = 60 ns tRAC = 15 ns ECC 02h ECC 02h ECC 02h 15.6 µs 00h 15.6 µs 00h 15.6 µs 00h x4 04h x4 04h x4 04h x4 04h x4 04h x4 04h Rev. 1 01h Rev. 1 01h Rev. 1 01h 50 32h 62 3Eh 75 4Bh 97h 9700...00h 97h 9700...00h 97h 9700...00h 12h 167–255 Open † TBD indicates that values are determined at manufacturing time and are module-dependent. ‡ These TBD values are determined and programmed by the customer (optional). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 device symbolization (TM4EP64BPN illustrated) TM4EP64BPN -SS Unbuffered Key Position 3.3-V Voltage Key Position YY MM T -SS = = = = Year Code Month Code Assembly Site Code Speed Code NOTE A: Location of symbolization may vary. 20 YYMMT POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 MECHANICAL DATA BR (R-PDIM-N168) DUAL IN-LINE MEMORY MODULE 5.255 (133,48) 5.245 (133,22) (Note D) Notch 0.157 (4,00) x 0.122 (3,10) Deep 2 Places 0.039 (1,00) TYP 0.125 (3,18) 0.054 (1,37) 0.046 (1,17) Notch 0.079 (2,00) x 0.122 (3,10) Deep 2 Places 0.050 (1,27) 0.014 (0,35) MAX 0.118 (3,00) TYP 0.125 (3,18) 0.700 (17,78) TYP 0.118 (3,00) DIA 2 Places 1.005 (25,53) 0.995 (25,27) 0.106 (2,70) MAX 0.157 (4,00) MAX (For Double Sided DIMM Only) 4088180/A 07/97 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MO-161 Dimension includes de-panelization variations; applies between notch and tab edge. Outline may vary above notches to allow router/panelization irregularities. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright 1998, Texas Instruments Incorporated