TM497EU9 4194304-WORD BY 9-BIT DYNAMIC RAM MODULE SMMS499A – FEBRUARY 1994 – REVISED JUNE 1995 D D D D D D D D Organization . . . 4 194 304 × 9 Single 5-V Power Supply (±10% Tolerance) 30-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets Utilizes One 4-Megabit and Two 16-Megabit Dynamic RAMs in Plastic Small-Outline J-Lead (SOJ) Packages Long Refresh Period 32 ms† (2048 Cycles) All Inputs, Outputs, and Clocks Fully TTL Compatible 3-State Outputs Performance Ranges: ’497EU9-60 ’497EU9-70 ’497EU9-80 D D D D D ACCESS ACCESS TIME TIME (tRAC) t(AA) (MAX) (MAX) 60 ns 30 ns 70 ns 35 ns 80 ns 40 ns ACCESS READ OR TIME WRITE (tCAC) CYCLE (MAX) (MIN) 15 ns 110 ns 18 ns 130 ns 20 ns 150 ns Common CAS Control for Eight Common Data-In and Data-Out Lines Separate CAS Control for One Separate Pair of Data-In and Data-Out Lines Low Power Dissipation Operating Free-Air Temperature Range 0°C to 70°C Enhanced Page Mode Operation With CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh U SINGLE-IN-LINE PACKAGE ( TOP VIEW ) VCC CAS DQ1 A0 A1 DQ2 A2 A3 VSS DQ3 A4 A5 DQ4 A6 A7 DQ5 A8 A9 A10 DQ6 W VSS DQ7 NC DQ8 Q9 RAS CAS9 D9 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 description The TM497EU9 is a 4M-byte dynamic random-access memory (RAM) organized as 4 194 304 × 9 bits [bit nine (D9, Q9) is generally used for parity and is controlled by CAS9] in a 30-pin leadless single-in-line memory module (SIMM). The SIMM is composed of two TMS417400DJ, 4 194 304 × 4-bit dynamic RAMs, each in a 24/26-lead plastic small-outline J-lead (SOJ) package, and one TMS44100DJ, 4 194 304 × 1-bit dynamic RAM in a 20/26-lead plastic SOJ package, mounted on a substrate with decoupling capacitors. PIN NOMENCLATURE A0 – A10 CAS, CAS9 DQ1 – DQ8 D9 NC Q9 RAS VCC VSS W Address Inputs Column-Address Strobe Data In / Data Out Data In No Connection Data Out Row-Address Strobe 5-V Supply Ground Write Enable The TM497EU9 is available in the U single-sided, leadless module for use with sockets and is characterized for operation from 0°C to 70°C. † A0 – A9 address lines must be refreshed every 16 ms. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TM497EU9 4194304-WORD BY 9-BIT DYNAMIC RAM MODULE SMMS499A – FEBRUARY 1994 – REVISED JUNE 1995 operation The TM497EU9 operates as two TMS417400DJs and one TMS44100DJ connected as shown in the functional block diagram (refer to the TMS417400 and TMS44100 data sheets for details of their operation). The common I/O feature of the TM497EU9 dictates the use of early write cycles to prevent contention on D and Q. refresh The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power. In addition, the ten least significant row addresses ( A0– A9) must be refreshed every 16 ms as required by the TMS44100. power up To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh (RAS-only or CBR) cycle. single-in-line memory module and components PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for socketable devices: Nickel plate and solder plate over copper functional block diagram 11 A0 – A10 RAS CAS W 11 11 CAS9 2 POST OFFICE BOX 1443 4M × 4 A0 – A10 DQ1 RAS DQ2 DQ3 CAS DQ4 W OE 3 6 10 13 DQ1 DQ2 DQ3 DQ4 4M × 4 A0 – A10 DQ1 RAS DQ2 DQ3 CAS DQ4 W OE 16 20 23 25 DQ5 DQ6 DQ7 DQ8 29 26 D9 Q9 4M × 1 A0 – A10 RAS CAS W D Q • HOUSTON, TEXAS 77251–1443 TM497EU9 4194304-WORD BY 9-BIT DYNAMIC RAM MODULE SMMS499A – FEBRUARY 1994 – REVISED JUNE 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX 5 UNIT VCC VIH Supply voltage 4.5 5.5 V High-level input voltage 2.4 6.5 V VIL TA Low-level input voltage (see Note 2) –1 0.8 V 0 70 °C Operating free-air temperature NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH VOL High-level output voltage II Input current (leakage) IO ICC1 ICC2 Low-level output voltage TEST CONDITIONS IOH = – 5 mA IOL = 4.2 mA ’497EU9-60 MIN MAX 2.4 ’497EU9-70 MIN MAX 2.4 ’497EU9-80 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V VCC = 5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ±10 ±10 ±10 µA Output current (leakage) VCC = 5.5 V, CAS high VO = 0 V to VCC, ±10 ±10 ±10 µA Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 325 290 260 mA VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 6 6 6 VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 3 3 3 Standby current mA ICC3 Average refresh current (RAS-only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS-only); RAS low after CAS low (CBR) 325 290 260 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, RAS low, 210 180 150 mA tPC = MIN, CAS cycling NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 TM497EU9 4194304-WORD BY 9-BIT DYNAMIC RAM MODULE SMMS499A – FEBRUARY 1994 – REVISED JUNE 1995 capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) PARAMETER Ci(A) Input capacitance, A0 – A10 Ci(D) Input capacitance, data input (D9) Ci(R) Input capacitance, strobe input (RAS) Ci(C) Input capacitance, capacitance strobe inputs Ci(W) Input capacitance, W Co(DQ) Output capacitance (DQ1 – DQ8) MIN MAX pF 5 pF 21 pF CAS 14 CAS9 7 Co(Q) Output capacitance (Q9) NOTE 5: VCC = 5 V ± 0.5 V, and the bias on pin under test is 0 V. UNIT 15 pF 21 pF 7 pF 7 pF switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’497EU9-60 MIN MAX ’497EU9-70 MIN MAX ’497EU9-80 MIN MAX UNIT tAA tCAC Access time from column address 30 35 40 ns Access time from CAS low 15 18 20 ns tCPA tRAC Access time from column precharge 35 40 45 ns Access time from RAS low 60 70 80 ns tCLZ tOH CAS to output in low-impedance state 0 Output disable time, start of CAS high 3 tOFF Output disable time after CAS high (see Note 6) NOTE 6: tOFF is specified when the output is no longer driven. 4 POST OFFICE BOX 1443 0 • HOUSTON, TEXAS 77251–1443 0 0 3 15 0 ns 3 18 0 ns 20 ns TM497EU9 4194304-WORD BY 9-BIT DYNAMIC RAM MODULE SMMS499A – FEBRUARY 1994 – REVISED JUNE 1995 timing requirements over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’497EU9-60 ’497EU9-70 ’497EU9-80 MIN MIN MIN MAX MAX MAX UNIT tRC tPC Cycle time, random read or write (see Note 7) 110 130 150 Cycle time, page mode read or write (see Notes 7 and 8) 40 45 50 tRASP tRAS Pulse duration, page mode, RAS low 60 100 000 70 100 000 80 100 000 ns Pulse duration, nonpage mode, RAS low 60 10 000 70 10 000 80 10 000 ns tCAS tCP Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns Pulse duration, CAS high 10 10 10 ns tRP tWP Pulse duration, RAS high (precharge) 40 50 60 ns Pulse duration, W low 10 10 10 ns tASC tASR Setup time, column address before CAS low 0 0 0 ns Setup time, row address before RAS low 0 0 0 ns tDS tRCS Setup time, data before CAS low 0 0 0 ns Setup time, W high before CAS low 0 0 0 ns tCWL tRWL Setup time, W low before CAS high 15 18 20 ns Setup time, W low before RAS high 15 18 20 ns tWCS tWRP Setup time, W low before CAS low 0 0 0 ns Setup time, W high before RAS low (CBR refresh only) 10 10 10 ns tCAH tDH Hold time, column address after CAS low 10 15 15 ns Hold time, data after CAS low 10 15 15 ns tRAH tRCH Hold time, row address after RAS low 10 10 10 ns Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH tWCH Hold time, W high after RAS high (see Note 9) 0 0 0 ns Hold time, W low after CAS low 10 15 15 ns tWRH tRHCP Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns Hold time, RAS high from CAS precharge 35 40 45 ns tCHR tCRP Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns Delay time, CAS high to RAS low 5 5 5 ns tCSH tCSR Delay time, RAS low to CAS high 60 70 80 ns tRAD tRAL Delay time, RAS low to column address (see Note 10) 15 Delay time, column address to RAS high 30 35 40 tCAL tRCD Delay time, column address to CAS high 30 35 40 Delay time, RAS low to CAS low (see Note 10) 20 tRPC tRSH Delay time, RAS high to CAS low 0 0 0 Delay time, CAS low to RAS high 15 18 20 tREF tT Refresh time interval Delay time, CAS low to RAS low (CBR refresh only) 5 45 15 20 32 Transition time NOTES: 7. 8. 9. 10. 5 30 3 30 ns 5 35 52 15 20 32 3 ns 30 3 ns 40 ns ns ns 60 ns ns ns 32 ms 30 ns All cycle times assume tT = 5 ns. To assure tPC min, tASC should be ≥ tCP. Either tRRH or tRCH must be satisfied for a read cycle. The maximum value is specified only to assure access time. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TM497EU9 4194304-WORD BY 9-BIT DYNAMIC RAM MODULE SMMS499A – FEBRUARY 1994 – REVISED JUNE 1995 device symbolization TM497EU9 -SS YYMMT YY MM T -SS = = = = Year Code Month Code Assembly Site Code Speed NOTE: The location of the part number may vary. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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