Data sheet acquired from Harris Semiconductor SCHS257 D ENDE M M O S EC IGN NOT R NEW DES ology n Tech FOR January 1997 Features MOS Use C • Buffered Inputs • Typical Propagation Delay: 6.4ns at VCC = 5V, TA = 25oC, CL = 50pF • CD74FCT540 - Inverting • CD74FCT541 - Noninverting • SCR Latchup Resistant BiCMOS Process and Circuit Design • Speed of Bipolar FAST™/AS/S • 64mA Output Sink Current • Output Voltage Swing Limited to 3.7V at VCC = 5V • Controlled Output Edge Rates • Input/Output Isolation to VCC • BiCMOS Technology with Low Quiescent Power CD74FCT540, CD74FCT541 BiCMOS FCT Interface Logic, Octal Buffers/Line Drivers, Three-State Description The CD74FCT540 and CD74FCT541 octal buffers/line drivers use a small geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output HIGH level to two diode drops below VCC. This resultant lowering of output swing (0V to 3.7V) reduces power bus ringing (a source of EMI) and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 64 milliamperes. The CD74FCT540 is a three-state buffer having two active LOW output enables. The CD74FCT541 is a noninverting three state buffer having two active LOW output enables. Ordering Information TEMP. RANGE (oC) PART NUMBER PKG. NO. PACKAGE CD74FCT540E 0 to 70 20 Ld PDIP CD74FCT541E 0 to 70 20 Ld PDIP E20.3 E20.3 CD74FCT540M 0 to 70 20 Ld SOIC M20.3 CD74FCT541M 0 to 70 20 Ld SOIC M20.3 CD74FCT541SM 0 to 70 20 Ld SSOP M20.209 NOTE: When ordering the suffix M and SM packages, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. Pinouts CD74FCT540 (PDIP, SOIC) TOP VIEW CD74FCT541 (PDIP, SOIC, SSOP) TOP VIEW OE1 1 20 VCC OE1 1 A0 2 19 OE2 A0 2 19 OE2 A1 3 18 Y0 A1 3 18 Y0 A2 4 17 Y1 A2 4 17 Y1 A3 5 16 Y2 A3 5 16 Y2 A4 6 15 Y3 A4 6 15 Y3 A5 7 14 Y4 A5 7 14 Y4 A6 8 13 Y5 A6 8 13 Y5 A7 9 12 Y6 A7 9 12 Y6 GND 10 11 Y7 GND 10 11 Y7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a trademark of Fairchild Semiconductor. Copyright © Harris Corporation 1997 8-1 20 VCC File Number 2383.2 CD74FCT540, CD74FCT541 Functional Diagram A0 A1 A2 A3 A0 A1 A2 A3 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 1 OE1 OE2 541 540 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 19 GND = PIN 10 VCC = PIN 20 TRUTH TABLE (Note 1) INPUTS OUTPUTS OE1 OE2 An CD74FCT540 CD74FCT541 L L H L H H X X Z Z X H X Z Z L L L H L NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance IEC Logic Symbol CD74FCT540 1 19 CD74FCT541 1 19 EN EN 2 18 2 18 3 17 3 17 4 16 4 16 5 15 5 15 6 14 6 14 7 13 7 13 8 12 8 12 9 11 9 11 8-2 CD74FCT540, CD74FCT541 Absolute Maximum Ratings Thermal Information DC Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK (For VI < -0.5V) . . . . . . . . . . . . . -20mA DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . . 70mA DC Output Source Current per Output Pin, IO . . . . . . . . . . . . -30mA DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140mA DC Ground Current (IGND). . . . . . . . . . . . . . . . . . . . . . . . . . . 528mA Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC and SSOP-Lead Tips Only) Operating Conditions Operating Temperature Range (TA) . . . . . . . . . . . . . . . .0oC to 70oC Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V DC Input Voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC DC Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ VCC Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Commercial Temperature Range 0oC to 70oC, VCC Max = 5.25V, VCC Min = 4.75V (Note 5) AMBIENT TEMPERATURE (TA) 25oC TEST CONDITIONS PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN 0oC TO 70oC MAX MIN MAX UNITS High Level Input Voltage VIH 4.75 to 5.25 2 - 2 - V Low Level Input Voltage VIL 4.75 to 5.25 - 0.8 - 0.8 V High Level Output Voltage VOH VIH or VIL -15 Min 2.4 - 2.4 - V Low Level Output Voltage VOL VIH or VIL 64 Min - 0.55 - 0.55 V High Level Input Current IIH VCC Max - 0.1 - 1 µA Low Level Input Current IIL GND Max - -0.1 - -1 µA IOZH VCC Max - 0.5 - 10 µA IOZL GND Max - -0.5 - -10 µA Input Clamp Voltage VIK VCC or GND Min - -1.2 - -1.2 V Short Circuit Output Current (Note 3) IOS VO = 0 VCC or GND Max -60 - -60 - mA Quiescent Supply Current, MSI ICC VCC or GND Max - 8 - 80 µA ∆ICC 3.4V (Note 4) Max - 1.6 - 1.6 mA Three State Leakage Current Additional Quiescent Supply Current per Input Pin TTL Inputs High, 1 Unit Load -18 0 NOTES: 3. Not more than one output should be shorted at one time. Test duration should not exceed 100ms. 4. Inputs that are not measured are at VCC or GND. 5. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆ICC limit specified in Static Characteristics Chart, e.g., 1.6mA Max. @ 70oC. 8-3 CD74FCT540, CD74FCT541 Switching Specifications Over Operating Range FCT Series tr, tf = 2.5ns, CL = 50pF, RL (Figure 3) (Note 6) PARAMETER SYMBOL Propagation Delays VCC (V) 25oC 0oC TO 70oC TYP MIN MAX UNITS (Note 6) Data to Outputs CD74FCT540 tPLH, tPHL 5 6.4 2 8.5 ns CD74FCT541 tPLH, tPHL 5 6 2 8 ns Output Disable to Output tPLZ, tPHZ 5 7.1 2 9.5 ns Output Enable to Output tPZL, tPZH 5 7.5 2 10 ns CPD (Note 7) - 37 - - pF - 40 - - pF Power Dissipation Capacitance CD74FCT540 CD74FCT541 Minimum (Valley) VOHV During Switching of Other Outputs (Output Under Test Not Switching) VOHV 5 0.5 - - V Maximum (Peak) VOLP During Switching of Other Outputs (Output Under Test Not Switching) VOLP 5 1 - - V Input Capacitance CI - - - 10 pF Three-State Output Capacitance CO - - - 15 pF NOTES: 6. 5V: Min is at 5.25V for 0oC to 70oC, Max is at 4.75V for 0oC to 70oC, Typ is at 5V. 7. CPD, measured per flip-flop, is used to determine the dynamic power consumption. PD (per package) = VCC ICC + Σ(VCC2 fI CPD + VO2 fO CL + VCC ∆ICC D) where: VCC = supply voltage ∆ICC = flow through current x unit load CL = output load capacitance D = duty cycle of input high fO = output frequency fI = input frequency 8-4 CD74FCT540, CD74FCT541 8-5 Test Circuits and Waveforms VCC tr, tf = 2.5ns (NOTE 8) VI 3V 0 PULSE ZO GEN SWITCH POSITION 7V 500Ω RL V0 DUT CL 50pF RT RT = ZO 500Ω RL SWITCH Closed tPHZ, tPZH, tPLH, tPHL Open DEFINITIONS: CL = Load capacitance, includes jig and probe capacitance. RT = Termination resistance, should be equal to ZOUT of the Pulse Generator. VIN = 0V to 3V. Input: tr = tf = 2.5ns (10% to 90%), unless otherwise specified NOTE: 8. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZOUT ≤ 50Ω; tf, tr ≤ 2.5ns. FIGURE 1. TEST CIRCUIT ENABLE TEST tPLZ, tPZL, Open Drain DISABLE 3V 3V SAME PHASE INPUT TRANSITION 1.5V CONTROL INPUT 1.5V 0V 3.5V OUTPUT NORMALLY LOW SWITCH CLOSED SWITCH OPEN tPHL 3.5V VOH 1.5V 1.5V VOL OUTPUT 0.3V tPZH OUTPUT NORMALLY HIGH tPLH tPLZ tPZL tPHZ 0.3V VOL tPLH tPHL VOH 3V OPPOSITE PHASE INPUT TRANSITION 1.5V 0V 0V 0V 1.5V 0V FIGURE 2. ENABLE AND DISABLE TIMING FIGURE 3. PROPAGATION DELAY VOH OTHER OUTPUTS VOL VOH OUTPUT UNDER TEST VOHV VOLP VOL NOTES: 9. VOLP is measured with respect to a ground reference near the output under test. VOHV is measured with respect to VOH. 10. Input pulses have the following characteristics: PRR ≤ 1MHz, tr = 2.5ns, tf = 2.5ns, skew 1ns. 11. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and probes require 700MHz bandwidth. FIGURE 4. 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